Datasheet SST32HF401-70-4C-L3K, SST32HF202-90-4E-L3K, SST32HF202-90-4C-L3K, SST32HF202-70-4E-L3K, SST32HF202-70-4C-L3K Datasheet (Silicon Storage Technology)

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

SST32HF201 / 202 / 401 / 4022Mb Flash + 1Mb SRAM, 2Mb Flash + 2Mb SRAM,

4Mb Flash + 1Mb SRAM, 4Mb Flash + 2Mb SRAM (x16) MCP ComboMemories

FEATURES:

Preliminary Specifications

• MPF + SRAM ComboMemory

– SST32HF201: 128K x16 Flash + 64K x16 SRAM – SST32HF2 02: 128K x16 Flash + 128K x16 SRAM – SST32HF401: 256K x16 Flash + 64K x16 SRAM – SST32HF4 02: 256K x16 Flash + 128K x16 SRAM

• Single 2.7-3.3V Read and Write Operations

• Concurrent Operation

– Read from or write to SRAM while

Erase/Program Flash

• Superior Reliability

– Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention

• Low Power Consumption:

– Active Current: 15 mA (typical) for

Flash or SRAM Read

– Standby Current: 20 µA (typical)

• Flexible Erase Capability

– Uniform 2 KWord sectors – Uniform 32 KWord size blocks

• Fast Read Access Times:

– Flash: 70 and 90 ns – SRAM: 70 and 90 ns

• Latched Address and Data for Flash

• Flash Fast Erase and Word-Program:

– Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 70 ms (typical) – Word-Program Time: 14 µs (typical) – Chip Rewrite Time:

SST32HF201/202: 2 seconds (typical) SST32HF401/402: 4 seconds (typical)

• Flash Automatic Erase and Program Timing

– Internal V

Generation

PP

• Flash End-of-Write Detection

– Toggle Bit – Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard Command Set

• Conforms to Flash pinout

• Package Available

– 48-ball LFBGA (6mm x 8mm)

PRODUCT DESCRIPTION

The SST32HF2 0x /4 0 x C om boM em ory devices integrate a 128K x16 or 256K x16 CMOS fla sh memor y bank with a 64K x16 or 128K x16 CMO S SRAM memory bank in a Multi-Chip Package (MCP), manufactured with SST’s proprietary , high performance SuperFlash technology .

Featuring high performance Word-Program, the flash memory bank provides a maximum Word-Program time of 14 µsec. The entire flash memory bank can be erased and programmed word-by-word in typi cally 2 seconds for the SST32HF201/202 and 4 seconds for the SST32HF40 1/ 40 2, when us ing interface features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent flash write, the SST32HF20x/40 x devices contain o n-chip hardware and software data protection schemes.The SST32HF20x/40x devices offer a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years.

The SST32HF20x/40x devices consist of two independent memory ban ks with respective bank enable signals. The Flash and SRAM memory banks are superimposed in the same memor y ad dress spac e. Both m emory banks sha re common address lines, data lines, WE# and OE#. The memory ban k selection is do ne by memory bank en able signals. The S RAM ban k enable signa l, BES # sele cts th e

SRAM bank. The flash memory bank enable signal, BEF# selects the flash mem ory bank. The W E# signa l has to be used with Software Data Protection (SDP) command sequence when controlling the Eras e an d P r ogram ope rations in the flash memory bank. The SDP command sequence protects the data stored in the flash memory bank from accidental alteration.

The SST32HF20x/40x provide the added functionality of being able to simultaneously read from or write to the SRAM bank while erasing or programming in the flash memory ban k. The SRAM memo ry bank can be read or written while the flash memory bank performs SectorErase, Bank-Erase, or Word-Program concurrently. All flash memory Erase and Program operations will automatically latch the input address and data signals and complete the operation in ba ckground without fur ther in put stimulus requirement. On ce the internall y controlled Erase or Program cycle in the fla sh bank has c ommenced , the SRAM bank can be accessed for Read or Write.

The SST32HF20x/40 x devices are suited for applications that use both flash memory and SRAM memory to store code or data. For systems requiring low power and s mall form factor, the SST32HF20x/40x devices significantly improve performance and r eliability, while lowering power

1

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF and ComboMemory are trademarks of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

consumption, when compared w ith multiple chip so lu tions. The SST32HF20x/40x inherently use less energy during erase and program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shor ter erase time, the to tal energy consumed during any Erase or Program operation is less than alternative flash technologies.

The SuperFlash technolog y pro vides f ixed Erase and Program times, independent of the n umbe r of Er ase/Prog r am cycles that have occurred. Therefore the system software or hardware does not hav e to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.

Device Operation

The ComboMemory uses BES# and BEF# to control operation of either the SRAM or the flash memory bank. When BES# is low, the SRAM Bank is activated for Read and Write operatio n. When BEF# is l ow the flash b ank is act ivated for Read, Program or Erase operation. BES# and BEF# cannot be at low level at the same time. If BES# and BEF# are both asserted to low level bus contention will result and the device may suffer permanent damage. A ll address, data, and control lines are shared by SRAM Bank and flash bank whi ch minimizes power consumption and loading. The device goes into standby when both bank enables are high.

SRAM Operation

With BES# low and BEF# high, the SST32HF201/401 operate as 64K x16 CMOS SRAM, and the SST32HF202/ 402 operates as 12 8K x16 CMOS SRAM, wit h fully stat ic operation requiring no external clocks or timing strobes. The SST32HF201/40 1 SRAM is mapp ed into the fi rst 64 KWord address space of the device, and the SST32HF202/402 SRAM is mapped into the first 128 KWord address space. When BES# and BEF# are high , both memor y ba nks a re dese le cted a nd the d evice enter s standby mode. Read and Write cycle times are equal. The control signals UBS# and LBS# provide access to the upper data byte and lower data byte. See T able 3 for SRAM read and write data byte control modes of operation.

control and is used to gate data fr om the outpu t pins. The data bus is in high impedance state when OE# is high. See Figure 2 for the Read cycle timing diagram.

SRAM Write

The SRAM Write operation of the SST32HF20x/40x is controlled by WE# and BE S#, bot h have to be low for the system to write to the SRAM. During the Word-Write operation, the addres ses and d ata are referenced to the ris ing edge of either BES# or WE#, whi chever occurs first. The write time is measured from the last falling edge to the first rising edge of BES# or W E#. See F igures 3 a nd 4 for the Write cycle timi ng diag ram s.

Flash Operation

With BEF# acti ve, the S ST3 2HF2 01/202 operate as 1 28K x16 flash memor y and the S ST32HF401/ 402 operat es as 256K x16 flash m emory. The flash memory bank i s read using the common address lines, data lines, WE# and OE#. Erase and Program operations are initiated with the JEDEC standard SDP command sequences. Address and data are latched during the SDP commands and during the internally timed Erase and Program operations.

Flash Read

The Read operation of the SST32HF20x/40x devices is controlled by BEF# and OE#. Both have to be low, with WE# high, for the system to obtain data from the outputs. BEF# is used for flash memory bank selection. When BEF# and BES# are high, both banks are deselected and only standby power is consumed. OE# is the output control and is used to gate d ata from the ou tput pins. The data bus is in high impedance state when OE# is high. Ref er to Figure 5 for further details.

Flash Erase/Program Operation

SDP commands are used to initiate the flash memory bank Program and Erase operation s of the SST32HF20x/40x. SDP commands are loaded to the flash memory bank using standard microprocess or write sequences. A command is loaded by asserting WE# low while keeping BEF# low and OE# high. The a ddress is latched on the falling edge of WE# or BEF#, wh ichever occurs last. The dat a is latched on the rising edge of WE# or BEF#, whichever occurs first.

SRAM Read

The SRAM Read operation of the SST32HF20x/40x is controlled by OE# and BES#, both have to be low with WE# high for the system to obtain data fr om the outputs. BES# is used for SRAM bank se le ction. OE# is the ou tpu t

Flash Word-Program Operation

The flash memory bank of the SST32HF20x/40x devices is programmed on a word-by-word basis. Before Program operations, the memory must be erased first. The Program

2

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications operation consists of three steps. The first step is the three-

byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addr esses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initiated, will be completed, within 20 µs. See Figures 6 and 7 for WE# and BEF# controlled Program operation timing diagrams and Figure 17 for flowcharts. During the Program operation, the only valid flash Read operations are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any SDP commands loaded during the internal Program operation will be ignored.

Flash Sector/Block-Erase Operation

The Flash Sector/Block-Erase operation allows the system to erase the device on a sector-by-sector (or block-byblock) basis. The SST32HF20x/40x offer both SectorErase and Block-Erase mode. The sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The Sector-Erase op eration is init iated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The address lines A

, for SST32HF201/202, and A17-A11, for

16-A11

SST32HF401/402, are used to determine the sector address. The Block-Erase operation is initiated by executing a six-byte command se quence with Block-E rase command (50H) and block addres s (BA) in the last bus cycle. The address lines A

, for SST32HF401/402, are used to determine the block

A

15

, for SST32HF201/202, and A17-

16-A15

address. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The inter nal Erase operatio n begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 11 and 12 for timing waveforms. Any commands issued during the Sec tor- or B l ock-Era se op eration are ignored.

Flash Chip-Erase Operation

The SST32HF20x/40x provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1” state. This is useful when the entir e de vice must be quickly erased.

The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Eras e operation begins with the rising edge of the sixt h WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is T oggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 9 for timing diagram, and Figure 20 for the flowchart. Any commands issued during the Chip-Erase operation are ignored.

Write Operation Status Detection

The SST32HF20x/40x provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the syste m Write cycle time. The software detection includes two status bits: Data# Polling

) and Toggle Bit (DQ6). The End-of-Write detection

(DQ

7

mode is enabled after the r ising edge of WE#, which in itiates the internal Program or Erase operation.

The actual comple tion of the n onvolatile write is as ync hronous with the sys tem; therefore, either a Data# Polling or Toggle Bit read may be simultaneou s with the compl etion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either D Q

or DQ6. In order to prevent spurio us

7

rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If bo th reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

Flash Data# Polling (DQ7)

When the SST32HF20x/40x flash memory banks are in the internal Pr ogram operation, any attempt to read DQ will produce the co mplement of the true data. Once th e Program operation is completed, DQ data. Note that even though DQ immediately following the completion of an inter nal Write operation, the remai ning data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycl es, after an inter val of 1 µs. During internal Erase operation, any attempt to read DQ duce a ‘0’. Once the internal Erase operation is completed,

will produce a ‘1’. The Da ta# Polling is valid a fter the

DQ

7

rising edge of the fourth WE# (or BEF#) pulse for Program operation. For Sector- or Blo ck-Erase, the Da ta# Polling is valid after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 8 for Data# Polling timing diagram and Figure 18 for a flowchart.

will produce true

7

may have valid data

7

will pro-

7

3

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

Flash Toggle Bit (DQ6)

During the inter nal Program or Erase ope ration, any consecutive attempts to read DQ

will produce alternating ‘1’s

6

and ‘0’s, i.e., toggling between 1 and 0. Whe n the inte r nal Program or Erase operation is com plete d, t he tog gling wi ll stop. The flash memor y bank is then ready for the next operation. The T oggle Bit is valid after the rising edge of the fourth WE# (or BEF#) pulse for Program operation. For Sector- or Bank-Er ase, t he Toggle Bit is v alid af ter the rising edge of the sixth WE# (or BEF#) pulse. See Figur e 9 for Toggle Bit timing diagram and Figure 18 for a flowchart.

Flash Memory Data Protection

The SST32HF20x/40x flash memory bank provides both hardware and software features to protec t nonvolatile data from inadvertent writes.

Flash Hardware Data Protection

Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle.

Power Up/Down Detection: The Write operation is

V

DD

inhibited when V Write Inhibi t Mode:

high will inhibit the Flash Write operation. This prevents inadvertent writes during power-up or power-down.

is less than 1.5V.

DD

Forcing OE# low, BEF# high, or WE #

ONCURRENT READ/WRITE STATE TABLE

C

Flash SRAM

Program/Erase Read Program/Erase Write

The device will ig nore a ll S DP c omma nds when an Era se or Program operation is in progress. Note that Product Identification comman ds use SDP; therefore, these commands will also be ignored while an Erase or Program operation is in progress.

Product Identification

The Product Id entification mode ide ntifies the devices as the SST32HF20x/40x and manufacturer as SST. This

mode may be accessed by software operations only. The hardware device ID Read operation, which is typically used by programmers, cannot be used on this device because of t he sh ar ed lin es be twe en fla sh and SRAM in the multi-chip package. Therefore, application of high voltage to pin A

Users may use the software P roduct Identifica tion operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Tables 3 and 4 for software operation, Figure 13 for the software ID entry and Read timing diagram, and Figure 19 for the ID entry command sequence flowchart.

may damage this device.

9

Flash Software Data Protection (SDP)

The SST32HF20x /40x provide t he JEDEC app roved software data protection scheme for all flash memory bank data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadver tent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte load sequence. The SST32HF20x/40x devices are shipped with the software data protection pe rmanently e nabled. See Ta ble 4 for the specific software command codes. During SDP command sequence, invalid SDP comma nds wil l abor t the device t o the read mode, within Read Cycle Time (T

RC

).

Concurrent Read and Write Operations

The SST32HF20x/40x provide the unique benefi t of being able to read from or write to S RAM, while simultaneously erasing or programming the Flash. This allows data alteration code to be executed from SRAM, while altering the data in Flash. The following table lists all valid states.

TABLE 1: PRODUCT IDENTIFICATION

Address Data

Manufacture r’s ID 0000H 00BFH Device ID

SST32HF201/202 0001H 2789H SST32HF401/402 0001H 2780H

T1.0 557

Product Identification Mode Exit/Reset

In order to retur n to the sta nda rd r ead mod e, the So ftwar e Product Identification mode must be exited. Exiting is accomplished by issuing the Exit ID command sequence, which returns the device to the Read operation. Please note that the software-reset command is ignored during an internal Pr ogram or Erase op eration. See Table 4 for software command cod es, Figur e 14 for timin g waveform and Figure 19 for a flowchart.

Design Considerations

SST recommends a high frequency 0.1 µF ceramic capacitor to be plac ed as close as possible between V

, e.g., less than 1 cm away from the VDD pin of the

V

SS

DD

and

4

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications device. Additionally, a low frequency 4.7 µF electrolytic

capacitor from V

DD

pin.

the V

FUNCTIONAL BLOCK DIAGRAM

to VSS should be placed within 1 cm of

DD

AMS-A

Address Buffers

SRAM

UBS#

LBS#

BES#

0

BEF#

OE#

Control Logic

I/O Buffers

DQ15 - DQ

DQ7 - DQ

8

0

WE#

Address Buffers

& Latches

TOP VIEW (balls facing down)

SST32HF201/202

6

A13

A12

A14

A15

A16

USB#

5 4 3 2 1

A9

WE#

BES#

A7

A3

A8

NC

A4

A10

LBS#

NC

A6

A2

A11

NC

A5

A1

DQ7

DQ5

DQ2

DQ0

A0

DQ14

DQ12

DQ10

DQ8

BEF#

DQ15

DQ13

V

DD

DQ11

DQ9

OE#

V

DQ6

DQ4

DQ3

DQ1

V

SS

A B C D E F G H

SuperFlash

Memory

557 ILL F01a.0

557 ILL B1.0

TOP VIEW (balls facing down)

SST32HF401/402

6

A13

A12

A14

A15

A16

USB#

5 4 3 2 1

A9

WE#

BES#

A7

A3

A8

NC

A17

A4

A10

LBS#

NC

A6

A2

A11

NC

A5

A1

DQ7

DQ5

DQ2

DQ0

A0

DQ14

DQ12

DQ10

DQ8

BEF#

DQ15

DQ13

V

DD

DQ11

DQ9

OE#

V

DQ6

DQ4

DQ3

DQ1

V

SS

557 ILL F01b.0

A B C D E F G H

FIGURE 1: P

IN ASSIGNMENTS FOR 48-BALL LFBGA

5

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

1

-A

A

MS

-DQ0Data Input/output T o output data during Read cycles and receive input data during Write cycles.

DQ

15

BES# SRAM Memory Bank Enable To activate the SRAM memory bank when BES# is low. BEF# Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. V

DD

V

SS

UBS# Upper Byte Control (SRAM) To enable DQ15-DQ LBS# Lower Byte Control (SRAM) To enable DQ7-DQ NC No Connection Unconnected Pins

1. AMS = Most significant address

Address Inputs To provide flash addresses, A16-A0 for 2M and A17-A0 for 4M.

0

To pr ovide SRAM addresses, A

for 1M and A16-A0 for 2M.

15-A0

Data is internally latched during a flash Erase/Program cycle. The outputs are in tri-state when OE# or BES# and BEF# are high.

Power Supply 2.7-3.3V power supply Ground

8

0

T2.0 557

TABLE 3: OPERATION MODES SELECTION

Mode BES#

Not Allowed V Flash

Read V Program V Erase X V

SRAM

Read V

Write V

Standby V Flash Write Inhibit X X V

Output Disable V

Product Identification

Software Mode V

1. Do not apply BES#=VIL and BEF#=VIL at the same time

2. X can be VIL or VIH, but no other value.

3. Device ID for: SST32HF201/202 = 2789H and SST32HF401/402 = 2780H

4. AMS = Most significant flash address

1

BEF#1OE# WE# UBS# LBS# DQ15 to DQ8DQ7 to DQ

2

X

XXX X X X

V

IL

V

IH

V

IH

V

IL

V

IL

V

IL

XVILV XVILV XVILV

XX D

IH

XX D

IL

X X X X Sector or Block address,

IL

V

IH IH IH

IL

V

IL

V

IH IL IL IH

X X X X High Z High Z X

XXXHigh Z / D

IL

V V

IL

IH IH

IL IL IL IL IL IL

IHC

V

IL

V

IL

V

IL IL

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

V

IHC

XXXVIHXXHigh Z / D XV

V

IH

V V

V

IL

V

IL

V

IH

XX X XHigh Z / D

IH

V

IL IH IH

IL

V

IH

XXVIHV

V

IH

V

IL

X X High Z High Z X

IH

X X High Z High Z X

IH

X X Manufacturer’s ID (00BFH)

IH

Address

A

IN

A

IN

OUT

IN

0

D

OUT

D

IN

XXH for Chip-Erase

V

IL

V

IH

V

IL

V

IL

V

IH

V

IL

IH

D

OUT

D

OUT

High Z D

D

IN

D

IN

High Z D

OUT OUT OUT

D

OUT

High Z A

OUT

D

IN

High Z A

IN

High Z / D High Z / D High Z / D

OUT OUT OUT

A

A A

A

High Z High Z X

4

A

-A1=VIL, A0=V

Device ID

3

MSF

(See Table 4)

IN IN IN IN IN IN

X X X

IH

T3.2 557

6

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command Sequence

Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BA Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Software ID Entry

4,5

Software ID Exit XXH F0H Software ID Exit 5555H AAH 2AAAH 55H 5555H F0H

1. Address format A14-A0 (Hex),Address A15 can be VIL or VIH, but no other value, for the Command sequence.

2. WA = Program Word address

3. SA

for Sector-Erase; uses AMS-A11 address lines

X

BA

for Block-Erase; uses AMS-A15 address lines

X

= Most significant address

A

MS

= A16 for SST32HF201/202 and A17 for SST32HF401/402

A

MS

4. The device does not remain in Software Product ID mode if powered down.

5. With A

= 0; SST Manufacturer’s ID = 00BFH, is read with A0 = 0,

MS-A1

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data

2

Data

3

X

3

X

5555H AAH 2AAAH 55H 5555H 90H

SST32HF201/202 Device ID = 2789H, is read with A SST32HF401/402 Device ID = 2780H, is read with A

0 0

= 1, = 1.

30H 50H

T4.1 557

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause pe r manent dama ge to the device. This is a stres s rating only and funct ional operatio n of the device at these conditions or conditions greater tha n those defined in the ope rational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to V

DD DD

+0.3V

+2.0V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Lead Soldering Temperature (3 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

1

Output Short Circ uit Curr ent

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE

Range Ambient Temp V

Commercial 0°C to +70°C 2.7-3.3V Extended -20°C to +85°C 2.7-3.3V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

AC CONDITIONS OF TEST

DD

Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF

See Figures 15 and 16

7

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

TABLE 5: DC OPERATING CHARACTERISTICS (VDD = V

Limits

Symbol Parameter

I

I I I V V V V V V V

DD

SB LI LO

IL IH IHC OLF OHF OLS OHS

Power Supply Current Address input=VIL/VIH, at f=1/TRC Min,

Read

Flash

SRAM 20 mA BEF#=VIH, BES#=V Concurrent Operation 45 mA BEF#=VIH, BES#=V Write

Flash 25 mA

SRAM 20 mA BEF#=VIH, BES#=V Standby VDD Current 30 µA VDD=VDD Max, BEF#=BES#=V Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max Output Leakage Current 1 µA V Input Low Voltage 0.8 V VDD=VDD Min Input High Voltage 0.7 V

DD

Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max Flash Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min Flash Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min Output Low Voltage 0.4 V IOL=1 mA, VDD=VDD Min Output High Voltage 2.2 V IOH=-500 µA, VDD=VDD Min

AND V

DDF

20 mA

VVDD=VDD Max

= 2.7-3.3V)

DDS

Test ConditionsMin Max Units

DD=VDD

Max, all DQs open

, WE#=V

IL

V OE#=V

BEF#=VIL, BES#=V

WE#=V

IL

BEF#=VIL, BES#=V

=GND to VDD, VDD=VDD Max

OUT

IH

IL IL

OE#=V

IH,

IL

IH

IHC

T5.1 557

TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

T T

1

PU-READ PU-WRITE

1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs Powe r-up to Program/Erase Operation 100 µs

TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

1

C

I/O

1

C

IN

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance V

= 0V 24 pF

I/O

Input Capacitance VIN = 0V 12 pF

TABLE 8: FLASH RELIABILI TY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

1

N

END

1

T

DR

1

I

LTH

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117 Data Retention 100 Years JEDEC Standard A103 Latch Up 100 + I

DD

mA JEDEC Standard 78

T6.0 557

T7.0 557

T8.0 557

8

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

AC CHARACTERISTICS

TABLE 9: SRAM READ CYCLE TIMING PARAMETERS

SST32HF201/202/401/402-70 SST32HF201/202/401/402-90

Symbol Parameter

T

RCS

T

AAS

T

BES

T

OES

T

BYES

T

BLZS

T

OLZS

T

BYLZS

T

BHZS

T

OHZS

T

BYHZS

T

OHS

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Read Cycle Time 70 90 ns Address Access Time 70 90 ns Bank Enable Access Time 70 90 ns Output Enable Access Time 35 45 ns UBS#, LBS# Access Time 70 90 ns

1

BES# to Active Output 0 0 ns

1

Output Enable to Active Output 0 0 ns

1

UBS#, LBS# to Active Output 0 0 ns

1

BES# to High-Z Output 25 35 ns

1

Output Disable to High-Z Output 0 25 0 35 ns

1

UBS#, LBS# to High-Z Output 35 45 ns

Output Hold from Address Change 10 10 ns

UnitsMinMaxMinMax

T9.0 557

TABLE 10: SRAM WRITE CYCLE TIMING PARAMETERS

SST32HF201/202/401/402-70 SST32HF201/202/401/402-90

Symbol Parameter

T

WCS

T

BWS

T

AWS

T

ASTS

T

WPS

T

WRS

T

BYWS

T

ODWS

T

OEWS

T

DSS

T

DHS

Write Cycle Time 70 90 ns Bank Enable to End-of-Write 60 80 ns Address Valid to End-of-Write 60 80 ns Address Set-up Time 0 0 ns Write Pulse Width 60 80 ns Write Recovery Time 0 0 ns UBS#, LBS# to End-of-Write 60 80 ns Output Disable from WE# Low 30 40 ns Output Enable from WE# High 0 0 ns Data Set-up Time 30 40 ns Data Hold from Write Time 0 0 ns

UnitsMin Max Min Max

T10.0 557

9

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

TABLE 11: FLASH READ CYCLE TIMING PARAMETERS

SST32HF201/202/401/402-70 SST32HF201/202/401/402-90

Symbol Parameter

T

RC

T

BE

T

AA

T

OE

T

BLZ

T

OLZ

T

BHZ

T

OHZ

T

OH

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Read Cycle Time 70 90 ns Bank Enable Access Time 70 90 ns Address Access Time 70 90 ns Output Enable Access Time 35 45 ns

1

BEF# Low to Active Output 0 0 ns

1

OE# Low to Active Output 0 0 ns

1

BEF# High to High-Z Output 20 30 ns

1

OE# High to H igh-Z Output 20 30 ns

1

Output Hold from Address Change 0 0 ns

TABLE 12: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

T T T T T T T T T T T T T T T T T

BP AS AH

BS

BH OES OEH

BPW

WP

WPH

BPH

DS

DH

IDA

SE

BE

SCE

Word-Program Time 20 µs Address Setup Time 0 ns Address Hold Time 30 ns WE# and BEF# Setup Time 0 ns WE# and BEF# Hold Time 0 ns OE# High Setup Time 0 ns OE# High Hold Time 10 ns BEF# Pulse Width 40 ns WE# Pulse Width 40 ns WE# Pulse Width High 30 ns BEF# Pulse Width High 30 ns Data Setup Time 30 ns Data Hold Time 0 ns Software ID Access and Exit Time 150 ns Sector-Erase 25 ms Block-Erase 25 ms Chip-Erase 100 ms

UnitsMin Max Min Max

T11.0 557

T12.0 557

10

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

T

RCS

ADDRESSES A

MSS-0

BES#

T

BLZS

T

AAS T

BES

OE#

T

OLZS

UBS#, LBS#

T

BYLZS

DQ

15-0

Note: WE# remains High (VIH) for the Read cycle A

= Most Significant SRAM Address

MSS

FIGURE 2: SRAM READ CYCLE TIMING DIAGRAM

T

OES

T

BYES

T

WCS

DATA VALID

T

OHS

T

BHZS

T

OHZS

T

BYHZS

557 ILL F02.0

ADDRESSES A

UBS#, LBS#

DQ

15-8, DQ7-0

MSS-0

T

ASTS

WE#

T

BWS

BES#

T

BYWS

T

ODWS

NOTE 2

Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.

2. If BES# goes Low coincident with or after WE# goes Low, the output will remain at high impedance. If BES# goes High coincident with or before WE# goes High, the output will remain at high impedance. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.

T

AWS

T

WPS

T

DSS

VALID DATA IN

T

FIGURE 3: SRAM WRITE CYCLE TIMING DIAGRAM (WE# C ONTROLLED)

WRS

T

DHS

T

1

OEWS

NOTE 2

557 ILL F03.1

11

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

T

WCS

ADDRESSES A

MSS-0

T

WPS

WE#

T

BWS

BES#

T

AWS

T

ASTS

UBS#, LBS#

DQ

15-8, DQ7-0

Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.

2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.

NOTE 2

T

BYWS

T

DSS

T

WRS

T

DHS

VALID DATA IN

FIGURE 4: SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROL LED)

NOTE 2

557 ILL F04.0

1

T

AA

T

OHZ

T

OH

BHZ

HIGH-Z

DATA VALIDDATA VALID

557 ILL F05.0

ADDRESSES A

MSF-0

BEF#

OE#

WE#

DQ

15-0

IH

HIGH-Z

A

= Most Significant Flash Address

MSF

T

OLZV

BLZ

T

RC

T

BE

T

OE

FIGURE 5: FLASH READ CYCLE TIMING DIAGRAM

12

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

INTERNAL PROGRAM OPERATION STARTS

ADDRESSES A

MSF-0

WE#

BEF#

DQ

T

OE#

15-0

5555 2AAA 5555 ADDR

T

AH

T

WP

AS

T

WPH

T

CH

T

CS

XXAA XX55 XXA0 DATA

SW0 SW1 SW2

A

= Most Significant Flash Address

MSF

Note: X can be VIL or VIH, but no other value

T

DS

WORD

(ADDR/DATA)

T

DH

T

BP

557 ILL F06.0

FIGURE 6: FLASH WE# CONTROLLE D PROGRAM CYCLE TIMING DIAGRAM

INTERNAL PROGRAM OPERATION STARTS

ADDRESSES A

MSF-0

BEF#

DQ

OE#

WE#

15-0

T

A Note: X can be VIL or VIH, but no other value

5555 2AAA 5555 ADDR

T

AH

T

CP

AS

= Most Significant Flash Address

MSF

T

CPH

T

CS

XXAA XX55 XXA0 DATA

SW0 SW1 SW2

T

CH

T

DS

WORD

(ADDR/DATA)

T

DH

T

BP

557 ILL F07.0

FIGURE 7: BEF# CONTROL LED FLASH PROGRAM CYCLE TIMING DIAGRAM

13

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

ADDRESSES A

MSF-0

BEF#

OE#

WE#

DQ

T

OEH

T

7

A

MSF

Data Data# Data# Data

= Most Significant Flash Address

FIGURE 8: FLASH DATA# POLLING TIMING DIAGRAM

CE

OE

T

OES

557 ILL F08.0

ADDRESSES A

MSF-0

T

BE

BEF#

T

OEH

T

OET

OES

OE#

WE#

DQ

6

A

= Most Significant Flash Address

MSF

TWO READ CYCLES

WITH SAME OUTPUTS

557 ILL F09.0

FIGURE 9: FLASH TOGGLE BIT TIMING DIAGRAM

14

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

SIX-BYTE CODE FOR CHIP-ERASE

T

SCE

ADDRESS A

MSF-0

5555 2AAA 2AAA5555 5555

CE#

OE#

T

WP

WE#

DQ

15-0

XX55 XX10XX55XXAA XX80 XXAA

SW0 SW1 SW2 SW3 SW4 SW5

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 12) X can be VIL or VIH, but no other value

A

= Most Significant Flash Address

MSF

FIGURE 10: WE# CONTROLLED FLASH CHIP-ERASE TIMING DIAGRAM

5555

557 ILL F10.0

SIX-WORD CODE FOR SECTOR-ERASE

ADDRESSES A

MSF-0

BEF#

DQ

OE#

WE#

15-0

5555 2AAA 2AAA5555 5555

T

WP

XX55 XX30XX55XXAA XX80 XXAA

SW0

Note: The device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are

SW1 SW2 SW3 SW4 SW5

interchangeable as long as minimum timings are met. (See Table 12) X can be VIL or VIH, but no other value SAX = Sector Address A

= Most Significant Flash Address

MSF

FIGURE 11: WE# CONTROLLED FLASH SECTOR-ERASE TIMING DIAGRAM

SA

T

SE

X

557 ILL F11.0

15

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

T

SIX-WORD CODE FOR BLOCK-ERASE

SBE

ADDRESSES A

MSF-0

BEF#

WE#

DQ

OE#

15-0

5555 2AAA 2AAA5555 5555

T

WP

XX55 XX50XX55XXAA XX80 XXAA

SW0 SW1 SW2 SW3 SW4 SW5

Note: The device also supports BEF# controlled Block-Erase operation. The WE# and BEF# signals are

interchangeable as long as minimum timings are met. (See Table 12) X can be VIL or VIH, but no other value BAX = Block Address A

= Most Significant Flash Address

MSF

FIGURE 12: WE# CONTROLLED FLASH BLOCK-ERASE TIMING DIAGRAM

THREE-WORD SEQUENCE FOR

SOFTWARE ID ENTRY

BA

X

557 ILL F12.0

ADDRESS A

14-0

5555 2AAA 5555 0000 0001

BEF#

OE#

T

WP

IDA

WE#

T

DQ

15-0

WPH

XX55XXAA XX90

T

AA

00BF

DEVICE ID

SW0 SW1 SW2 MFG ID

Note: X can be VIL or VIH, but no other value Device ID = 2789H for SST32VF201/202 and

2780H for SST32VF401/402

557 ILL F13.0

FIGURE 13: SOFTWARE ID ENTRY AND READ

16

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

THREE-WORD SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

ADDRESS A

DQ

14-0

15-0

BEF#

OE#

WE#

5555 2AAA 5555

XXAA XX55 XXF0

T

WP

T

WHP

SW0 SW1 SW2

Note: X can be VIL or VIH, but no other value

FIGURE 14: SOFTWARE ID EXIT AND RESET

T

IDA

557 ILL F14.0

17

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

V

IHT

V

ILT

AC test inputs are driven at V for inputs and outputs are V

V

IT

(0.9 VDD) for a logic “1” and V

IHT

(0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

IT

REFERENCE POINTS OUTPUTINPUT

FIGURE 15: AC INPUT/OUTPUT REFERENCE WAVEFORMS

TO DUT

V

OT

557 ILL F15.0

(0.1 VDD) for a logic “0”. Measurement ref erence points

IL T

Note: V

- V

INPUT

OUTPUT

INPUT

Test

HIGH Test

LOW Test

IT

V

OT

V

IHT

V

ILT

TO TESTER

557 ILL F16.0

FIGURE 16: A TEST LOAD EXAMPLE

C

L

18

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

Start

Write data: XXAAH

Address: 5555H

Write data: XX55H

Address: 2AAAH

Write data: XXA0H

Address: 5555H

X can be VIL or VIH, but no other value.

FIGURE 17: WORD-PROGRAM ALGORITHM

Write Word

Address/Word

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

557 ILL F17.0

19

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

Internal Timer

Program/Erase

Initiated

Wait TBP,

T

SCE, or TBE

Program/Erase

Completed

No

Toggle Bit

Program/Erase

Initiated

Read word

Read same

word

Does DQ

6

match?

Yes

No

Data# Polling

Program/Erase

Initiated

Read DQ

7

Is DQ7 =

true data?

Yes

Program/Erase

Completed

Program/Erase

Completed

557 ILL F18.0

FIGURE 18: WAIT OPTIONS

20

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

Software Product ID Entry

Command Sequence

Write data: XXAAH

Address: 5555H

Write data: XX55H

Address: 2AAAH

Write data: XX90H

Address: 5555H

Wait T

IDA

Read Software ID

Software Product ID Exit &

Reset Command Sequence

Write data: XXAAH

Address: 5555H

Write data: XX55H

Address: 2AAAH

Write data: XXF0H

Address: 5555H

Wait T

IDA

Return to normal

operation

Write data: XXF0H

Address: XXXXH

Wait T

IDA

Return to normal

operation

557 ILL F19.0

X can be VIL or VIH, but no other value.

FIGURE 19: SOFTWARE PRODUCT COMMAND FLOWCHARTS

21

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

Chip-Erase

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Sector-Erase

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Block-Erase

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX10H

Address: 5555H

Wait T

SCE

Chip erased

to FFFFH

Load data: XX30H

Address: SA

Wait T

X

SE

Sector erased

to FFFFH

X can be VIL or VIH, but no other value.

Load data: XX50H

Address: BA

Wait T

X

BE

Block erased

to FFFFH

557 ILL F20.0

FIGURE 20: ERASE COMMAND SEQUENCE

22

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

Concurrent

Operation

Load SDP Command

Sequence

Flash

Program/Erase

Initiated

Wait for End of Write Indication

Flash Operation

Completed

End Concurrent

Operation

FIGURE 21: CONCURRENT OPERATION FLOWCHART

Read or Write

SRAM

End

Wait

557 ILL F21.0

23

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

PRODUCT ORDERING INFORMATION

Device Speed Suffix1 Suffix2

Preliminary Specifications

SST32

HFxxx -XXX -XX -XX

Package Modifier

K = 48 balls

Package Type

L3 = LFBGA (6mm x 8mm x 1.4mm)

T emperature Range

C = Commercial = 0°C to +70°C E = Extended = -20°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns 90 = 90 ns

Density

201 = 2 Mbit Flash + 1 Mbit SRAM 202 = 2 Mbit Flash + 2 Mbit SRAM 401 = 4 Mbit Flash + 1 Mbit SRAM 402 = 4 Mbit Flash + 2 Mbit SRAM

Voltage

H = 2.7-3.3V

Device Family

32 = MPF + SRAM ComboMemory

24

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

Valid combinations for SST32HF201

SST32HF201-70-4C-L3K SST32HF201-70-4E-L3K

SST32HF201-90-4C-L3K SST32HF201-90-4E-L3K

Valid combinations for SST32HF202

SST32HF202-70-4C-L3K SST32HF202-70-4E-L3K

SST32HF202-90-4C-L3K SST32HF202-90-4E-L3K

Valid combinations for SST32HF401

SST32HF401-70-4C-L3K SST32HF401-70-4E-L3K

SST32HF401-90-4C-L3K SST32HF401-90-4E-L3K

Valid combinations for SST32HF402

SST32HF402-70-4C-L3K SST32HF402-70-4E-L3K

SST32HF402-90-4C-L3K SST32HF402-90-4E-L3K

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST

sales representative to confirm availability of valid combinations an d to determine availability of new combinations.

25

PACKAGING DIAGRAMS

TOP VIEW

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

BOTTOM VIEW

8.00 ± 0.20

5.60

0.80

6 5 4 3 2 1

A1 CORNER

A B C D E F G H

SIDE VIEW

SEATING PLANE

6.00 ± 0.20

1.30 ± 0.10

0.15

0.35 ± 0.05

4.00

0.80 H G F E D C B A

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210,

this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.1 (±.05) mm.

4. The actual shape of the corners may be slightly different than as portrayed in the drawing.

48-BALL LOW-PROFILE, FINE -PITCH BALL GRID ARRAY (LFBGA) 6MM X 8MM SST PACKAGE CODE: L3K

6 5 4 3 2 1

0.45 ± 0.05 (48X)

A1 CORNER

48ba-lfbga-L3K-6x8-450mic-ILL.1

1mm

Silicon Storage Technolog y, Inc. • 1171 Sonora Court • Sunnyvale , CA 94086 • Telephone 408-73 5-91 10 • Fax 408-735-9036

www.SuperFlash.com or www.ssti.com

26

Datasheet SST32HF401-70-4C-L3K, SST32HF202-90-4E-L3K, SST32HF202-90-4C-L3K, SST32HF202-70-4E-L3K, SST32HF202-70-4C-L3K Datasheet (Silicon Storage Technology)

Specifications and Main Features

Frequently Asked Questions

User Manual