Datasheet SST30VR022-70-C-WN-R, SST30VR022-70-C-WH-R, SST30VR022-70-C-UN-R, SST30VR022-70-C-UH-R, SST30VR022-500-E-WH-R Datasheet (Silicon Storage Technology)

1

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

ComboMemory is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Data Sheet

FEATURES:

• ROM + SRAM ROM/RAM Combo

– SST30VR021: 256K x8 ROM + 128K x8 SRAM – SST30VR022: 256K x8 ROM + 256K x8 SRAM – SST30VR023: 256K x8 ROM + 32K x8 SRAM

• ROM/RAM combo on a monolithic chip

• Equivalent ComboMemory (Flash + SRAM):

SST31LF021E for code development and pre-production

• Wide Operating Voltage Range: 2.7-3.3V

• Chip Access Time

– SST30VR022 70 ns – SST30VR021/023 500 ns

• Low Power Dissipation:

– Sta ndby: 3 µW (Typical) – Operating: 10 mW (Typical)

• Fully Static Operation

– No clock or refresh required

• Three state Outputs

• Packages Available

– 32-pin TSOP (8mm x14mm)

PRODUCT DESCRIPTION

The SST30VR021/022/023 are ROM/RAM com bo chips consisting of 2 Mbi t Read Onl y Mem or y or gani zed as 256 KBytes and Static Ran dom Acce ss Memor y organized as 128, 256, and 32 KBytes.

The device is fabricated using SST’s adv a nc ed CMO S lo w power pr ocess te chnolog y.

The SST30VR021/02 2/023 has an outpu t enable inpu t for precise control of the data outputs. It also has two (2) separate chip enable inputs for selection of either RAM or ROM and fo r minimi zing c urren t drai n during pow er-do wn mode .

The SST30VR021/022/023 is particularly well suited for use in low voltage (2.7-3.3V) supplies such as pagers, organizers and other handheld applications.

RAMCS#

OE#

ROMCS#

WE#

DQ7-DQ

0

AMS-A

0

Note: AMS = Most Significant Address

ROMCS#

RAM

ROM

WE#

OE#

380 ILL B1.1

Address Buffer

Data Buffer

RAMCS#

Control

Circuit

FUNCTIONAL BLOCK DIAGRAM

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM

ROM/RAM Combo

SST30VR021 / SST30VR022 / SST30VR023

SST30VR021/022/0232 Mb Mask ROM (x8) + 1 Mb / 2Mb / 256 Kb SRAM (x8) Combo

2

Data Sheet

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM

ROM/RAM Combo

SST30VR021 / SST30VR022 / SST30VR023

FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP

TABLE 1: P

IN DESCRIPTION

Symbol Pin Name

A

MS

1

-A

0

1. AMS = Most significant address

Address Inputs, for ROM: AMS = A17, for RAM: AMS =A16 for SST30VR021

A

17

for SST30VR022

A

14

for SST30VR023 WE# Write Enable Input OE# Output Enable RAMCS# RAM Enable Input ROMCS# ROM Enable Input DQ

7

-DQ

0

Data Input/Output

V

DD

Power Supply

V

SS

Ground

T1.2 380

A11

A9

A8 A13 A14 A17

RAMCS#

V

DD

WE#

A16 A15 A12

A7

A6

A5

A4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

OE# A10 ROMCS# DQ7 DQ6 DQ5 DQ4 DQ3 V

SS

DQ2 DQ1 DQ0 A0 A1 A2 A3

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

380 ILL F01.0

Standard Pinout

T op Vie w

Die Up

Data Sheet

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR021 / SST30VR022 / SST30VR023

3

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause pe r manent dama ge to the device. This is a stres s rating only and funct ional operatio n of the device at these conditions or conditions greater tha n those defined in the ope rational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

Voltage on Any Pin Relative to V

SS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD + 0.5V

Voltage on V

DD

Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 4.0V

Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Soldering Temperature (10 Seconds Lead Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

O

PERATING RANGE

Range Ambient Temp V

DD

Commercial 0°C to +70°C 2.7-3.3V Extended -20°C to +85°C 2.7-3.3V

AC CONDITIONS OF TEST

Input Pulse Lev el. . . . . . . . . . . . . . . . . . . . . . . .0-V

DD

Input & Output Timing Reference Levels . . . . . . .VDD/2

Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C

L

= 30 pF for 70 ns

Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C

L

= 100 pF for 500 ns

TABLE 2: RECOMMENDED DC OPERATING CONDITIONS

Symbol Parameter Min Max Units

V

DD

Supply Voltage 2.7 3.3 V

V

SS

Ground 0 0 V

V

IH

Input High Voltage 2.4 VDD + 0.5 V

V

IL

Input Low Voltage -0.3 0.3 V

T2.0 380

TABLE 3: DC OPERATING CHARACTERISTICS

Symbol Parameter

V

DD

= 3.0 ± 0.3V

Test ConditionsMin Max Units

I

DD1

ROM Operating Supply Current 4.0+1.1(f)

1

1. f = Frequency of operation (MHz) = 1/cycle time

mA ROMCS#=VIL, RAMCS#=VIH,

V

IN=VIH

or V

IL, II/O

=Opens

I

DD2

RAM Operating Supply Current 2.5+1(f)

1

mA ROMCS#=VIH, RAMCS#=VIL, I

I/O

=Opens

I

SB

Standby VDD Current 10 µA ROMCS#≥VDD-0.2V, RAMCS#≥VDD-0.2V

V

IN≥VDD

-0.2V or VIN ≤0.2V

I

LI

Input Leakage Current -1 1 µA VIN=VSS to V

DD

I

LO

Output Leakage Current -1 1 µA ROMCS#=RAMCS#=VIH or OE#=VIH or

WE#=V

IL

, V

I/O=VSS

to V

DD

V

OL

Output Low Voltage 0.4 V IOL = 1.0 mA

V

OH

Output High Voltage 2.2 V IOH = -0.5 mA

T3.3 380

4

Data Sheet

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM

ROM/RAM Combo

SST30VR021 / SST30VR022 / SST30VR023

FIGURE 2: AC INPUT/OUTPUT REFERENCE WAVEFORMS

FIGURE 3: A TEST LOAD EXAMPLE

TABLE 4: CAPACITANCE (Ta = 25°C, f=1 Mhz)

Parameter Description Test Condition Maximum

C

I/O

1

I/O Pin Capacitance V

I/O

= 0V 8 pF

C

IN

1

Input Capacitance VIN = 0V 6 pF

T4.1 380

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

380 ILL F08.0

REFERENCE POINTS OUTPUTINPUT

V

IT

V

IHT

V

ILT

V

OT

AC test inputs are driven at V

IHT

(0.9 VDD) for a logic “1” and V

IL T

(0.1 VDD) for a logic “0”. Measurement reference points

for inputs and outputs are V

IT

(0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: V

IT

- V

INPUT

Test

V

OT

- V

OUTPUT

Test

V

IHT

- V

INPUT

HIGH Test

V

ILT

- V

INPUT

LOW Test

380 ILL F09.0

TO TESTER

TO DUT

C

L

Data Sheet

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR021 / SST30VR022 / SST30VR023

5

AC CHARACTERISTICS I. ROM Operation

FIGURE 4: ROM READ CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED) (ROMCS# = OE# = VIL)

TABLE 5: R

EAD CYCLE TIMING PARAMETERS V

DD

= 3.0V±0.3

Symbol Parameter

SST30VR022-70 SST30VR021/023-500

UnitsMin Max Min Max

T

RC

Read Cycle Time 70 500 ns

T

AA

Address Access Time 70 500 ns

T

CO

Chip Select to Output 70 500 ns

T

OE

Output Enable to Valid Output 35 250 ns

T

LZ

Chip Select to Low-Z Output 0 25 ns

T

OLZ

Output Enable to Low-Z Output 0 25 ns

T

HZ

Chip Disable to High-Z Ou tpu t 25 30 ns

T

OHZ

Output Disable to High-Z Output 25 30 ns

T

OH

Output Hold from Address Change 10 15 ns

T5.1 380

T

RC

T

AA

Data Valid

380 ILL F02.0

Data Out Previous Data Valid

Address

T

OH

6

Data Sheet

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM

ROM/RAM Combo

SST30VR021 / SST30VR022 / SST30VR023

FIGURE 5: ROM READ CYCLE TIMING DIAGRAM (ROMCS# & OE# CONTROLLED)

T

RC

T

AA

T

CO

T

LZ(2)

T

OHZ(1)

T

OH

T

HZ(1,2)

Data Valid

380 ILL F03.0

Data Out

OE#

ROMCS#

High-Z

Address

T

OE

T

OLZ

Notes: 1. THZ and T

OHZ

are defined as the time at which the outputs achieve the open circuit condition

and are referenced to the VOH or VOL.

2. At any given temperature and voltage condition THZ(max) is less than TLZ(min) both for a given device and from device to device.

Data Sheet

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR021 / SST30VR022 / SST30VR023

7

II. SRAM Operation (ROMCS# = V

IH

)

TABLE 6: R

EAD CYCLE TIMING PARAMETERS V

DD

= 3.0V±0.3

Symbol Parameter

SST30VR022-70 SST30VR021/023-500

UnitsMin Max Min Max

T

RC

Read Cycle Time 70 500 ns

T

AA

Address Access Time 70 500 ns

T

CO

Chip Select to Output 70 500 ns

T

OE

Output Enable to Valid Output 35 250 ns

T

LZ

Chip Select to Low-Z Output 0 25 ns

T

HZ

Chip Disable to High-Z Output 25 30 ns

T

OHZ

Output Disable to High-Z Outpu t 25 30 ns

T

OH

Output Hold from Address Change 10 15 ns

T6.2 380

TABLE 7: WRITE CYCLE TIMING PARAMETERS VDD = 3.0V±0.3

Symbol Parameter

SST30VR022-70 SST30VR021/023-500

UnitsMin Max Min Max

T

WC

Write Cycle Time 70 500 ns

T

CW

Chip Select to End-of-Write 60 365 ns

T

AW

Address Valid to End-of-Write 60 375 ns

T

AS

Address Set-up Time 0 0 ns

T

WP

Write Pulse Width 60 375 ns

T

WR

Write Recovery Time 0 0 ns

T

WHZ

Write to Output High-Z 30 80 ns

T

DW

Data to Write Time Overlap 30 200 ns

T

DH

Data Hold from Write Time 0 0 ns

T

OW

End Write to Output Low-Z 0 15 ns

T7.1 380

8

Data Sheet

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM

ROM/RAM Combo

SST30VR021 / SST30VR022 / SST30VR023

FIGURE 6: SRAM READ CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED) (OE# = RAMCS# = VIL, WE# = VIH)

FIGURE 7: SRAM R

EAD CYCLE TIMING DIAGRAM (OE# OR RAMCS# CONTROLLED)

T

RC

T

AA

Data Valid

380 ILL F04.0

Data Out Previous Data Valid

Address

T

OH

T

RC

T

AA

T

OE

T

CO

T

LZ(2)

T

OH

T

OHZ(1)

T

HZ

(1,2)

Data Valid

380 ILL F05.0

Data Out

RAMCS#

High-Z

Address

OE#

Notes: 1. THZ and T

OHZ

are defined as the time at which the outputs achieve the open circuit condition

and are referenced to the VOH or VOL.

2. At any given temperature and voltage condition THZ(max) is less than TLZ(min) both for a given device and from device to device.

3. WE# is high for Read cycle.

4. Address valid prior to coincidence with RAMCS# transition low.

Data Sheet

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR021 / SST30VR022 / SST30VR023

9

FIGURE 8: SRAM WRITE CYCLE TIMING DIAGRAM

TABLE 8: FUNCTIONAL DESCRIPTION/TRUTH TABLE

Address Inputs ROMCS#

1

1. If is forbidden for ROMCS# pin and RAMCS# pin to be “0” at the same time

RAMCS#

1

WE# OE# DQ0-DQ

7

XHHX

2

2. X means Don’t Care.

X

2

Z Standby

A

17-A0

LHX

2

H Z Output Floating

A17-A

0

LHX

2

L Dout ROM Read

Only A

MS

3

-A0 are valid

4

3. AMS = A16 for SST30VR021, A17 for SST30VR022, and A14 for SST30VR023

4. For SST30VR021: A

17

must be fixed to “L” or “H”

For SST30VR023: A

15

, A16, and A17 must be fixed to “L” or “H”

H L H H Z Output Floating

Only

A

MS

3

-A0 are valid

4

H L H L Dout RAM Read

Only A

MS

3

-A0 are valid

4

HLLHDinRAM Write

T8.4 380

Notes: 1. A write occurs during the overlap (TWP) of a low RAMCS# and low WE#. A write begins at the latest transition among

RAMCS# going low and WE# going low: A write end at the earliest transition among RAMCS# going high and WE# going high, TWP is measured from the beginning of write to the end of write.

2. TCW is measured from the later of RAMCS# going low to the end of write.

3. TAS is measured from the address valid to the beginning of write.

4. TWR is measured from the end of write to the address change.

5. If RAMCS#, WE# are in the read mode during this period, the I/O pins are in the outputs Low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur.

6. If RAMCS# goes low simultaneously with WE# going low or after WE# going low, the outputs remain high impedance state.

7. D

OUT

is the same phase of the latest written data in this write cycle.

8. D

OUT

is the read data of new address

9. ROMCS# = V

IH

T

WC

T

AW

T

CW(2)

T

OH

T

DH

T

DW

T

OW

T

WR(4)

Data Valid

380 ILL F07.0

Data In

Data Out

WE#

High-Z

High-Z (6)

(7) (8)

Address

RAMCS#

T

WP(1)

T

AS(3)

T

WHZ(5)

10

Data Sheet

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM

ROM/RAM Combo

SST30VR021 / SST30VR022 / SST30VR023

SST30VR021 Valid combinations

SST30VR021-500-C-WH SST30VR021-500-C-U1 SST30VR021-500-E-WH

SST30VR022 Valid combinations

SST30VR022-70-C-WH SST30VR022-70-C-U1

SST30VR022-70-E-WH

SST30VR023 Valid combinations

SST30VR023-500-C-WH SST30VR023-500-C-U1 SST30VR023-500-E-WH

Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

C-Spec Number Package Modifie r

H = 32 leads Numeric = Die modifier

Package Type

W = TSOP (8mm x 14mm) U = Die only

Temperature Range

C = Commercial = 0°C to +70°C E = Extended = -20°C to +85°C

Read Access Speed

70 = 70 ns

500 = 500 ns

Device Density

021 = 2 Mbit R OM + 1 Mbit SRAM 022 = 2 Mbit R OM + 2 Mbit SRAM 023 = 2 Mbit ROM + 256 Kbit SRAM

Voltage Range

V = 2.7-3.3V

Device Family

30 = ROM/RAM Combo

Device Speed Suffix1 Suffix2

SST30

VR023 -XXX -X -XX - RXXXX

Data Sheet

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR021 / SST30VR022 / SST30VR023

11

PACKAGING DIAGRAMS

32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM SST PACKAGE CODE: WH

32.TSOP-WH-ILL.4

Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (min/max).

3. Coplanarity: 0.1 (±.05) mm.

4. Maximum allowable mold flash is 0.15mm at the packa

g

e ends, and 0.25mm between leads.

8.10

7.90

.270 .170

1.05

0.95

.50

BSC

0.15

0.05

12.50

12.30

Pin # 1 Identifier

14.20

13.80

0.70

0.50

12

Data Sheet

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM

ROM/RAM Combo

SST30VR021 / SST30VR022 / SST30VR023

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale , CA 940 86 • Telephone 408-735-9110 • Fax 408-735 -90 36

www.SuperFlash.com or www.ssti.com

Datasheet SST30VR022-70-C-WN-R, SST30VR022-70-C-WH-R, SST30VR022-70-C-UN-R, SST30VR022-70-C-UH-R, SST30VR022-500-E-WH-R Datasheet (Silicon Storage Technology)

Specifications and Main Features

Frequently Asked Questions

User Manual