Datasheet SST29SF512, SST29SF010, SST29SF020, SST29SF040, SST29VF512 Datasheet (Silicon Storage Technology)

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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

SST29SF/VF512 / 010 / 020 / 0405.0 & 2.7V 512Kb / 1Mb / 2Mb / 4Mb (x8) Byte-Program, Small Erase Sector flash memories

FEATURES:

• Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8

• Single V oltage Read and Write Operations

– 5.0V-only for SST29SF512/010/020/040 – 2.7-3.6V for SST29VF512/010/020/040

• Superior Reliability

– Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention

• Low Power Consumption:

– Ac ti ve Current: 10 mA (typical) – Standby Current:

30 µA (typical) for SST29SF512/010/020/040

1 µA (typical) for SST29VF512/010/020/040

• Sector-Erase Capability

– Uniform 128 Byte sectors

• Fast Read Access Time:

– 55 ns – 70 ns

• Latched Address and Data

• Fast Erase and Byte-Program:

– Sector-Erase Time: 18 ms (typical) – Chip-Erase Time: 70 ms (typical) – Byte-Program Time: 14 µs (typical) – Chip Rewrite Time:

1 second (typical) for SST29SF/VF512 2 seconds (typical) for SST29SF/VF010 4 seconds (typical) for SST29SF/VF020 8 seconds (typical) for SST29SF/VF040

• Automatic Write Timing

– Internal V

• End-of-Write Detection

– Toggle Bit – Data# Polling

• TTL I/O Compatibility for SST29SFxxx

• CMOS I/O Compatibility for SST29VFxxx

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 32-pin PLCC – 32-pin TSOP (8mm x 14mm) – 32-pin PDIP

Generation

PP

Preliminary Specifications

PRODUCT DESCRIPTION

The SST29SF512/010/020/040 and SST29VF512/010/ 020/040 are 64K x8 / 128K x8 / 256K x8 / 512K x8 CMOS Small-Sector Flash (SSF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate c el l d es ig n a nd thick oxide tunneling in jector attain better reliability and manufacturability compared with alternate approaches. The SST29SFxxx devices write (Program or Erase) with a 4.5-5.5V power supply. The SST29VFxxx devices write (Program or Erase) with a 2.7-

3.6V power supply . These devices conform to JEDEC standard pinouts for x8 memories.

Featuring high performance Byte-Program, the SST29SFxxx and SST29VFxxx devices provide a maximum Byte-Program time of 20 µsec. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, ma nufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of at least 10,000 cycles. Data ret ention is rated at greater than 100 years.

The SST29SFxxx and SST29VFxxx devices are suited for applications that require convenient and economical updating of program, configura tion, or data me mory. For all system applications, they significantly improve performance

and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash te chnologi es. The total ene rgy consumed is a function of the applied voltage, current, and time of application. Sin ce for any given voltage range, the SuperFlash technology uses less current to program and has a short er erase time, the t otal energy consum ed duri ng any Erase or Program opera tion is less than alter native flash technologies. They also improve flexibility while lowering the cost for program, data, and configuration storage applications.

The SuperFlash te ch nology provides fixed Erase and P r ogram times, independent o f th e numbe r of Erase/ Pro gram cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times i ncrease with accumul ated Erase/P rogram cycles .

To meet high density, surface mount requirements, the SST29SFxxx and SST29VFxxx devices are offered in 32pin PLCC and 32- pin TSOP packages. A 600 mil, 32-pin PDIP is also offered for SST29SFxxx devices. See Figures 1, 2, and 3 for pinouts.

1

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

SSF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

Device Operation

Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocess or write sequences. A command is written by asse r ting WE# low whil e keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. T he data bus is latc hed o n the rising edge of WE# or CE#, whichever occurs first.

Read

The Read operation of the SST29SFxxx and SST29VFxxx devices are controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. W hen CE# is high, the chip is deselected and onl y standby power is consumed . OE# is the output control and is used to gate data from the out put pins. The data bus is in high im pedan ce sta te when e ither CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 4).

Byte-Program Operation

The SST29SFxxx and SST29VFxxx devices are programmed on a byte-by-byte basis. The Program operation consists of three steps. The first step is the three-byte-load sequence for Software Data Protection. The second step is to load byte address and byte data. Dur ing the Byte-Pr ogram operation, the address es are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on th e rising edge of ei ther CE# or WE#, whichever occurs first. The third step is the in ternal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once ini tiated, will be completed , within 20 µs. See Figure s 5 a nd 6 for WE # and CE # co nt ro ll ed P r og ram operation timing diagrams and Figure 16 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the in tern al Program operation, the host is fre e to perform ad ditiona l tasks. Any commands wri tten during the inter nal Program operation will be ignored.

Sector-Erase Operation

The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The SST29SFxxx and SST29VFxxx offer Sector-Erase mode. The sector architecture is based on uniform sector size of 128 Bytes. The Sector-Erase ope ration is i nitia ted by executing a s ix-bytecommand sequence with Sector-Erase command (20H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (20H) is latched on the rising

edge of the sixth W E # pu ls e. The i nte rnal Erase op eratio n begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figure 9 for timing waveforms. Any commands issued during the Sector-Erase operation are ignored.

Chip-Erase Operation

The SST29SFxxx and SST29VFxxx devices provide a Chip-Erase operation, wh ich allows the user to era se the entire memor y array to the “1s” state. This is usefu l when the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a sixbyte Software Data Protection command sequence with Chip-Erase command (10H) wi th a ddre ss 55 5H i n th e l ast byte sequence. The inter nal Erase operation beg ins with the rising edge of the sixt h WE # o r CE# , which ever oc cu rs first. During the internal Erase operation, the only valid read is T oggle Bit or Data# Polling. See Table 4 f or the command sequence, Figure 10 for timing diagram, an d Figu re 19 for the flowchart. Any commands written during the ChipErase operation will be ignored.

Write Operation Status Detection

The SST29SFxxx and SST29VFxxx devices provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The softw are det ection includes tw o status bits: Data# Polling (DQ End-of-Write detection mode is enabled after the rising edge of WE# which initiates the internal Program or Erase operatio n.

The actual comple tion of the n onvolatile write is as ync hronous with the sys tem; therefore, either a Data# Polling or Toggle Bit read may be simultaneous wi th the complet ion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If bo th reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

or DQ6. In order to prevent spurious

7

) and Toggle Bit (DQ6). The

7

2

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

Data# Polling (DQ7)

When the SST29SFx xx and SST29VFxxx devices are i n the internal Pr ogram operation, any attempt to read DQ will produce the co mplement of the true data. Once th e Program operation is completed, DQ

will produce true

7

data. The device is then ready for the next operation. During intern al Erase ope ration, any atte mpt to re ad DQ

7

will produce a ‘0’. Once the inter nal Erase operation is com- pleted, DQ

will produce a ‘1’. The Data# Polling is valid

7

after the risin g e dge of four th WE# (or CE#) pul se for Program operation. For Sector- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data # Polling timing diagram and Figure 17 for a flowchart.

Toggle Bit (DQ6)

During the inter nal Program or Erase ope ration, any consecutive attempts to read DQ

will produce alter nating 0s

6

and 1s, i.e., toggling between 0 and 1. W hen the internal Program or Erase operation is com plete d, t he tog gling wi ll stop. The device is then rea dy for the next operation. Th e Toggle Bit is valid after the rising edge of fourth WE # (or CE#) pulse for Program operation. For Sector or ChipErase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for T oggle Bit timing diagram an d Figur e 17 f or a flo wcha rt.

Data Protection

The SST29SFxxx and SST29VFxxx devices provide both hardware and software features to protec t nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of le ss than 5 ns will not init iate a write cycle .

Power Up/Down Detection: The Write operation is

V

DD

inhibited when V Write operation is in hi bi ted whe n V

is less than 2.5V f or SST29SFxxx. The

DD

is less than 1.5V. for

DD

SST29VFxxx. Write Inhibit Mode: Forcing OE# low, CE# high, or WE#

high will inhibit the W r ite operation. This prevents inadvertent writes during p ow er-up o r pow er- down.

Software Data Protection (SDP)

The SST29SFxx x and SST29VFxxx provide the JE DEC approved Software Data Protection scheme for all data alteration operation, i.e., Program and Erase. Any Program operation requires the inclusion of a se ries of three byte sequence. The three byte-load sequence is used to initiate

the Program operation, p roviding optimal protection from inadvertent write operations, e.g., during the system powerup or power -down. Any Er as e op er a t io n req u ire s th e inclu -

7

sion of six byte load sequence. These devices are shipped with the Software Data Protection permanently enabled. See T ab le 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode, within T

RC

.

Product Identification

The Product Identifi cation mode identifies the devices as SST29SF512, SST29SF010, SST29SF020, SST29SF040 and SST29VF512, SST29VF010, SST29VF020, SST29VF040 and manufacturer as SS T. This mode may be accessed by software o perations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when us ing mul tiple manufacturers in the same socket. For details, see Table 4 f or software operation, Figure 11 for the Software ID Entry and Read timing diagram and Figure 18 for the Software ID Entry command sequence flowchart.

TABLE 1: P

Manufacturer’s ID 0000H BFH Device ID SST29SF512 0001H 20H SST29VF512 0001H 21H SST29SF010 0001H 22H SST29VF010 0001H 23H SST29SF020 0001H 24H SST29VF020 0001H 25H SST29SF040 0001H 13H SST29VF040 0001H 14H

RODUCT IDENTIFICATION

Address Data

Product Identification Mode Exit/Reset

In order to return to the standard Read mode, the Software Product Identific ation mode must be exited. Exit is acco mplished by issuing the Software ID Exit command sequence, which returns the device to the Read operation. Please note that the S oftware ID Exit command is ig nor e d during an internal Program or Erase operation. See T able 4 for software command codes, Figure 12 for timing waveform and Figure 18 for a flowchart.

T1.1 505

3

FUNCTIONAL BLOCK DIAGRAM

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

Memory Address

Address Buffers & Latches

CE# OE#

WE#

X-Decoder

Control Logic

A12

A15

A16

A18

VDDWE#

A16NCVDDWE#

SuperFlash

Memory

Y-Decoder

I/O Buffers and Data Latches

DQ7 - DQ

A17

NC

0

505 ILL B1.1

A7 A6 A5 A4 A3 A2 A1 A0

DQ0

A7 A6 A5 A4 A3 A2 A1 A0

DQ0

A7 A6 A5 A4 A3 A2 A1 A0

DQ0

A12

A15NCNC

SST29SF/VF512SST29SF/VF010SST29SF/VF020SST29SF/VF040 SST29SF/VF010 SST29SF/VF020 SST29SF/VF040SST29SF/VF512

A7 A6 A5 A4 A3 A2 A1 A0

DQ0

4 3 2 1 32 31 30

5 6 7 8

32-pin PLCC

9 10 11 12 13

SST29SF/VF512SST29SF/VF010SST29SF/VF020SST29SF/VF040 SST29SF/VF010 SST29SF/VF020 SST29SF/VF040SST29SF/VF512

T op Vie w

14 15 16 17 18 19 20

DQ1

DQ2

DQ1

DQ2

DQ1

DQ2

DQ1

DQ2

VDDWE#

NC

29

A14

28

A13

27

A8

26

A9

25

A11

24

OE#

23

A10

22

CE#

21

DQ7

SS

V

DQ3

DQ4

DQ5

SS

V

DQ3

DQ4

DQ5

SS

V

DQ3

DQ4

DQ5

SS

V

DQ3

DQ4

DQ5

DQ6

505 ILL F02a.3

A14 A13 A8 A9 A11 OE# A10 CE# DQ7

FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN PLCC

4

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

SST29SF/VF512SST29SF/VF010SST29SF/VF020SST29SF/VF040 SST29SF/VF010 SST29SF/VF020 SST29SF/VF040SST29SF/VF512

A11

A9

A8 A13 A14 A17

WE# V

DD

A18 A16 A15 A12

A7

A6

A5

A4

FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN TSOP (8MM X 14MM)

A11

A13 A14

A17 WE# V

DD

NC A16 A15 A12

A9 A8

A7 A6 A5 A4

A11

A13 A14

WE# V

A16 A15 A12

NC

DD NC

A11 A9 A8

A13

A14

NC WE# V

DD

NC

A15

A12 A7 A6 A5 A4

1

A9

2

A8

3 4 5 6 7 8 9 10 11 12

A7

13

A6

14

A5

15

A4

16

SST29SF512SST29SF010SST29SF020SST29SF040 SST29SF010 SST29SF020 SST29SF040SST29SF512

Standard Pinout

T op Vie w

Die Up

505 ILL F01.2

OE#

32

A10

31

CE#

30

DQ7

29

DQ6

28

DQ5

27

DQ4

26

DQ3

25

V

24

DQ2

23

DQ1

22

DQ0

21

A0

20

A1

19

A2

18

A3

17

OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 V DQ2 DQ1 DQ0 A0 A1 A2 A3

SS

OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 V DQ2 DQ1 DQ0 A0 A1 A2 A3

SS

OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 V DQ2 DQ1 DQ0 A0 A1 A2 A3

SS

FIGURE 3: P

A18 A16 A15 A12

A7 A6 A5 A4 A3 A2 A1

A0 DQ0 DQ1 DQ2 V

SS

NC A16 A15 A12

A7 A6 A5 A4 A3 A2 A1

A0 DQ0 DQ1 DQ2 V

SS

NC A16 A15 A12

DQ0 DQ1 DQ2

V

SS

A7 A6 A5 A4 A3 A2 A1 A0

NC

NC A15 A12

A7 A6 A5 A4 A3 A2 A1

A0 DQ0 DQ1 DQ2 V

SS

IN ASSIGNMENTS FOR 32-PIN PDIP

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

32-pin

PDIP

T op Vie w

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

V

DD

WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3

505 ILL F02b.4

V

DD

WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3

V

DD

WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3

V

DD

WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3

5

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

1

-A

A

MS

-DQ

DQ

7

CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. V

DD

V

SS

NC No Connection Pin not connected internally

1. AMS = Most significant address A

MS

Address Inputs To provide memory addresses. During Sector-Erase AMS-A8 address lines will select the

0

sector.

Data Input/output To output data during Read cycles and receive input data during Write cycles.

0

Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high.

Power Supply To provide power supply voltage: 4.5-5.5V for SST29SF512/010/020/040

Ground

= A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020, and A18 for SST29SF/VF040

Preliminary Specifications

2.7-3.6V for SST29VF512/010/020/040

T2.3 505

TABLE 3: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address

Read V Program V Erase V

Standby V Write Inhibit X V

Product Identification Software Mode V

1. X can be VIL or VIH, but no other value.

V

IL

V

IL

V

IL

IH

XXV

V

IL

VIHD

IL

VILD

IH

VILX

IH

OUT IN

1

XXHigh Z X

XHigh Z/ D

IL

High Z/ D

IH

V

IL

IH

OUT OUT

A

IN

A

IN

Sector addre ss, XXH for Chip-Erase

X X

See Table 4

T3.4 505

6

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command Sequence

Byte-Program 555H AAH 2AAH 55H 555H A0H BA Sector-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA Chip-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H Software ID Entry Software ID Exit Software ID Exit

1. Address format A14-A0 (Hex),

2. BA = Program Byte address

for Sector-Erase; uses AMS-A7 address lines for SST29SF/VFxxx

3. SA

X

= Most significant address

A

MS

= A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020, and A18 for SST29SF/VF040

A

MS

4. The device does not remain in Software Product ID Mode if powered down.

5. With A

6. Both Software ID Exit operations are equivalent

4,5 6 6

Address A Addresses A Addresses A Addresses A

=0; SST Manufacturer’s ID= BFH, is read with A0 = 0,

MS-A1

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data

2

Data

3

X

555H AAH 2AAH 55H 555H 90H

XXH F0H

555H AAH 2AAH 55H 555H F0H

can be VIL or VIH, but no other value, for the Command sequence for SST29SF/VF512.

15

- A16 can be VIL or VIH, but no other value, for the Command sequence for SST29SF/VF010.

15

- A17 can be VIL or VIH, but no other value, for the Command sequence for SST29SF/VF020.

15

- A18 can be VIL or VIH, but no other value, for the Command sequence for SST29SF/VF040.

15

SST29SF512 Device ID = 20H, is read with A SST29SF512 Device ID = 21H, is read with A SST29SF010 Device ID = 22H, is read with A SST29VF010 Device ID = 23H, is read with A SST29SF020 Device ID = 24H, is read with A SST29SF020 Device ID = 25H, is read with A SST29SF040 Device ID = 13H, is read with A SST29VF040 Device ID = 14H, is read with A

0 0 0 0 0 0 0 0

= 1 = 1 = 1 = 1 = 1 = 1 = 1 = 1

20H

T4.4 505

7

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause pe r manent dama ge to the device. This is a stres s rating only and funct ional operatio n of the device at these conditions or conditions greater tha n those defined in the ope rational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to V

Voltage on A

Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

9

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

1

Output Short Circ uit Curr ent

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

+ 0.5V

DD

+ 1.0V

DD

OPERATING RANGE FOR SST29S F51 2/010/020 /040

Range Ambient Temp V

Commercial 0°C to +70°C 5V±10% Industrial -40°C to +85°C 5V±10%

DD

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . . C

= 30 pF for 55 ns

L

= 100 pF for 70 ns

L

See Figures 13, 14, and 15

TABLE 5: DC OPERATING CHARACTERISTICS V

Symbol Parameter

I

DD

I

SB1

I

SB2

I

LI

I

LO

V V V V V

IL IH IHC OL OH

Power Supply Current Address input=VIL/VIH, at f=1/TRC Min

Read 20 mA CE#=OE#=VIL, WE#=VIH, all I/Os open Write 20 mA CE#=WE#=V Standby VDD Current (TTL input) 3 mA CE#=VIH, VDD=VDD Max Standby VDD Current (CMOS input) 100 µA CE#=V Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max Output Leakage Current 10 µA V Input Low Voltage 0.8 V VDD=VDD Min Input High Voltage 2.0 V VDD=VDD Max Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max Output Low Voltage 0.4 V IOL=2.1 µA, VDD=VDD Min Output High Voltage 2.4 V IOH=-400 µA, VDD=VDD Min

DD

OPERATING RANGE FOR SST29V F51 2/010/020 /040

Range Ambient Temp V

Commercial 0°C to +70°C 2.7-3.6V Industrial -40°C to +85°C 2.7-3.6V

= 5.0V±10% FOR S ST29S FXXX

Limits

Test ConditionsMin Max Units

V

DD=VDD

OUT

Max

IL

, VDD=VDD Max

IHC

=GND to VDD, VDD=VDD Max

, OE#=V

DD

IH

T5.3 505

8

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

TABLE 6: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V FOR SST29V F XXX

Limits

Symbol Parameter

I

DD

Power Supply Current Address input=VIL/VIH, at f=1/TRC Min

Read 20 mA CE#=OE#=V Write 20 mA CE#=WE#=V

I

SB

I

LI

I

LO

V

IL

V

IH

V

IHC

V

OL

V

OH

Standby VDD Current 15 µA CE#=V Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max Output Leakage Current 10 µA V Input Low Voltage 0.8 V VDD=VDD Min Input High Voltage 0.7V Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min Output Hi gh Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

DD

Test ConditionsMin Max Units

V

DD=VDD

OUT

Max

, VDD=VDD Max

IHC

=GND to VDD, VDD=VDD Max

VVDD=VDD Max

, WE#=VIH, all I/Os open

IL

, OE#=V

IL

IH

T6.5 505

TABLE 7: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

T T

1

PU-READ PU-WRITE

1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs Power-up to Program/Erase Operation 100 µs

TABLE 8: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

1

C

I/O

1

C

IN

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance V

= 0V 12 pF

I/O

Input Capacitance VIN = 0V 6 pF

TABLE 9: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

1

N

END

1

T

DR

1

I

LTH

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117 Data Retention 100 Years JEDEC Standard A103 Latch Up 100 + I

DD

mA JEDEC Standard 78

T7.1 505

T8.1 505

T9.2 505

9

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

AC CHARACTERISTICS

TABLE 10: READ CYCLE TIMING PARAMETERS

VDD = 5V±10% FOR SST29S FXXX AND 2.7-3.6V FOR SST29VFXXX

SST29SF/VFxxx-55 SST29SF/VFxxx-70

Symbol Parameter

T

RC

T

CE

T

AA

T

OE

1

T

CLZ

1

T

OLZ

1

T

CHZ

1

T

OHZ

1

T

OH

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Read Cycle Time 55 70 ns Chip Enable Access Time 55 70 ns Address Acce ss Time 55 70 ns Output Enable Access Time 30 35 ns CE# Low to Active Output 0 0 ns OE# Low to Active Output 0 0 ns CE# High to High-Z Output 20 25 ns OE# High to High-Z Output 20 25 ns

Output Hold from Address Change

00ns

UnitsMin Max Min Max

T10.5 505

TABLE 11: PROGRAM/ERASE CYCLE TIMING PARAMETERS

VDD = 5V±10%V FOR SST 29SFXX X AND 2.7-3.6V FOR SST29V F XXX

Symbol Parameter Min Max Units

T

BP

T

AS

T

AH

T

CS

T

CH

T

OES

T

OEH

T

CP

T

WP

T

WPH

T

CPH

T

DS

T

DH

T

IDA

T

SE

T

SCE

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Byte-Program Time 20 µs Address Setup Time 0 ns Address Hold Time 30 ns WE# and CE# Setup Time 0 ns WE# and CE# Hold Time 0 ns OE# High Setup Time 0 ns OE# High Hold Time 10 ns CE# Pulse Width 40 ns WE# Pulse Width 40 ns

1

WE# Pulse Width High 30 ns

1

CE# Pulse Width High 30 ns Data Setup Time 40 ns

1

Data Hold Time 0 ns

1

Software ID Access and Exit Time 150 ns Sector-Erase 25 ms Chip-Erase 100 ms

T11.6 505

10

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

ADDRESS A

MS-0

WE#

DQ

CE#

OE#

7-0

IH

HIGH-Z

Note: AMS = Most Significant Address

AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040

FIGURE 4: READ CYCLE TIMING DIAGRAM

T

OLZV

CLZ

T

RC

T

CE

T

OE

T

AA

T

OHZ

T

OH

DATA VALIDDATA VALID

CHZ

HIGH-Z

505 ILL F03.1

ADDRESS A

MS-0

DQ

WE#

OE#

CE#

7-0

T

AS

Note: AMS = Most Significant Address

555 2AA 555 ADDR

T

AH

T

WP

T

WPH

T

CH

T

CS

AA 55 A0 DATA

SW0 SW1 SW2

AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040

DS

BYTE

(ADDR/DATA)

FIGURE 5: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

INTERNAL PROGRAM OPERATION STARTS

T

BP

T

DH

505 ILL F04.1

11

ADDRESS A

MS-0

DQ

CE#

OE#

WE#

7-0

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

INTERNAL PROGRAM OPERATION STARTS

T

BP

555 2AA 555 ADDR

T

AH

T

CP

T

AS

T

CPH

T

CH

T

CS

AA 55 A0 DATA

T

DS

T

DH

SW0 SW1 SW2

Note: AMS = Most Significant Address

AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040

BYTE

(ADDR/DATA)

FIGURE 6: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

ADDRESS A

MS-0

CE#

OE#

WE#

DQ

T

CE

T

OEH

T

OE

7

DD# D# D

505 ILL F05.1

T

OES

Note: AMS = Most Significant Address

AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040

505 ILL F06.1

FIGURE 7: DATA# POLLING TIMING DIAGRAM

12

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

ADDRESS A

MS-0

CE#

OE#

WE#

DQ

OEH

6

Note: AMS = Most Significant Address

AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040

FIGURE 8: TOGGLE BIT TIMING DIAGRAM

SIX-BYTE CODE FOR SECTOR-ERASE

T

CE

T

OET

TWO READ CYCLES

WITH SAME OUTPUTS

T

SE

OES

505 ILL F07.1

ADDRESS A

MS-0

WE#

DQ

CE#

OE#

7-0

555 2AA 2AA555 555

T

WP

SW0 SW1 SW2 SW3 SW4 SW5

Note: The device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are

interchangeable as long as minimum timings are met. (See Table 11) AMS = Most significant address AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040

FIGURE 9: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

SA

X

55 2055AA 80 AA

505 ILL F10.2

13

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

T

SIX-BYTE CODE FOR CHIP-ERASE

SCE

ADDRESS A

MS-0

WE#

DQ

CE#

OE#

7-0

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are

Note: AMS = Most Significant Address

555 2AA 2AA555 555

T

WP

SW0 SW1 SW2 SW3 SW4 SW5

interchageable as long as minimum timings are met. (See Table 11)

AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040

FIGURE 10: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

555

55 1055AA 80 AA

505 ILL F17.2

Three-Byte Sequence for

Software ID Entry

ADDRESS A

DQ

14-0

CE#

OE#

WE#

7-0

555 2AA 555 0000 0001

T

WP

T

WPH

SW1SW0 SW2

Note: Device ID = 20H for SST29SF512, 22H for SST29SF010, 24H for SST29SF020, 13H for SST29SF040

21H for SST29VF512, 23H for SST29VF010, 25H for SST29VF020, 14H for SST29VF040

FIGURE 11: SOFTWARE ID ENTRY AND READ

T

IDA

T

AA

BF55AA 90

Device ID

505 ILL F08.2

14

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

ADDRESS A

DQ

14-0

7-0

CE#

OE#

WE#

555 2AA 555

AA 55 F0

T

WP

T

WHP

SW0 SW1 SW2

FIGURE 12: SOFTWARE ID EXIT AND RESET

T

IDA

505 ILL F21.0

15

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

V

IHT

V

ILT

AC test inputs are driven at V inputs and outputs are V

(1.5 VDD) and VOT (1.5 VDD). Input rise and fall times (10% ↔ 90%) are <10 n s.

IT

V

IT

(3.0 V) for a logic “1” and V

IHT

REFERENCE POINTS OUTPUTINPUT

(0 V) for a logic “0”. Measurement re ference points for

IL T

FIGURE 13: AC INPUT/O UTPUT REFERE NCE WAVEFORMS FOR SST29SFXXX

V

IHT

V

IT

V

ILT

REFERENCE POINTS OUTPUTINPUT

V

OT

505 ILL F11.0

Note: V

505 ILL F11.0

- V

INPUT

OUTPUT

INPUT

Test

HIGH Test

LOW Test

IT

V

OT

V

IHT

V

ILT

AC test inputs are driven at V for inputs and outputs are V

(0.9 VDD) for a logic “1” and V

IHT

(0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

IT

(0.1 VDD) for a logic “0”. Measurement reference points

IL T

FIGURE 14: AC INPUT/O UTPUT REFERE NCE WAVEFORMS FOR SST29VFXXX

TO DUT

TEST LOAD EXAMPLE FOR SST29SF512/010/020/040

TO TESTER

C

L

R

L LOW

V

DD

RL

HIGH

505 ILL F12.2

TEST LOAD EXAMPLE FOR SST29VF512/010/020/040

FIGURE 15: TEST LOAD EXAMPLES

TO DUT

505 ILL F12b.2

Note: V

- V

IT

- V

V

OT

V

IHT

- V

V

ILT

TO TESTER

- V

INPUT

OUTPUT

INPUT

Test

HIGH Test

LOW Test

C

L

16

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

Start

Load data: AAH

Address: 555H

Load data: 55H Address: 2AAH

Load data: A0H

Address: 555H

FIGURE 16: B YTE-PROGRAM ALGORITHM

Load Byte

Address/Byte

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

505 ILL F13.1

17

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

Internal Timer

Byte-

Program/Erase

Initiated

Wait TBP,

T

SCE, or TSE

Program/Erase

Completed

Program/Erase

No

Toggle Bit

Byte-

Initiated

Read byte

Read same

byte

Does DQ

6

match?

Yes

No

Data# Polling

Byte-

Program/Erase

Initiated

Read DQ

7

Is DQ7 =

true data?

Yes

Program/Erase

Completed

FIGURE 17: WAIT OPTIONS

Program/Erase

Completed

505 ILL F14.0

18

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

Software ID Entry

Command Sequence

Load data: AAH

Address: 555H

Load data: 55H Address: 2AAH

Load data: 90H

Address: 555H

Wait T

IDA

Read Software ID

Software ID Exit &

Reset Command Sequence

Load data: AAH

Address: 555H

Load data: 55H Address: 2AAH

Load data: F0H

Address: 555H

Wait T

IDA

Return to normal

operation

Load data: F0H

Address: XXH

Wait T

IDA

Return to normal

operation

505 ILL F15.1

FIGURE 18: SOFTWARE ID COMMAND FLOWCHARTS

19

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

Chip-Erase

Command Sequence

Load data: AAH

Address: 555H

Load data: 55H Address: 2AAH

Load data: 80H

Address: 555H

Load data: AAH

Address: 555H

Load data: 55H Address: 2AAH

Sector-Erase

Command Sequence

Load data: AAH

Address: 555H

Load data: 55H Address: 2AAH

Load data: 80H

Address: 555H

Load data: AAH

Address: 555H

Load data: 55H Address: 2AAH

Load data: 10H

Address: 555H

Wait T

SCE

Chip erased

to FFH

FIGURE 19: ERASE C OMMAND SEQUENCE

20

Load data: 20H

Address: SA

Wait T

X

SE

Sector erased

to FFH

505 ILL F19.2

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

Device Speed Suffix1 Suffix2

SST29x

Fxxx -XXX -XX -XX

Package Modifi e r

H = 32 pins Numeric = Die modifier

Package Type

N = PLCC W = TSOP (die up) (8mm x 14mm) P = PDIP

Temperature Range

C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

55 = 55 ns 70 = 70 ns

Device Density

512 = 512 Kilobit 010 = 1 Megabit 020 = 2 Megabit 040 = 4 Megabit

Voltage

S = 5V±10% V = 2.7-3.6V

21

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

SST29SF512 Valid combinations

SST29SF512-55-4C-NH SST29SF512-55-4C-WH SST29SF512-70-4C-NH SST29SF512-70-4C-WH SST29SF512-70-4C-PH

SST29SF512-55-4I-NH SST29SF512-55-4I-WH SST29SF512-70-4I-NH SST29SF512-70-4I-WH

SST29VF512 Valid combinations

SST29VF512-55-4C-NH SST29VF512-55-4C-WH SST29VF512-70-4C-NH SST29VF512-70-4C-WH

SST29VF512-55-4I-NH SST29VF512-55-4I-WH SST29VF512-70-4I-NH SST29VF512-70-4I-WH

SST29SF010 Valid combinations

SST29SF010-55-4C-NH SST29SF010-55-4C-WH SST29SF010-70-4C-NH SST29SF010-70-4C-WH SST29SF010-70-4C-PH

SST29SF010-55-4I-NH SST29SF010-55-4I-WH SST29SF010-70-4I-NH SST29SF010-70-4I-WH

Preliminary Specifications

SST29VF010 Valid combinations

SST29VF010-55-4C-NH SST29VF010-55-4C-WH SST29VF010-70-4C-NH SST29VF010-70-4C-WH

SST29VF010-55-4I-NH SST29VF010-55-4I-WH SST29VF010-70-4I-NH SST29VF010-70-4I-WH

SST29SF020 Valid combinations

SST29SF020-55-4C-NH SST29SF020-55-4C-WH SST29SF020-70-4C-NH SST29SF020-70-4C-WH SST29SF020-70-4C-PH

SST29SF020-55-4I-NH SST29SF020-55-4I-WH SST29SF020-70-4I-NH SST29SF020-70-4I-WH

SST29VF020 Valid combinations

SST29VF020-55-4C-NH SST29VF020-55-4C-WH SST29VF020-70-4C-NH SST29VF020-70-4C-WH

SST29VF020-55-4I-NH SST29VF020-55-4I-WH SST29VF020-70-4I-NH SST29VF020-70-4I-WH

SST29SF040 Valid combinations

SST29SF040-55-4C-NH SST29SF040-55-4C-WH SST29SF040-70-4C-NH SST29SF040-70-4C-WH SST29SF040-70-4C-PH

SST29SF040-55-4I-NH SST29SF040-55-4I-WH SST29SF040-70-4I-NH SST29SF040-70-4I-WH

SST29VF040 Valid combinations

SST29VF040-55-4C-NH SST29VF040-55-4C-WH SST29VF040-70-4C-NH SST29VF040-70-4C-WH

SST29VF040-55-4I-NH SST29VF040-55-4I-WH SST29VF040-70-4I-NH SST29VF040-70-4I-WH

Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

22

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

g

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

PACKAGING DIAGRAMS

TOP VIEW SIDE VIEW BOTT OM VIEW

.485

Optional

Pin #1 Identifier

.042 .048

.495

.447 .453

1232

.020 R. MAX.

.023 .029

x 30˚

.106 .112

.030 .040

R.

.042 .048

.547

.585

.553

.595

.050 BSC.

Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (min/max).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

32-PIN PLASTIC LEAD CHIP CARRIER (PLCC)

ACKAGE CODE: NH

SST P

Pin # 1 Identifier

.026 .032

.050 BSC.

.125 .140

.075 .095

.013 .021

8.10

7.90

.400 BSC

.015 Min.

1.05

0.95

.490 .530

.50

BSC

.270 .170

.026 .032

32.PLCC.NH-ILL.2

12.50

12.30

0.70

0.50

Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (min/max).

3. Coplanarity: 0.1 (±.05) mm.

4. Maximum allowable mold flash is 0.15mm at the packa

32-

PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM

14.20

13.80

32.TSOP-WH-ILL.4

e ends, and 0.25mm between leads.

0.15

0.05

SST PACKAGE CODE: WH

23

Pin #1 Identifier

.065 .075

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

32

C

L

.600

1

1.645

1.655

7˚

4 PLCS.

.625 .530

.550

Base Plane

Seating Plane

.015 .050

.070 .080

Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (min/max).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.

.045 .065

.016 .022

32-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP)

ACKAGE CODE: PH

SST P

.100 BSC

.120 .150

.170 .200

.008 .012

.600 BSC

32.pdipPH-ILL.2

0˚

15˚

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 940 86 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.ssti.com

24

Datasheet SST29SF512, SST29SF010, SST29SF020, SST29SF040, SST29VF512 Datasheet (Silicon Storage Technology)

Specifications and Main Features

Frequently Asked Questions

User Manual