Datasheet SST29EE020, SST29LE020, SST29VE020 Datasheet (Silicon Storage Technology)

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2 Mbit (256K x8) Page-Mode EEPROM

SST29EE020 / SST29LE020 / SST29VE020

SST29EE020 / SST29LE020 / SST29VE0202 Mb Page-Mode flash memories

FEATURES:

Data Sheet

• Single Voltage Read and Write Operations

– 5.0V-only for SST29EE020 – 3.0-3.6V for SST29LE020 – 2.7-3.6V for SST29VE020

• Superior Reliability

– Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention

• Low Power Consumption

– Active Current: 20 mA (typical) for 5V and

10 mA (typical) for 3.0/2.7V

– Standby Current: 10 µA (typical)

• Fast Page-Write Operation

– 128 Bytes per Page, 2048 Pages – Page-Write Cycle: 5 ms (typical) – Complete Memory Rewrite: 10 sec (typical) – Effective Byte-Write Cycle Time: 39 µs (typical)

• Fast Read Access Time

– 5.0V-only operation: 120 and 150 ns – 3.0-3.6V operation: 200 and 250 ns – 2.7-3.6V operation: 200 and 250 ns

PRODUCT DESCRIPTION

• Latched Address and Data

• Automatic Write Timing

– Internal V

Generation

PP

• End of Write Detection

– Toggle Bit – Data# Polling

• Hardware and Software Data Protection

• Product Identification can be accessed via

Software Operation

• TTL I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 32-lead PLCC – 32-lead TSOP (8mm x 14mm, 8mm x 20mm) – 32-pin PDIP

The SST29EE/LE/VE020 are 256K x8 CMOS Page-Write EEPROM manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and th ick oxide tunnelin g injector attain better reliability and manufacturability compared with alternate approaches. The SST29EE/LE/VE020 write with a single power supply. Internal Erase /Program is transparent to the user. The SST29EE/LE/VE020 conform to JEDEC standard pinouts for byte-wide memories.

Featuring high performance Page-Write, the SST29EE/LE/ VE020 provide a typica l Byte-Write time of 39 µsec. The entire memor y, i.e., 256 KBytes, can be written page -bypage in as l ittle as 10 s econds, when u sing inter face features such as Toggle Bit or Data# Polling to indicate the completion of a W r ite cy cle. To protect again st in adver ten t write, the SST29EE/LE/VE020 have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wid e spectrum of ap plications, the SST29EE/LE/VE02 0 are offered with a guaranteed PageWrite endurance of 10,000 cycles. Data retention is rated at greater th an 100 y ear s.

The SST29EE/LE/VE020 are suited for applications that require convenient and economi cal updating of program, configuration, or da ta mem ory. For all system appl ications, the SST29EE/ LE/VE020 signifi cantly imp rov e perf ormance and reliability, while lowering power consumption. The SST29EE/LE/ VE020 improve flexibility while lowering the cost for program, data, and confi guration storage appli cations.

To meet high density, surface mount requirements, the SST29EE/LE/VE020 are offered in 32-lead PLCC and 32lead TSOP packages. A 600-mi l, 32-pin P DIP package is also available. See Figures 1, 2, and 3 for pinouts.

Device Operation

The SST Page-Mode EE PROM offers in-circuit electr ical write capability. The SST29EE/LE/VE020 does not require separate Erase and Program operations. The internally timed Write c ycl e executes both erase and p ro gram t ransparently to the user. The SST29EE/LE/VE020 have industry standard optional Software Data Protection, which SST recommends always to be enabled. The SST29EE/LE/ VE020 are compatible with industry standard EEPROM pinouts and functionality.

1

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

SSF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

2 Mbit Page-Mode EEPROM

SST29EE020 / SST29LE020 / SST29VE020

Data Sheet

Read

The Read operations of the SST29EE /LE /VE020 are controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for fur ther details (Figure 4).

Write

The Page-Write to the SST29EE/LE/VE020 should always use the JEDEC Stan dard So ftware Dat a P rotec ti on (SDP ) three-byte command s equen ce. The SST 29EE/L E/VE 020 contain the opti onal JED EC approved Software Dat a Protection scheme. SST recommends that SDP always be enabled, thus, the description of the write operations will be given using the SDP en abled format. The three-byte S DP Enable and SDP Wr i te c o mma nd s are identical; therefore, any time a SDP Write command is issued , Software Dat a Protection is automatically assured. The first time the threebyte SDP command is given, the device becomes SDP enabled. Subsequent issuance of the same command bypasses the data protection for the page being written. At the end of the desired Page-Write, the entire device remains protec ted. For addi tional descr iption s, please s ee the applicatio n not es T he Pr ope r Us e of JE DE C S ta nda rd

Software Data Protection and Protecting Against Uninten- tional Writes When Using Single Power Supply Flash Memories.

The Write ope ration consists o f three steps. Ste p 1 is the three-byte load sequence for Software Data Protection. Step 2 is the byte-load cycle to a page buffer of the SST29EE/LE/VE020. Steps 1 and 2 use the same timing for both operations. Step 3 is an internally controlled Write cycle for writin g th e d at a l oa ded i n t he pag e buffer into th e memory array for nonvolatile storage. During both the SDP three-byte load sequence and the byte-load cycle, the addresses are lat ched by the falling e dge of e ither CE# or WE#, whichever occ ur s la st . Th e da ta i s l at ch ed by the rising edge of either CE# or WE#, whichever occurs first. The internal Write cycle is initiated by the T rising edge o f WE# or CE#, whichever occurs first. The Write cycle, once initiated, will continue to completion, typically within 5 ms. See Fig ures 5 and 6 for WE# and CE# controlled Page-Wr ite cycle timing diagrams and Figures 15 and 17 for flowcharts.

The Write op eration has three functional cycles : the Software Data Protection l oad sequ ence, the pag e load c ycle, and the internal Write cycle. The Software Data Protection

timer after the

BLCO

consists of a s pec i fic t hr ee - byte lo ad s equ en ce tha t a ll ows writing to the selected page an d will leave the SST29EE/ LE/VE020 protected at the end of the Page-Write. The page load cycle consists of loading 1 to 128 Bytes of data into the page buffer. The internal Write cycle consists of the

time-out and the write timer operation. Dur ing the

T

BLCO

Write operation, the only valid reads are Data# Polling and Toggle Bit.

The Page-Write operation allow s the loading of up to 128 bytes of data into the page buffer of the SST29EE/LE/ VE020 before the initiation of the internal Write cycle. During the internal Write cycle, all the data in the page buffer is written simult aneously into the memory array. Hence, the Page-Write feature of SST29EE/LE/VE020 allow the entire memory to be written in as little as 10 seconds. During the internal Wr ite cycle, the host is free t o perform additional tasks, such as to fetch data from other locations in the system to set up the write to the next page. In each Page-Write operation, all the bytes that are loaded into the page buffer must have the same page address, i.e. A

through A16. Any

7

byte not loaded with user data will be written to FFH. See Figures 5 and 6 for the Page-Write cycle timing dia-

grams. If after the completio n of the three-byte SDP loa d sequence or the initial byte-load cycle, the host loads a second byte into the page buffer within a byte-load cycle time

) of 100 µs, the SST29EE/LE/VE020 will stay in the

(T

BLC

page load cycle. Additional bytes are then loaded consecutively. The page load cycle will be terminated if no additional byte is loaded into the page buffer within 200 µs

) from the last byte-load c ycle, i.e., no subsequent

(T

BLCO

WE# or CE# hig h-to -l ow t ran si tion after the la st risi ng ed ge of WE# or CE#. Data in the page buffer can be changed by a subsequent byte-load cyc le. The page load period can continue indefin itely, as long as the host c ontinues to loa d the device within the byte-load cycle time of 100 µs. The page to be loaded i s determined by the page address of the last byte loaded.

Software Chip-Erase

The SST29EE/LE/VE020 provide a Chip-Erase operation, which allows the user to simultaneously clear the entire memory array to the “1” state. This is useful when the entire device must be quickly erased.

The Software Chip- Erase operation is i nitiated by using a specific six-byte l oad sequence. After th e load sequence, the device enters into an internally timed cycle similar to the Write cycle. During the Erase operation, the only valid read is Toggle Bit. See Tab le 4 for the load sequence, Figure 10 for timing diagram, and Figure 19 for the flowchart.

2

2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020

Data Sheet

Write Operation Status Detection

The SST29EE/LE/VE020 provide two software means to detect the completi on of a W rite cycle, in order to o pti mi ze the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ

). The end of write detection mode is enabled after the

(DQ

6

) and T oggle Bit

7

rising WE# or CE# whichever occurs first, wh ich initiates the internal Write cycle .

The actual completion of the nonvolatile write is asynchronous with the sys tem; therefore, either a Data# Polling or Toggle B it read may be simultaneou s with the complet ion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ

or DQ6. In order to prevent spurious

7

rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If bo th reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

Data# Polling (DQ7)

When the SST29EE/LE/VE020 are in the internal Write cycle, any attempt to read DQ

of the last byte loaded dur-

7

ing the byte-load cycle wil l receive the complem ent of the true data. Once the Write cycle is completed, DQ

will

7

show true data. The device is then ready for the next operation. See Figure 7 for Data# Polling timing diagram and Figure 16 for a flowchart.

Toggle Bit (DQ6)

During the internal Write cycle , any consecu tive attemp ts to read DQ

will produce alter nating 0s and 1s, i.e., toggling

6

between 0 and 1. When the Wr ite c ycle is co mple ted, the toggling will stop. The device is then ready for the next operation. See Fig ure 8 for Toggle Bit timing diagram and Figure 16 for a flowchart. The initial read of the Toggle Bit will typically be a “1”.

Data Protection

The SST29EE/L E/ VE02 0 provide both har dware an d so ftware features to protect nonvolatile d ata from inadverten t writes.

Write Inhibit Mode:

Forcing OE# low, CE# high, or WE# high will inhibit the W r ite operation. This prevents inadvertent writes durin g pow er-u p or po wer- dow n.

Software Data Protection (SDP)

The SST29EE/LE/VE020 provide the JEDEC approved optional Software Data Protection scheme for all data alteration operations, i.e., Write and Chip-Erase. With this scheme, any Write operation requires the inclusion of a series of three byte-load operations to precede the data loading operation. The three byte-load sequence is used to initiate the Write cycle, providing optimal protection from inadvertent write operations, e.g., during the system powerup or power-down. The SST29 EE/LE/VE020 are shippe d with the Software Data Protection disabled.

The software protection s ch em e can be enabled by applying a three-byte sequenc e to the device, during a pageload cycle (Figures 5 and 6). The device will then be automatically set into the data protect mode. Any subsequent Write operation will require the preceding three-byte sequence. See Table 4 for the specifi c s oft ware co mm an d codes and Figures 5 and 6 for the timin g diagrams. To set the device into the unprotected mode, a six-byte sequence is required. See Table 4 for the specific codes and Figure 9 for the timing diagram. If a wr i te is at tem pte d while SDP is enabled the device will be in a non-accessible state for ~300 µs. SST recommends Software Data Protection always be enabled. See Figure 17 for flowcharts.

The SST29EE/LE/VE020 Software Data Protection is a global command, protecting all pages in the entire memory array once enabled (or disabled). Therefore using SDP for a single Page-Write will enable SDP for the entire array. Single pages by themselves cannot be SDP ena bled or disabled.

Single power supply reprogrammable nonvolatile memories may be unintentionally altered. SST strongly recommends that Software Data Protection (SDP) always be enabled. The SST29EE/LE/VE020 should be programmed using the SDP command sequence. SST recommends the SDP Disable Command Seq uence not be issued to the device prior to w riting.

Please refer to the following Application Notes for more informati on on usi ng SDP:

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of le ss than 5 ns will not init iate a Writ e cycle .

Power Up/Down Detection: The Write operation is

V

DD

inhibited when V

is less than 2.5V.

DD

• Protecting Against Unintentional Writes When

Using Single Power Supply Flash Memories

• The Proper Use of JEDEC Standard Software

Data Protection

3

2 Mbit Page-Mode EEPROM

SST29EE020 / SST29LE020 / SST29VE020

Data Sheet

Product Identification

The product id ent ific ati on mod e ident ifi es the de vi ce as the SST29EE/LE/VE020 and manufacturer as SST . This mode is accessed via so ftware. For details, see Table 4, Figur e 11 for the software ID entr y and read timi ng diagram, an d Figure 18 for the ID entry command sequence flowchart.

TABLE 1: P

Manufacturer’s ID 0000H BFH Device ID

SST29EE020 0001H 10H SST29LE020 0001H 12H SST29VE020 0001H 12H

FUNCTIONAL BLOCK DIAGRAM

RODUCT IDENTIFICATION

Address Data

T1.3 307

X-Decoder

Product Identification Mode Exit

In order to retur n to the sta nda rd r ead mod e, the So ftwar e Product Identification mode must be exited. Exiting is accomplished b y issuing the Softw are ID Exit (reset) oper ation, which ret urns the device to the Re ad operation. T he Reset operation may also be used to reset the device to the Read mode after an inadvertent transient condition that apparently caus es the device to behave abnor mally, e.g., not read correctly. See Table 4 for software command codes, Figure 12 for timing waveform, and Figu re 18 for a flowchart.

SuperFlash

Memory

A17 - A

0

CE# OE#

WE#

FIGURE 1: P

Address Buffer & Latches

Control Logic

A12

A15

4 3 2 1 32 31 30

5

A7

6

A6

7

A5

8

A4 A3 A2 A1 A0

DQ0

IN ASSIGNMENTS FOR 32-LEAD PLCC

32-lead PLCC

9 10 11 12 13

14 15 16 17 18 19 20

DQ1

DQ2

A16NCVDDWE#

T op Vie w

SS

V

DQ3

DQ4

Y-Decoder and Page Latches

I/O Buffers and Data Latches

DQ5

A17

29 28 27 26 25 24 23 22 21

DQ6

307 ILL F02.3

DQ7 - DQ

A14 A13 A8 A9 A11 OE# A10 CE# DQ7

0

307 ILL B1.1

4

2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020

Data Sheet

A11

A13 A14

A17 WE# V

DD

NC A16 A15 A12

A9 A8

A7 A6 A5 A4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Standard Pinout

T op Vie w

Die Up

FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP

1

NC

2

A16

3

A15

4

A12

5

A7

6

A6

7

A5

8

A4

9

A3

10

A2

11

A1

12

A0

SS

13 14 15 16

DQ0 DQ1 DQ2 V

32-pin

PDIP

T op Vie w

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

32

V 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

DD

WE#

A17

A14

A13

A8

A9

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 V

SS

DQ2 DQ1 DQ0 A0 A1 A2 A3

307 ILL F01.2

307 ILL F19.0

FIGURE 3: P

IN ASSIGNMENTS FOR 32-PIN PDIP

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

A17-A A6-A

0

DQ

-DQ0Data Input/ output To output data during Read cycles and receive input data durin g Write cycles.

7

CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. V

DD

V

SS

NC No Connection Unconnected pins.

Row Address Inputs To provide memory addresses. Row addresses define a page for a Write cycle.

7

Column Address Inputs Column Addresses are toggled to load page data

Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high.

Power Supply To provide: 5.0V supply (±10%) for SST2 9EE020

3.0V supply (3.0-3.6V) for SST29LE020

2.7V supply (2.7-3.6V) for SST29VE020

Ground

5

T2.2 307

2 Mbit Page-Mode EEPROM

SST29EE020 / SST29LE020 / SST29VE020

Data Sheet

TABLE 3: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address

Read V Page-Write V Standby V

V

IL

V

IL IH

Write Inhibit X V

XXV

Software Chip-Erase V

V

IL

Product Identification Software Mode V

SDP Enable Mode V SDP Disable Mode V

1. X can be VIL or VIH, but no other value

2. Device ID = 10H for SST29EE020 and 12H for SST29LE/VE020

V

IL

V

IL

V

IL

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command Sequence

Software Data Protect Enable & Page-Write

Software Data Protect Disable

Software Chip-Erase Software ID Entry

4,5

Software ID Exit 5555H AAH 2AAAH 55H 5555H F0H Alternate

Software ID Entry

1. Address format A14-A0 (Hex), Addres s A15 can be VIL or VIH, but no other value.

2. Page-Write consists of loading up to 128 Bytes (A6-A0)

3. The software Chip-Erase function is not supported by the industrial temperature part. Please contact SST if you require this function for an industrial temperature part.

4. The device does not remain in Software Product ID Mode if powered down.

5. With A

6. Alternate six-byte Software Product ID Command Code

Note: This product supports both the JEDEC standard three-byte command code sequence and SST’s original six-byte command code

sequence. For new designs, SST recommends that the three-byte command code sequence be used.

6

=0; SST Manufacturer’s ID= BFH, is read with A0 = 0,

14-A1

1st Bus

Write Cycle

1

Addr

Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data

5555H AAH 2AAAH 55H 5555H A0H Addr

5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 20H

3

5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H 5555H AAH 2AAAH 55H 5555H 90H

5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 60H

SST29EE020 Device ID = 10H, is read with A SST29LE/VE020 Device ID = 12H, is read with A

IL IH

1

X

IL

IH

IH IH

2nd Bus

Write Cycle

V

D

IH

OUT

V

D

IL

IN

A

IN

A

IN

XHigh Z X XHigh Z/ D

High Z/ D

IH

V

D

IL

IN

V

Manufacturer’s ID (BFH)

IL

Device ID

V

IL

V

IL

OUT OUT

2

3rd Bus

Write Cycle

0

= 1

0

4th Bus

Write Cycle

2

= 1

Data

X X A

IN,

See Table 4

See Table 4 See Table 4

See Table 4

5th Bus

Write Cycle

6th Bus

Write Cycle

T3.3 307

T4.2 307

6

2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020

Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause pe r manent dama ge to the device. This is a stres s rating only and funct ional operatio n of the device at these conditions or conditions greater tha n those defined in the ope rational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to V

Voltage on A

Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14.0V

9

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

1

Output Short Circ uit Curr ent

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

OPERATING RANGE FOR SST29E E020

Range Ambient Temp V

Commercial 0°C to +70°C5.0V±10% Industrial -40°C to +85°C5.0V±10%

DD

+ 0.5V

DD

+ 1.0V

DD

OPERATING RANGE FOR SST29L E02 0

Range Ambient Temp V

Commercial 0°C to +70°C 3.0-3.6V Industrial -40°C to +85°C 3.0-3.6V

DD

OPERATING RANGE FOR SST29V E020

Range Ambient Temp V

Commercial 0°C to +70°C 2.7-3.6V Industrial -40°C to +85°C 2.7-3.6V

DD

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 10 ns

Output Load . . . . . . . . . . . . . . . . . . . . . 1 TTL Gate and CL = 100 pF

See Figures 13 and 14

7

2 Mbit Page-Mode EEPROM

SST29EE020 / SST29LE020 / SST29VE020

TABLE 5: DC OPERATING CHARACTERISTICS VDD = 5.0V±10% FOR S ST29E E020

Limits

Symbol Parameter

I

DD

Power Supply Current Address input=VIL/VIH, at f=1/TRC Min,

Read 30 mA CE#=OE#=V Write 50 mA CE#=WE#=V

I

SB1

Standby VDD Current (TTL input)

I

SB2

Standby VDD Current (CMOS input)

I

LI

I

LO

V

IL

V

IH

V

OL

V

OH

Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max Output Leakage Current 10 µA V Input Low Voltage 0.8 V VDD=VDD Min Input High Voltage 2.0 V VDD=VDD Max Output Low Voltage 0.4 V IOL=2.1 mA, VDD=VDD Min Output High Voltage 2.4 V IOH=-400 µA, VDD=VDD Min

3 mA CE#=OE#=WE#=VIH, VDD=VDD Max

50 µA CE#=OE#=WE#=VDD-0.3V, VDD=VDD Max

Test ConditionsMin Max Units

V

DD=VDD

OUT

Max

IL

=GND to VDD, VDD=VDD Max

Data Sheet

, WE#=VIH, all I/Os open

, OE#=VIH, VDD=VDD Max

T5.2 307

TABLE 6: DC OPERATING CHARACTERISTICS VDD = 3.0-3.6V FOR SST29LE020 AND 2.7-3.0V FOR SST29VE020

Limits

Symbol Parameter

I

DD

Power Supply Current Address input=VIL/VIH, at f=1/TRC Min,

Read 12 mA CE#=OE#=V Write 15 mA CE#=WE#=V

I

SB1

Standby VDD Current (TTL input)

I

SB2

Standby VDD Current (CMOS input)

I

LI

I

LO

V

IL

V

IH

V

OL

V

OH

Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max Output Leakage Current 10 µA V Input Low Voltage 0.8 V VDD=VDD Min Input High Voltage 2.0 V VDD=VDD Max Output Low Voltage 0.4 V IOL=100 µA, VDD=VDD Min Output High Voltage 2.4 V IOH=-100 µA, VDD=VDD Min

1 mA CE#=OE#=WE#=VIH, VDD=VDD Max

15 µA CE#=OE#=WE#=VDD-0.3V, VDD=VDD Max

Test ConditionsMin Max Units

V

DD=VDD

OUT

Max

, WE#=VIH, all I/Os open

IL

, OE#=VIH, VDD=VDD Max

IL

=GND to VDD, VDD=VDD Max

T6.2 307

8

2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020

Data Sheet

TABLE 7: RECOMMENDED SYSTE M POWER-UP TIMINGS

Symbol Parameter Minimum Units

T

PU-READ

T

PU-WRITE

1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 8: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

1

C

I/O

1

C

IN

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 9: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

1

N

END

1

T

DR

1

I

LTH

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs Power-up to Write Operation 5 ms

I/O Pin Capacitance V

= 0V 12 pF

I/O

Input Capacitance VIN = 0V 6 pF

Endurance 10,000 Cycles JEDEC Standard A117 Data Retention 100 Years JEDEC Standard A103 Latch Up 100 mA JEDEC Standard 78

T7.1 307

T8.0 307

T9.5 307

9

2 Mbit Page-Mode EEPROM

SST29EE020 / SST29LE020 / SST29VE020

AC CHARACTERISTICS

TABLE 10: READ CYCLE TIMING PARAMETERS FOR SST29EE020

SST29EE020-120 SST29EE020-150

Symbol Parameter

T

RC

T

CE

T

AA

T

OE

1

T

CLZ

1

T

OLZ

1

T

CHZ

1

T

OHZ

1

T

OH

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 11: READ CYCLE TIMING PARAMETERS FOR SST29LE020

Symbol Parameter

T

RC

T

CE

T

AA

T

OE

1

T

CLZ

1

T

OLZ

1

T

CHZ

1

T

OHZ

1

T

OH

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Read Cycle Time 120 150 ns Chip Enable Access Time 120 150 ns Address Access Time 120 150 ns Output Enable Access Time 50 60 ns CE# Low to Active Output 0 0 ns OE# Low to Active Output 0 0 ns CE# High to High-Z Output 30 30 ns OE# High to High-Z Output 30 30 ns Output Hold from Address Change 0 0 ns

SST29LE020-200 SST29LE020-250

Read Cycle Time 200 250 ns Chip Enable Access Time 200 250 ns Address Access Time 200 250 ns Output Enable Access Time 100 120 ns CE# Low to Active Output 0 0 ns OE# Low to Active Output 0 0 ns CE# High to High-Z Output 50 50 ns OE# High to High-Z Output 50 50 ns Output Hold from Address Change 0 0 ns

Data Sheet

UnitsMin Max Min Max

T10.4 307

UnitsMinMaxMinMax

T11.1 307

TABLE 12: READ CYCLE TIMING PARAMETERS FOR SST29VE020

SST29VE020-200 SST29VE020-250

Symbol Parameter

T

RC

T

CE

T

AA

T

OE

1

T

CLZ

1

T

OLZ

1

T

CHZ

1

T

OHZ

1

T

OH

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Read Cycle Time 200 250 ns Chip Enable Access Time 200 250 ns Address Access Time 200 250 ns Output Enable Access Time 100 120 ns CE# Low to Active Output 0 0 ns OE# Low to Active Output 0 0 ns CE# High to High-Z Output 50 50 ns OE# High to High-Z Output 50 50 ns Output Hold from Address Change 0 0 ns

10

UnitsMinMaxMinMax

T12.1 307

2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020

Data Sheet

TABLE 13: PAGE-WRITE CYCLE TIMING PARAMETERS

SST29EE020 SST29LE/VE020

Symbol Parameter

T

WC

T

AS

T

AH

T

CS

T

CH

T

OES

T

OEH

T

CP

T

WP

T

DS

1

T

DH

1

T

BLC

1

T

BLCO

1

T

IDA

T

SCE

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Write Cycle (Erase and Program) 10 10 ms Address Setup Time 0 0 ns Address Hold Time 50 70 ns WE# and CE# Setup Time 0 0 ns WE# and CE# Hold Time 0 0 ns OE# High Setup Time 0 0 ns OE# High Hold Time 0 0 ns CE# Pulse Width 70 120 ns WE# Pulse Width 70 120 ns Data Setup Time 35 50 ns Data Hold Time 0 0 ns Byte Load Cycle Time 0.05 100 0.05 100 µs Byte Load Cycle Time 200 200 µs Software ID Ac cess and Exit Time 10 10 µs Software Chip-Erase 20 20 ms

UnitsMin Max Min Max

T13.5307

11

2 Mbit Page-Mode EEPROM

SST29EE020 / SST29LE020 / SST29VE020

Data Sheet

ADDRESS A

WE#

DQ

17-0

CE#

OE#

7-0

V

IH

HIGH-Z HIGH-Z

FIGURE 4: READ CYCLE TIMING DIAGRAM

T

CLZ

T

OLZ

T

CE

T

RC

OE

T

DATA VALID

OH

T

AA

T

OHZ

T

CHZ

DATA VALID

307 ILL F03.0

ADDRESS A

DQ

17-0

CE#

OE#

WE#

7-0

Three-Byte Sequence for

Enabling SDP

5555

2AAA 5555

AA 55 A0

SW0

SW1 SW2

T

CS

OES

T

AH

AS

T

CH

T

OEH

T

WP

DATA VALID

T

BYTE 0 BYTE 1 BYTE 127

DS

T

BLC

T

FIGURE 5: WE# CONTROLLED PAGE-WRITE CYCLE TIMING DIAGRAM

DH

T

BLCO

T

WC

307 ILL F04.1

12

2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020

Data Sheet

ADDRESS A

DQ

17-0

CE#

OE#

WE#

7-0

Three-Byte Sequence for

Enabling SDP

5555

2AAA 5555

AA 55 A0

SW0

SW1 SW2

T

OES

T

CS

T

AH

AS

T

CP

DATA VALID

T

BYTE 0 BYTE 1 BYTE 127

DS

T

BLC

T

OEH

CH

T

FIGURE 6: CE# CONTROLLED PAGE-WRITE CYCLE TIMING DIAGRAM

DH

T

BLCO

T

WC

307 ILL F05.1

ADDRESS A

17-0

CE#

OE#

WE#

DQ

T

CE

T

OEH

T

OE

7

D

D#

TWC + T

D#

BLCO

D

OES

307 ILL F06.0

FIGURE 7: DATA# POLLING TIMING DIAGRAM

13

2 Mbit Page-Mode EEPROM

SST29EE020 / SST29LE020 / SST29VE020

Data Sheet

ADDRESS A

17-0

CE#

OE#

WE#

DQ

T

OEH

6

FIGURE 8: TOGGLE BIT TIMING DIAGRAM

T

CE

T

OE

TWC + T

BLCO

TWO READ CYCLES

WITH SAME OUTPUTS

T

OES

307 ILL F07.1

Six-Byte Sequence for Disabling

Software Data Protection

ADDRESS A

DQ

14-0

7-0

CE#

OE#

WE#

55AA 55 20AA80

T

WP

T

BLC

SW0 SW1 SW2 SW3 SW4 SW5

55555555

2AAA2AAA 55555555

FIGURE 9: SOFTWARE DATA PROTECT DISABLE TIMING DIAGRAM

T

BLCO

T

WC

307 ILL F08.1

14

2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020

Data Sheet

Six-Byte Code for Software Chip-Erase

ADDRESS A

DQ

14-0

7-0

CE#

OE#

WE#

55AA 55 10AA80

T

WP

T

BLC

SW0 SW1 SW2 SW3 SW4 SW5

55555555

FIGURE 10: SOFTWARE CHIP-ERASE TIMING DIAGRAM

T

SCE

2AAA2AAA 55555555

T

BLCO

307 ILL F09.2

Three-Byte Sequence

for Software ID Entry

ADDRESS A

DQ

14-0

7-0

CE#

OE#

WE#

T

WP

SW0 SW1 SW2

5555

55AA BF

T

BLC

FIGURE 11: SOFTWARE ID ENTRY AND READ

90

00002AAA 00015555

T

AA

DEVICE ID

T

IDA

DEVICE ID = 10H for SST29EE020

= 12H for SST29LE020/29VE020

307 ILL F10.2

15

Three-Byte Sequence

for Software ID Exit and Reset

2 Mbit Page-Mode EEPROM

SST29EE020 / SST29LE020 / SST29VE020

Data Sheet

ADDRESS A

DQ

14-0

7-0

CE#

OE#

WE#

T

WP

SW0 SW1 SW2

2AAA5555

55AA F0

T

BLC

FIGURE 12: SOFTWARE ID EXIT AND RESET

5555

T

IDA

307 ILL F11.0

16

2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020

Data Sheet

V

IHT

ILT

V

HT

REFERENCE POINTS OUTPUTINPUT

V

LT

V

HT

V

LT

307 ILL F12.1

AC test inputs are driven at V inputs and outputs are V

HT

(2.4 V) for a logic “1” and V

IHT

(2.0 V) and VLT (0.8 V). Input rise and fall times (10% ↔ 90%) are <10 ns.

FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS

TEST LOAD EXAMPLE

TO TESTER

TO DUT

(0.4 V) for a logic “0”. Measurement reference point s for

IL T

Note: V

- V

HIGH

LOW

INPUT

V

DD

RL

Test

HIGH Test

LOW Test

HIGH

HT

V

LT

V

IHT

V

ILT

C

L

R

L LOW

307 ILL F13.1

FIGURE 14: A TEST LOAD EXAMPLE

17

2 Mbit Page-Mode EEPROM

SST29EE020 / SST29LE020 / SST29VE020

Data Sheet

Start

See Figure 17

Software Data

Protect Write

Command

Set Page

Address

Set Byte

Address = 0

Load Byte

Data

Increment

Byte Address

By 1

No

Byte

Address =

128?

Yes

Wait T

BLCO

Wait for end of

Write (TWC,

Data# Polling bit

or Toggle bit

operation)

Write

Completed

307 ILL F14.1

FIGURE 15: WRITE ALGORITHM

18

2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020

Data Sheet

Internal Timer

Page-Write

Initiated

Wait TWC

Write

Completed

No

Toggle Bit

Page-Write

Initiated

Read a byte

from page

Read same

byte

Does DQ

match?

6

No

Data# Polling

Page-Write

Initiated

Read DQ

7

(Data for last

byte loaded)

Is DQ7 =

true data?

Yes

Write

Completed

FIGURE 16: WAIT OPTIONS

Yes

Write

Completed

307 ILL F15.1

19

2 Mbit Page-Mode EEPROM

SST29EE020 / SST29LE020 / SST29VE020

Data Sheet

Software Data Protect Enable

Command Sequence

Write data: AAH Address: 5555H

Write data: 55H

Address: 2AAAH

Write data: A0H Address: 5555H

Load 0 to

128 Bytes of

page data

Wait T

BLCO

Optional Page Load Operation

Software Data Protect

Disable Command Sequence

Write data: AAH Address: 5555H

Write data: 55H

Address: 2AAAH

Write data: 80H

Address: 5555H

Write data: AAH Address: 5555H

Write data: 55H

Address: 2AAAH

Write data: 20H

Wait T

WC

SDP Enabled

Address: 5555H

Wait T

BLCO

Wait T

WC

SDP Disabled

307 ILL F16.1

FIGURE 17: SOFTWARE DATA PROTECTION FLOWCHARTS

20

2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020

Data Sheet

Software Product ID Entry

Command Sequence

Write data: AAH Address: 5555H

Write data: 55H

Address: 2AAAH

Write data: 90H

Address: 5555H

Pause 10 µs

Read Software ID

Software Product ID Exit &

Reset Command Sequence

Write data: AAH Address: 5555H

Write data: 55H

Address: 2AAAH

Write data: F0H

Address: 5555H

Pause 10 µs

Return to normal

operation

307 ILL F17.1

FIGURE 18: SOFTWARE PRODUCT COMMAND FLOWCHARTS

21

SST29EE020 / SST29LE020 / SST29VE020

Software Chip-Erase

Command Sequence

Write data: AAH Address: 5555H

Write data: 55H

Address: 2AAAH

Write data: 80H

Address: 5555H

2 Mbit Page-Mode EEPROM

Data Sheet

Write data: AAH Address: 5555H

Write data: 55H

Address: 2AAAH

Write data: 10H

Address: 5555H

Wait T

SCE

Chip-Erase

to FFH

307 ILL F18.2

FIGURE 19: SOFTWARE CHIP-ERASE COMMAND CODES

22

2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020

Data Sheet

PRODUCT ORDERING INFORMATION

Device Speed Suffix1 Suffix2

SST29x

E020 - XXX -XX -XX

Package Modifi e r

H = 32 leads or pins Numeric = Die modifier

Package Type

N = PLCC W = TSOP (die up) (8mm x 14mm) E = TSOP (die up) (8mm x 20mm) P = PDIP U = Unencapsulated die

Temperature Range

C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

250 = 250 ns 200 = 200 ns 150 = 150 ns 120 = 120 ns

Voltage

E = 5.0V-only L = 3.0-3.6V V = 2.7-3.6V

23

2 Mbit Page-Mode EEPROM

SST29EE020 / SST29LE020 / SST29VE020

Data Sheet

Valid combinations for SST29EE020

SST29EE020-120-4C-NH SST29EE020-120-4C-WH SST29EE020-120-4C-EH SST29EE020-120-4C-PH SST29EE020-120-4I-NH SST29EE020-120-4I-WH S ST29EE020-120-4I-EH

SST29EE020-150-4C-U2

Valid combinations for SST29LE020

SST29LE020-200-4C-NH SST29LE020-200-4C-WH SST29LE020-200-4C-EH SST29LE020-200-4I-NH SST29LE020-200-4I-WH SST29LE020-200-4I-EH

SST29LE020-250-4C-U2

Valid combinations for SST29VE020

SST29VE020-200-4C-NH SST29VE020-200-4C-WH SST29VE020-200-4C-EH SST29VE020-200-4I-NH SST29VE020-200-4I-WH S ST29VE020-200-4I-EH

SST29VE020-250-4C-U2

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

Note: The software Chip-Erase function is not supported by the industrial temperature part.

Please contact SST, if you require this function for an industrial temperature part.

24

2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020

Data Sheet

PACKAGING DIAGRAMS

TOP VIEW SIDE VIEW BOTT OM VIEW

.485 .495

Optional

Pin #1 Identifier

.042 .048

.447 .453

1232

.020 R. MAX.

.023 .029

x 30˚

.106 .112

.030 .040

R.

.042 .048

.547

.585

.553

.595

.050 BSC.

Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (min/max).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

.026 .032

.050 BSC.

32-LEAD PLASTI C LEA D CHIP CARRIER (PLCC)

ACKAGE CODE: NH

SST P

Pin # 1 Identifier

.125 .140

.075 .095

.013 .021

.400 BSC

.015 Min.

1.05

0.95

.490 .530

.50

BSC

.026 .032

32.PLCC.NH-ILL.2

12.50

12.30

0.70

0.50

Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (min/max).

3. Coplanarity: 0.1 (±.05) mm.

4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.

32-

LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM

14.20

13.80

8.10

7.90

32.TSOP-WH-ILL.4

0.15

0.05

.270 .170

SST PACKAGE CODE: WH

25

Pin # 1 Identifier

2 Mbit Page-Mode EEPROM

SST29EE020 / SST29LE020 / SST29VE020

Data Sheet

1.05

0.95

.50

BSC

18.50

18.30

0.70

0.50

Note: 1. Complies with JEDEC publication 95 MO-142 BD dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (min/max).

3. Coplanarity: 0.1 (±.05) mm.

4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.

20.20

19.80

32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 20MM SST PACKAGE CODE: EH

32

C

L

8.10

7.90

32.TSOP-EH-ILL.4

0.15

0.05

.27 .17

.600 .625

.530 .550

.600 BSC

32.pdipPH-ILL.2

15˚

0˚

.070 .080

1

1.645

1.655

.045 .065

Pin #1 Identifier

.065 .075

Base Plane

Seating Plane

.015 .050

Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.

32-

PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP)

ACKAGE CODE: PH

SST P

2. All linear dimensions are in inches (min/max).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.

.016 .022

.100 BSC

.120 .150

.170 .200

.008 .012

7˚

4 PLCS.

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.ssti.com

26