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查询SST29EE010-120-3C-E供应商
1 Megabit (128K x 8) Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
FEATURES:
• Single Voltage Read and Write Operations
– 5.0V-only for the 29EE010
– 3.0V-only for the 29LE010
– 2.7V-only for the 29VE010
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Current: 20 mA (typical) for 5V and
10 mA (typical) for 3.0/2.7V
– Standby Current: 10 µA (typical)
• Fast Page-Write Operation
– 128 Bytes per Page, 1024 Pages
– Page-Write Cycle: 5 ms (typical)
– Complete Memory Rewrite: 5 sec (typical)
– Effective Byte-write Cycle Time: 39 µs
(typical)
Data Sheet
• Fast Read Access Time
– 5.0V-only operation: 90 and 120 ns
– 3.0V-only operation: 150 and 200 ns
– 2.7V-only operation: 200 and 250 ns
• Latched Address and Data
• Automatic Write Timing
– Internal V
• End of Write Detection
– Toggle Bit
– Data# Polling
• Hardware and Software Data Protection
• TTL I/O Compatibility
• JEDEC Standard Byte-wide EEPROM Pinouts
• Packages Available
– 32-Pin TSOP (8x20 & 8x14 mm)
– 32-Lead PLCC
– 32 Pin Plastic DIP
Generation
pp
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PRODUCT DESCRIPTION
The 29EE010/29LE010/29VE010 are 128K x 8 CMOS
page mode EEPROMs manufactured with SST’s proprietary, high performance CMOS SuperFlash technology.
The split gate cell design and thick oxide tunneling
injector attain better reliability and manufacturability
compared with alternate approaches. The 29EE010/
29LE010/29VE010 write with a single power supply.
Internal Erase/Program is transparent to the user. The
29EE010/29LE010/29VE010 conform to JEDEC standard pinouts for byte-wide memories.
Featuring high performance page write, the 29EE010/
29LE010/29VE010 provide a typical byte-write time of
39 µsec. The entire memory, i.e., 128K bytes, can be
written page by page in as little as 5 seconds, when using
interface features such as Toggle Bit or Data# Polling to
indicate the completion of a write cycle. To protect
against inadvertent write, the 29EE010/29LE010/
29VE010 have on-chip hardware and software data
protection schemes. Designed, manufactured, and
tested for a wide spectrum of applications, the 29EE010/
29LE010/29VE010 are offered with a guaranteed pagewrite endurance of 104 or 103 cycles. Data retention is
rated at greater than 100 years.
The 29EE010/29LE010/29VE010 are suited for applications that require convenient and economical updating of
program, configuration, or data memory. For all system
applications, the 29EE010/29LE010/29VE010 significantly improve performance and reliability, while lowering power consumption, when compared with floppy disk
or EPROM approaches. The 29EE010/29LE010/
29VE010 improve flexibility while lowering the cost for
program, data, and configuration storage applications.
To meet high density, surface mount requirements, the
29EE010/29LE010/29VE010 are offered in 32-pin
TSOP and 32-lead PLCC packages. A 600-mil, 32-pin
PDIP package is also available. See Figures 1 and 2 for
pinouts.
Device Operation
The SST page mode EEPROM offers in-circuit electrical
write capability. The 29EE010/29LE010/29VE010 does
not require separate erase and program operations. The
internally timed write cycle executes both erase and
program transparently to the user. The 29EE010/
29LE010/29VE010 have industry standard optional
Software Data Protection, which SST recommends always to be enabled. The 29EE010/29LE010/29VE010
are compatible with industry standard EEPROM pinouts
and functionality.
Read
The Read operations of the 29EE010/29LE010/
29VE010 are controlled by CE# and OE#, both have to
be low for the system to obtain data from the outputs.
CE# is used for device selection. When CE# is high, the
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© 1998 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
304-04 12/97
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
chip is deselected and only standby power is consumed.
OE# is the output control and is used to gate data from
the output pins. The data bus is in high impedance state
when either CE# or OE# is high. Refer to the read cycle
timing diagram for further details (Figure 3).
Write
The Page Write to the SST29EE010/29LE010/29VE010
should always use the JEDEC Standard Software Data
Protection (SDP) 3-byte command sequence. The
29EE010/29LE010/29VE010 contain the optional
JEDEC approved Software Data Protection scheme.
SST recommends that SDP always be enabled, thus, the
description of the Write operations will be given using the
SDP enabled format. The 3-byte SDP Enable and SDP
Write commands are identical; therefore, any time a
SDP Write command is issued, software data protection is automatically assured. The first time the 3-byte
SDP command is given, the device becomes SDP enabled. Subsequent issuance of the same command
bypasses the data protection for the page being written.
At the end of the desired page write, the entire device
remains protected. For additional descriptions, please
see the application notes on “The Proper Use of JEDEC
Standard Software Data Protection” and “Protecting
Against Unintentional Writes When Using Single Power
Supply Flash Memories” in this data book.
The Write operation consists of three steps. Step 1 is the
three byte load sequence for Software Data Protection.
Step 2 is the byte-load cycle to a page buffer of the
29EE010/29LE010/29VE010. Steps 1 and 2 use the
same timing for both operations. Step 3 is an internally
controlled write cycle for writing the data loaded in the
page buffer into the memory array for nonvolatile storage. During both the SDP 3-byte load sequence and the
byte-load cycle, the addresses are latched by the falling
edge of either CE# or WE#, whichever occurs last. The
data is latched by the rising edge of either CE# or WE#,
whichever occurs first. The internal write cycle is initiated
by the T
timer after the rising edge of WE# or CE#,
BLCO
whichever occurs first. The write cycle, once initiated, will
continue to completion, typically within 5 ms. See Figures 4 and 5 for WE# and CE# controlled page write cycle
timing diagrams and Figures 14 and 16 for flowcharts.
The Write operation has three functional cycles: the
Software Data Protection load sequence, the page load
cycle, and the internal write cycle. The Software Data
Protection consists of a specific three byte load sequence that allows writing to the selected page and will
leave the 29EE010/29LE010/29VE010 protected at the
end of the page write. The page load cycle consists of
loading 1 to 128 bytes of data into the page buffer. The
internal write cycle consists of the T
time-out and the
BLCO
write timer operation. During the Write operation, the only
valid reads are Data# Polling and Toggle Bit.
The Page-Write operation allows the loading of up to 128
bytes of data into the page buffer of the 29EE010/
29LE010/29VE010 before the initiation of the internal
write cycle. During the internal write cycle, all the data in
the page buffer is written simultaneously into the memory
array. Hence, the page-write feature of 29EE010/
29LE010/29VE010 allow the entire memory to be written
in as little as 5 seconds. During the internal write cycle,
the host is free to perform additional tasks, such as to
fetch data from other locations in the system to set up the
write to the next page. In each Page-Write operation, all
the bytes that are loaded into the page buffer must have
the same page address, i.e. A7 through A16. Any byte not
loaded with user data will be written to FF.
See Figures 4 and 5 for the page-write cycle timing
diagrams. If after the completion of the 3-byte SDP load
sequence or the initial byte-load cycle, the host loads a
second byte into the page buffer within a byte-load cycle
time (T
) of 100 µs, the 29EE010/29LE010/29VE010
BLC
will stay in the page load cycle. Additional bytes are then
loaded consecutively. The page load cycle will be terminated if no additional byte is loaded into the page buffer
within 200 µs (T
) from the last byte-load cycle, i.e.,
BLCO
no subsequent WE# or CE# high-to-low transition after
the last rising edge of WE# or CE#. Data in the page
buffer can be changed by a subsequent byte-load cycle.
The page load period can continue indefinitely, as long
as the host continues to load the device within the byteload cycle time of 100 µs. The page to be loaded is
determined by the page address of the last byte loaded.
Software Chip-Erase
The 29EE010/29LE010/29VE010 provide a Chip-Erase
operation, which allows the user to simultaneously clear
the entire memory array to the “1” state. This is useful
when the entire device must be quickly erased.
The Software Chip-Erase operation is initiated by using
a specific six byte-load sequence. After the load sequence, the device enters into an internally timed cycle
similar to the write cycle. During the erase operation, the
only valid read is Toggle Bit. See Table 4 for the load
sequence, Figure 9 for timing diagram, and Figure 18 for
the flowchart.
© 1998 Silicon Storage Technology, Inc. 304-04 12/97
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
Write Operation Status Detection
The 29EE010/29LE010/29VE010 provide two software
means to detect the completion of a write cycle, in order
to optimize the system write cycle time. The software
detection includes two status bits: Data# Polling (DQ7)
and Toggle Bit (DQ6). The end of write detection mode is
enabled after the rising WE# or CE# whichever occurs
first, which initiates the internal write cycle.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data#
Polling or Toggle Bit read may be simultaneous with the
completion of the write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ7 or DQ6. In order to
prevent spurious rejection, if an erroneous result occurs,
the software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are valid, then the device has completed the write
cycle, otherwise the rejection is valid.
Data# Polling (DQ7)
When the 29EE010/29LE010/29VE010 are in the internal write cycle, any attempt to read DQ7 of the last byte
loaded during the byte-load cycle will receive the complement of the true data. Once the write cycle is completed, DQ7 will show true data. The device is then ready
for the next operation. See Figure 6 for Data# Polling
timing diagram and Figure 15 for a flowchart.
Toggle Bit (DQ6)
During the internal write cycle, any consecutive attempts
to read DQ6 will produce alternating 0’s and 1’s, i.e.
toggling between 0 and 1. When the write cycle is
completed, the toggling will stop. The device is then
ready for the next operation. See Figure 7 for Toggle Bit
timing diagram and Figure 15 for a flowchart. The initial
read of the Toggle Bit will typically be a “1”.
Data Protection
The 29EE010/29LE010/29VE010 provide both hardware and software features to protect nonvolatile data
from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than
5 ns will not initiate a write cycle.
VCC Power Up/Down Detection: The write operation is
inhibited when VCC is less than 2.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down.
Software Data Protection (SDP)
The 29EE010/29LE010/29VE010 provide the JEDEC
approved optional software data protection scheme for
all data alteration operations, i.e., Write and Chip erase.
With this scheme, any write operation requires the inclusion of a series of three byte-load operations to precede
the data loading operation. The three byte-load sequence is used to initiate the write cycle, providing
optimal protection from inadvertent write operations,
e.g., during the system power-up or power-down. The
29EE010/29LE010/29VE010 are shipped with the software data protection disabled.
The software protection scheme can be enabled by
applying a three-byte sequence to the device, during a
page-load cycle (Figures 4 and 5). The device will then
be automatically set into the data protect mode. Any
subsequent write operation will require the preceding
three-byte sequence. See Table 4 for the specific software command codes and Figures 4 and 5 for the timing
diagrams. To set the device into the unprotected mode,
a six-byte sequence is required. See Table 4 for the
specific codes and Figure 8 for the timing diagram. If a
write is attempted while SDP is enabled the device will be
in a non-accessible state for ~ 300 µs. SST recommends
Software Data Protection always be enabled. See Figure
16 for flowcharts.
The 29EE010/29LE010/29VE010 Software Data Protection is a global command, protecting (or unprotecting)
all pages in the entire memory array once enabled (or
disabled). Therefore using SDP for a single page write
will enable SDP for the entire array. Single pages by
themselves cannot be SDP enabled or disabled.
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
Single power supply reprogrammable nonvolatile
memories may be unintentionally altered. SST strongly
recommends that Software Data Protection (SDP) always be enabled. The 29EE010/29LE010/29VE010
should be programmed using the SDP command sequence. SST recommends the SDP Disable Command
Sequence not be issued to the device prior to writing.
Please refer to the following Application Notes located at
the back of this databook for more information on using
SDP:
• Protecting Against Unintentional Writes When Using
Single Power Supply Flash Memories
• The Proper Use of JEDEC Standard Software Data
Protection
Product Identification
The product identification mode identifies the device as
the 29EE010/29LE010/29VE010 and manufacturer as
SST. This mode may be accessed by hardware or
software operations. The hardware operation is typically
used by a programmer to identify the correct algorithm
for the 29EE010/29LE010/29VE010. Users may wish to
use the software product identification operation to identify the part (i.e. using the device code) when using
multiple manufacturers in the same socket. For details,
see Table 3 for hardware operation or Table 4 for
software operation, Figure 10 for the software ID entry
and read timing diagram and Figure 17 for the ID entry
command sequence flowchart. The manufacturer and
device codes are the same for both operations.
TABLE 1: PRODUCT IDENTIFICATION TABLE
Byte Data
Manufacturer’s Code 0000 H BF H
29EE010 Device Code 0001 H 07 H
29LE010 Device Code 0001 H 08 H
29VE010 Device Code 0001 H 08 H
304 PGM T1.1
Product Identification Mode Exit
In order to return to the standard read mode, the Software Product Identification mode must be exited. Exiting
is accomplished by issuing the Software ID Exit (reset)
operation, which returns the device to the read operation.
The Reset operation may also be used to reset the
device to the read mode after an inadvertent transient
condition that apparently causes the device to behave
abnormally, e.g. not read correctly. See Table 4 for
software command codes, Figure 11 for timing waveform and Figure 17 for a flowchart.
FUNCTIONAL BLOCK DIAGRAM OF SST 29EE010/29LE010/29VE010
1,048,576 Bit
X-Decoder
A
- A
16
0
CE#
OE#
WE#
© 1998 Silicon Storage Technology, Inc. 304-04 12/97
Address buffer & Latches
Control Logic
Y-Decoder and Page Latc hes
I/O Buffers and Data Latches
4
EEPROM
Cell Array
DQ
- DQ
7
0
304 MSW B1.0
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
A11
A9
A8
A13
A14
NC
WE#
Vcc
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Standard Pinout
FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP PACKAGES
NC
A16
A15
A12
DQ0
DQ1
DQ2
Vss
1
2
3
4
A7
5
A6
6
A5
7
A4
A3
A2
A1
A0
32-Pin PDIP
8
Top View
9
10
11
12
13
14
15
16
Vcc
32
WE#
31
NC
30
A14
29
A13
28
A8
27
A9
26
A11
25
OE#
24
A10
23
CE#
22
DQ7
21
DQ6
20
DQ5
19
DQ4
18
DQ3
17
Top View
Die up
DQ0
A15 NC WE#
A12 A16 Vcc NC
A7
A6
A5
A4
A3
A2
A1
A0
4 3 2 1 32 31 30
5
6
7
8
32-Lead PLCC
9
10
11
12
13
14 15 16 17 18 19 20
DQ1 Vss DQ4 DQ6
DQ2 DQ3 DQ5
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Top View
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A1
A2
A3
1
2
3
304 MSW F01.1
4
5
6
A14
29
A13
28
A8
27
A9
26
A11
25
OE#
24
A10
23
CE#
22
DQ7
21
304 MSW F02.1
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FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN PLASTIC DIPS AND 32-LEAD PLCCS
TABLE 2: PIN DESCRIPTION
Symbol Pin Name Functions
A16-A
7
Row Address Inputs To provide memory addresses. Row addresses define a page for a
write cycle.
A6-A
0
Column Address Column Addresses are toggled to load page data.
Inputs
DQ7-DQ
Data Input/output To output data during read cycles and receive input data during write
0
cycles. Data is internally latched during a write cycle. The outputs are in
tri-state when OE# or CE# is high.
CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the write operations
Vcc Power Supply To provide 5-volt supply (± 10%) for the 29EE010, 3-volt supply (3.0-3.6V)
for the 29LE010 and 2.7-volt supply (2.7-3.6V) for the 29VE010
Vss Ground
NC No Connection Unconnected pins.
304 PGM T2.0
© 1998 Silicon Storage Technology, Inc. 304-04 12/97
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
TABLE 3: OPERATION MODES SELECTION
Mode CE# OE# WE# DQ Address
Read V
Page Write V
Standby V
IL
IL
IH
Write Inhibit X V
Write Inhibit X X V
Software Chip Erase V
IL
Product Identification
Hardware Mode V
Software Mode V
SDP Enable Mode V
SDP Disable Mode V
IL
IL
IL
IL
TABLE 4: SOFTWARE COMMAND CODES
Command 1st Bus 2nd Bus 3rd Bus 4th Bus 5th Bus 6th Bus
Sequence Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle
Software Data 5555H AAH 2AAAH 55H 5555H A0H Addr
Protect Enable
& Page Write
Software Data 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 20H
Protect Disable
Software Chip 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Erase
Software ID Entry 5555H AAH 2AAAH 55H 5555H 90H
Addr
(1)
Data Addr
V
IL
V
IH
V
IH
V
IL
D
D
OUT
IN
X X High Z X
IL
V
IH
V
IL
X High Z/ D
IH
V
IL
V
IH
High Z/ D
D
IN
Manufacturer Code (BF) A16 - A1 = VIL, A9 = VH, A0 = V
OUT
OUT
Device Code (see notes) A16 - A1 = VIL, A9 = VH, A0= V
V
IH
V
IH
V
IH
V
IL
V
IL
V
IL
(1)
Data Addr
(1)
Data Addr
(1)
Data Addr
(2)
Data
A
IN
A
IN
X
X
AIN, See Table 4
See Table 4
See Table 4
See Table 4
(1)
Data Addr
304 PGM T3.0
(1)
Data
IL
IH
Software ID Exit 5555H AAH 2AAAH 55H 5555H F0H
Alternate Software 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 60H
ID Entry
Notes:
Notes for Software Product ID Command Code:
© 1998 Silicon Storage Technology, Inc. 304-04 12/97
(3)
(1)
Address format A14-A0 (Hex), Addresses A15 and A16 are a “Don’t Care”.
(2)
Page Write consists of loading up to 128 bytes (A6 - A0).
(3)
Alternate 6 byte software Product-ID Command Code
(4)
The software chip erase function is not supported by the industrial temperature part.
Please contact SST, if you require this function for an industrial temperature part.
1. With A
2. The device does not remain in Software Product ID Mode if powered down.
=0; SST Manufacturer Code = BFH, is read with A0 = 0,
14 -A1
29EE010 Device Code = 07H, is read with A0 = 1.
29LE010/29VE010 Device Code = 08H, is read with A0 = 1.
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304 PGM T4.1
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress
Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device
at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied.
Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias ................................................................................................................. -55°C to +125°C
Storage Temperature ...................................................................................................................... -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential ............................................................................. -0.5V to VCC+ 0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential......................................................... -1.0V to VCC+ 1.0V
Voltage on A9 Pin to Ground Potential ................................................................................................ -0.5V to 14.0V
Package Power Dissipation Capability (Ta = 25°C) ...........................................................................................1.0W
Through Hole Lead Soldering Temperature (10 Seconds) .............................................................................. 300°C
Surface Mount Lead Soldering Temperature (3 Seconds)............................................................................... 240°C
Output Short Circuit Current
(1)
Note:
Outputs shorted for no more than one second. No more than one output shorted at a time.
(1)
....................................................................................................................... 100 mA
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4
5
29EE010 OPERATING RANGE
Range Ambient Temp V
Commercial 0°C to +70°C 5V±10%
Industrial -40°C to +85°C 5V±10%
29LE010 OPERATING RANGE
Range Ambient Temp V
Commercial 0°C to +70°C 3.0V to 3.6V
Industrial -40°C to +85°C 3.0V to 3.6V
29VE010 OPERATING RANGE
Range Ambient Temp V
Commercial 0°C to +70°C 2.7V to 3.6V
Industrial -40°C to +85°C 2.7V to 3.6V
CC
CC
CC
AC CONDITIONS OF TEST
Input Rise/Fall Time......... 10 ns
Output Load..................... 1 TTL Gate and CL = 100 pF
See Figures 12 and 13
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© 1998 Silicon Storage Technology, Inc. 304-04 12/97
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
TABLE 5: 29EE010 DC OPERATING CHARACTERISTICS VCC = 5V±10%
Limits
Symbol Parameter Min Max Units Test Conditions
I
I
I
I
I
V
V
V
V
V
I
CC
SB1
SB2
LI
LO
IL
IH
OL
OH
H
H
Power Supply Current CE#=OE#=V
WE#=V
IL,
Read 30 mA Address input = VIL/VIH, at f=1/TRC Min.,
VCC=VCC Max
Write 50 mA CE#=WE#=V
IL,
Standby VCC Current 3 mA CE#=OE#=WE#=V
(TTL input)
Standby V
Current 50 µA CE#=OE#=WE#=VCC -0.3V.
CC
(CMOS input) VCC = VCC Max.
Input Leakage Current 1 µA VIN =GND to VCC, V
Output Leakage Current 1 0 µA V
=GND to VCC, VCC = VCC Max.
OUT
Input Low Voltage 0.8 V VCC = VCC Max.
Input High Voltage 2.0 V VCC = VCC Max.
Output Low Voltage 0.4 V IOL = 2.1 mA, V
Output High Voltage 2.4 V IOH = -400µA, V
Supervoltage for A
9
11.6 12.4 V CE# = OE# =VIL, WE# = V
Supervoltage Current 100 µA CE# = OE# = VIL, WE# = VIH,
for A
9
A9 = VH Max.
OE#=V
IH, VCC =VCC
CC
= VCC Min.
CC
= VCC Min.
CC
, all I/Os open,
IH
IH, VCC =VCC
Max.
= VCC Max.
IH
Max.
304 PGM T5.0
T
ABLE
6: 29LE010/29VE010 DC O
PERATING CHARACTERISTICS
VCC = 3.0-3.6
FOR
29LE010, VCC = 2.7-3.6
Limits
Symbol Parameter Min Max Units Test Conditions
I
CC
Power Supply Current CE#=OE#=V
WE#=V
IL,
Read 12 mA Address input = VIL/VIH, at f=1/TRC Min.,
VCC=VCC Max
I
SB1
Write 15 mA CE#=WE#=V
Standby VCC Current 1 mA CE#=OE#=WE#=V
IL,
(TTL input)
I
SB2
Standby V
Current 15 µA CE#=OE#=WE#=VCC -0.3V.
CC
(CMOS input) VCC = VCC Max.
I
LI
I
LO
V
IL
V
IH
V
OL
V
OH
V
H
I
H
Input Leakage Current 1 µA VIN =GND to VCC, V
Output Leakage Current 10 µA V
=GND to VCC, VCC = VCC Max.
OUT
Input Low Voltage 0.8 V VCC = VCC Max.
Input High Voltage 2.0 V VCC = VCC Max.
Output Low Voltage 0.4 V IOL = 100 µA, V
Output High Voltage 2.4 V IOH = -100 µA, V
Supervoltage for A
9
11.6 12.4 V CE# = OE# =VIL, WE# = V
Supervoltage Current 100 µA CE# = OE# = VIL, WE# = VIH,
for A
9
A9 = VH Max.
OE#=V
IH, VCC =VCC
CC
= VCC Min.
CC
= VCC Min.
CC
FOR
29VE010
, all I/Os open,
IH
IH, VCC =VCC
Max.
= VCC Max.
IH
Max.
304 PGM T6.0
© 1998 Silicon Storage Technology, Inc. 304-04 12/97
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
TABLE 7: POWER-UP TIMINGS
Symbol Parameter Maximum Units
T
PU-READ
T
PU-WRITE
TABLE 8: CAPACITANCE (Ta = 25 °C, f=1 MHz, other pins open)
Parameter Description Test Condition Maximum
C
I/O
(1)
C
IN
(1)
Note:
TABLE 9: RELIABILITY CHARACTERISTICS
Symbol Parameter Minimum Specification Units Test Method
N
END
(1)
T
DR
V
ZAP_HBM
V
ZAP_MM
(1)
I
LTH
Note:
(2)
(1)
(1)
(1)
This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Power-up to Read Operation 100 µs
Power-up to Write Operation 5 ms
I/O Pin Capacitance V
Input Capacitance V
Endurance 10,000
(2)
0V 12 pF
I/O =
0V 6 pF
IN =
Cycles MIL-STD-883, Method 1033
Data Retention 100 Years JEDEC Standard A103
(1)
ESD Susceptibility 1000 Volts JEDEC Standard A114
Human Body Model
(1)
ESD Susceptibility 200 Volts JEDEC Standard A115
Machine Model
Latch Up 100 mA JEDEC Standard 78
(1)
This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
See Ordering Information for desired type.
304 PGM T7.0
304 PGM T8.0
304 PGM T9.1
1
2
3
4
5
6
7
8
9
10
© 1998 Silicon Storage Technology, Inc. 304-04 12/97
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
AC CHARACTERISTICS
TABLE 10: 29EE010 READ CYCLE TIMING PARAMETERS
29EE010-90 29EE010-120
Symbol Parameter Min Max Min Max Units
T
T
T
T
T
T
T
T
T
RC
CE
AA
OE
CLZ
OLZ
CHZ
OHZ
OH
(1)
(1)
(1)
(1)
(1)
Read Cycle time 90 120 ns
Chip Enable Access Time 90 120 ns
Address Access Time 90 120 ns
Output Enable Access Time 40 50 ns
CE# Low to Active Output 0 0 ns
OE# Low to Active Output 0 0 ns
CE# High to High-Z Output 30 30 ns
OE# High to High-Z Output 3 0 30 ns
Output Hold from Address 0 0 ns
Change
304 PGM T10.1
TABLE 11: 29LE010 READ CYCLE TIMING PARAMETERS
29LE010-150 29LE010-200
Symbol Parameter Min Max Min Max Units
T
T
T
T
T
T
T
T
T
RC
CE
AA
OE
CLZ
OLZ
CHZ
OHZ
OH
(1)
(1)
(1)
(1)
(1)
Read Cycle time 150 200 ns
Chip Enable Access Time 150 200 ns
Address Access Time 150 200 ns
Output Enable Access Time 60 100 ns
CE# Low to Active Output 0 0 ns
OE# Low to Active Output 0 0 ns
CE# High to High-Z Output 30 50 ns
OE# High to High-Z Output 30 50 ns
Output Hold from Address Change 0 0 ns
304 PGM T11.0
TABLE 12: 29VE010 READ CYCLE TIMING PARAMETERS
29VE010-200 29VE010-250
Symbol Parameter Min Max Min Max Units
T
T
T
T
T
T
T
T
T
RC
CE
AA
OE
CLZ
OLZ
CHZ
OHZ
OH
(1)
(1)
(1)
(1)
(1)
Read Cycle time 200 250 ns
Chip Enable Access Time 200 250 ns
Address Access Time 200 250 ns
Output Enable Access Time 100 120 ns
CE# Low to Active Output 0 0 ns
OE# Low to Active Output 0 0 ns
CE# High to High-Z Output 50 50 ns
OE# High to High-Z Output 50 50 ns
Output Hold from Address Change 0 0 ns
304 PGM T12.0
© 1998 Silicon Storage Technology, Inc. 304-04 12/97
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
TABLE 13: PAGE-WRITE CYCLE TIMING PARAMETERS
29EE010 29LE/VE010
Symbol Parameter Min Max Min Max Units
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Note:
WC
AS
AH
CS
CH
OES
OEH
CP
WP
DS
DH
(1)
BLC
(1)
BLCO
IDA
SCE
(1)
This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
Write Cycle (erase and program) 10 10 ms
Address Setup Time 0 0 ns
Address Hold Time 50 70 ns
WE# and CE# Setup Time 0 0 ns
WE# and CE# Hold Time 0 0 ns
OE# High Setup Time 0 0 ns
OE# High Hold Time 0 0 ns
CE# Pulse Width 70 120 ns
WE# Pulse Width 70 120 ns
Data Setup Time 35 50 ns
Data Hold Time 0 0 ns
Byte Load Cycle Time 0.05 100 0.05 100 µs
Byte Load Cycle Time 200 200 µs
Software ID Access and Exit Time 10 10 µs
Software Chip Erase 20 20 ms
304 PGM T13.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
© 1998 Silicon Storage Technology, Inc. 304-04 12/97
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
FIGURE 3: READ CYCLE TIMING DIAGRAM
304 AC F03.0
304 AC F04.0
FIGURE 4: WE# CONTROLLED PAGE WRITE CYCLE TIMING DIAGRAM
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
1
2
3
4
5
6
FIGURE 5: CE# CONTROLLED PAGE WRITE CYCLE TIMING DIAGRAM
304 AC F05.0
7
8
9
10
11
12
13
14
304 AC F06.0
FIGURE 6: DATA# POLLING TIMING DIAGRAM
© 1998 Silicon Storage Technology, Inc. 304-04 12/97
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
FIGURE 7: TOGGLE BIT TIMING DIAGRAM
304 AC F07.0
304 AC F08.0
FIGURE 8: SOFTWARE DATA PROTECT DISABLE TIMING DIAGRAM
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
1
2
3
4
5
6
FIGURE 9: SOFTWARE CHIP ERASE TIMING DIAGRAM
DEVICE CODE
304 AC F09.0
7
8
9
10
11
12
13
14
DEVICE CODE = 07 for 29EE010
= 08 for 29LE010/29VE010
FIGURE 10: SOFTWARE ID ENTRY AND READ
© 1998 Silicon Storage Technology, Inc. 304-04 12/97
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304 AC F10.0
15
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
FIGURE 11: SOFTWARE ID EXIT AND RESET
304 AC F11.0
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
2.4
INPUT
0.4
AC test inputs are driven at VOH (2.4 V
points for inputs and outputs are VIH (2.0 V
ns.
FIGURE 12: AC INPUT/OUTPUT REFERENCE WAVEFORMS
2.0
0.8
) for a logic “1” and VOL (0.4 V
TTL
) and V
TTL
TEST LOAD EXAMPLE
TO TESTER
REFERENCE POINTS
(0.8 V
IL
TTL
2.0
OUTPUT
0.8
304 MSW F12.0
) for a logic “0”. Measurement reference
TTL
). Inputs rise and fall times (10% ↔ 90%) are <10
V
CC
RL
HIGH
1
2
3
4
5
6
7
8
9
TO DUT
C
L
FIGURE 13: TEST LOAD EXAMPLE
© 1998 Silicon Storage Technology, Inc. 304-04 12/97
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R
304 MSW F13.0
10
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13
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Page 18
See Figure 16
SST29EE010, SST29LE010, SST29VE010
Start
Software Data
Software Data
Protect Write
Protect Write
Command
Command
Set Page
Address
Set Byte
Address = 0
1 Megabit Page Mode EEPROM
Byte Address
No
Wait for end of
Wait for end of
Write (T
# Polling bit or
Data # Polling bit
Load Byte
Data
Increment
By 1
Byte
Address =
128 ?
Yes
Wait T
BLCO
Wait T
BLCO
, Data
WC
Write (T
Toggle bit or
WC
Toggle bit
operation)
operation)
,
Write
Completed
Figure 14: Write Algorithm
304 MSW F14.0
FIGURE 14: WRITE ALGORITHM
© 1998 Silicon Storage Technology, Inc. 304-04 12/97
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
Internal Timer Toggle Bit
Page W rite
Initiated
Wait T
Completed
WC
Write
No
Page W rite
Initiated
Read a byte
from page
Read same
byte
Does DQ
match?
6
No
Data# Polling
Page W rite
Initiated
Read DQ
(Data for last
byte loaded)
Is DQ7 =
true data?
Write
Completed
7
Yes
1
2
3
4
5
6
7
8
9
Yes
Write
Completed
304 MSW F15.0
FIGURE 15: WAIT OPTIONS
© 1998 Silicon Storage Technology, Inc. 304-04 12/97
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
Software Data Protect Enable
Command Sequence
Write data: AA
Address: 5555
Write data: 55
Address: 2AAA
Write data: A0
Address: 5555
Load 0 to
128 Bytes of
page data
Optional Page Load
Operation
Software Data Protect
Disable Command Sequence
Write data: AA
Address: 5555
Write data: 55
Address: 2AAA
Write data: 80
Address: 5555
Write data: AA
Address: 5555
Write data: 55
Address: 2AAA
Wait T
BLCO
Wait T
WC
SDP Enabled
FIGURE 16: SOFTWARE DATA PROTECTION FLOWCHARTS
Write data: 20
Address: 5555
Wait T
BLCO
Wait T
WC
SDP Disabled
304 MSW F16.0
© 1998 Silicon Storage Technology, Inc. 304-04 12/97
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
Software Product ID Entry
Command Sequence
Write data: AA
Address: 5555
Write data: 55
Address: 2AAA
Write data: 90
Address: 5555
Pause 10 µs
Software Product ID Exit &
Reset Command Sequence
Write data: AA
Address: 5555
Write data: 55
Address: 2AAA
Write data: F0
Address: 5555
Pause 10 µs
1
2
3
4
5
6
7
8
Read Software ID
FIGURE 17: SOFTWARE PRODUCT COMMAND FLOWCHARTS
Return to normal
operation
9
10
11
304 MSW F17.0
12
13
14
15
16
© 1998 Silicon Storage Technology, Inc. 304-04 12/97
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SST29EE010, SST29LE010, SST29VE010
Software Chip-Erase
Command Sequence
Write data: AA
Address: 5555
Write data: 55
Address: 2AAA
Write data: 80
Address: 5555
1 Megabit Page Mode EEPROM
Write data: AA
Address: 5555
Write data: 55
Address: 2AAA
Write data: 10
Address: 5555
Wait T
SCE
Chip Erase
to FFH
304 MSW F18.0
FIGURE 18: SOFTWARE CHIP ERASE COMMAND CODES
© 1998 Silicon Storage Technology, Inc. 304-04 12/97
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
PRODUCT ORDERING INFORMATION
Device Speed Suffix1 Suffix2
SST29XE010 - XXX - XX - XX
Package Modifier
H = 32 leads
Numeric = Die modifier
Package Type
P = PDIP
N = PLCC
E = TSOP (die up) 8x20 mm
W = TSOP (die up) 8x14 mm
U = Unencapsulated die
Operating Temperature
C = Commercial = 0° to 70°C
I = Industrial = -40° to 85°C
Minimum Endurance
3 = 1000 cycles
4 = 10,000 cycles
1
2
3
4
5
6
7
8
Read Access Speed
250 = 250 ns
200 = 200 ns
150 = 150 ns
120 = 120 ns
90 = 90 ns
Voltage
E = 5V-only
L = 3V-only
V = 2.7V-only
9
10
11
12
13
14
15
16
© 1998 Silicon Storage Technology, Inc. 304-04 12/97
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
29EE010 Valid combinations
SST29EE010- 90-4C- EH SST29EE010- 90-4C- NH SST29EE010- 90-4C- PH
SST29EE010-120-4C- EH SST29EE010-120-4C- NH SST29EE010-120-4C- PH
SST29EE010- 90-4C- WH
SST29EE010-120-4C- WH
SST29EE010- 90-4I-EH SST29EE010- 90-4I-NH
SST29EE010-120-4I-EH SST29EE010-120-4I-NH
SST29EE010-120-4C-U2
29LE010 Valid combinations
SST29LE010-150-4C- EH SST29LE010-150-4C- NH SST29LE010-150-4C- PH
SST29LE010-200-4C- EH SST29LE010-200-4C- NH SST29LE010-200-4C- PH
SST29LE010-150-4C- WH
SST29LE010-200-4C- WH
SST29LE010-150-4I-EH SST29LE010-150-4I-NH
SST29LE010-200-4C-U2
29VE010 Valid combinations
SST29VE010-200-4C- EH SST29VE010-200-4C- NH SST29VE010-200-4C- PH
SST29VE010-250-4C- EH SST29VE010-250-4C- NH SST29VE010-250-4C- PH
SST29VE010-200-4C-WH
SST29VE010-250-4C-WH
SST29VE010-200-4I-EH SST29VE010-200-4I-NH
SST29VE010-250-4C-U2
Example:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
Note: The software chip erase function is not supported by the industrial temperature part.
representative to confirm availability of valid combinations and to determine availability of new combinations.
Please contact SST, if you require this function for an industrial temperature part.
© 1998 Silicon Storage Technology, Inc. 304-04 12/97
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
PACKAGING DIAGRAMS
Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (min/max).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
1
2
3
4
5
6
32pn PDIP PH AC.2
7
32-LEAD PLASTIC DUAL-IN-LINE PACKAGE (PDIP)
SST PACKAGE CODE: PH
Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (min/max).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
32pn PLCC NH AC.2
8
9
10
11
12
13
14
15
16
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)
SST PACKAGE CODE: NH
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in metric (min/max).
3. Coplanarity: 0.1 (±.05) mm.
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP)
SST PACKAGE CODE: WH
32pn TSOP WH AC.3
Note: 1. Complies with JEDEC publication 95 MO-142 BD dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in metric (min/max).
3. Coplanarity: 0.1 (±.05) mm.
32pn TSOP EH AC.4
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP)
SST PACKAGE CODE: EH
© 1998 Silicon Storage Technology, Inc. 304-04 12/97
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
SST Area Offices
U.S.A. - California (408) 523-7722
U.S.A. - Florida (813) 771-8819
U.S.A. - Florida (941) 505-8893
U.S.A. - Massachusetts (978) 356-3845
Japan - Yokohama (81) 45-471-1851
Europe - UK (44) 1784-490455
North American Sales Representatives
Alabama
Elcom, Inc. (205) 830-4001
Arizona
QuadRep, Inc. (602) 839-2102
California
Northern
Premier Technical Sales (408) 736-2260
Southern
QuadRep, Inc., San Diego (619) 775-1188
QuadRep, Inc., Irvine (714) 727-4222
Colorado
QuadRep, Inc. (303) 771-6886
Florida
MEC Corporation - Central/East Coast (904) 427-7236
MEC Corporation - South/East Coast (954) 426-8944
MEC Corporation - West Coast (813) 393-5011
Georgia
Elcom, Inc. (770) 447-8200
Iowa
Oasis Sales Corporation (319) 377-8738
Idaho
QuadRep, Inc. (208) 939-9626
Illinois
Oasis Sales Corporation - Northern (847) 640-1850
Rush & West Associates - Southern (314) 965-3322
Kansas
Rush & West Associates (913) 764-2700
Massachusetts
S-J Associates (978) 670-8899
Minnesota
Cahill, Schmitz & Cahill (612) 646-7217
Missouri
Rush & West Associates (314) 965-3322
North Carolina
Elcom, Inc. - Charlotte (704) 543-1229
Elcom, Inc. - Raleigh (919) 743-5200
New Jersey
S-J Associates (609) 866-1234
New Mexico
QuadRep, Inc. (505) 332-2417
New York
S-J Associates - NYC (516) 536-4242
S-J Associates - Upstate (716) 924-1720
Ohio
Great Lakes - Columbus (614) 885-6700
Great Lakes - Cleveland (216) 349-2700
Oregon
Thorson Pacific, Inc. (503) 293-9001
Texas
Tech. Mktg, Inc. - Carrollton (972) 387-3601
Tech. Mktg, Inc. - Houston (713) 783-4497
Tech. Mktg, Inc. - Austin (512) 343-6976
Utah
QuadRep, Inc. (801) 521-4717
Virginia
S-J Associates (703) 533-2233
Washington
Thorson Pacific, Inc. (425) 603-9393
Wisconsin
Oasis Sales Corporation (414) 782-6660
Canada - Toronto
Kaltron Components Inc. (905) 405-6276
Canada - Ottawa
Kaltron Components Inc. (819) 457-1225
Canada - Montreal
Kaltron Components Inc. (514) 696-6589
Canada - B.C.
Thorson Pacific, Inc. (604) 294-3999
Puerto Rico
MEC/Caribe (787) 746-9897
International Sales Representatives & Distributors
Australia
ACD (61) 3-762 7644
Belgium
Memec Brussels (32) 2778-9850
China
Actron Technology Co., Ltd. (86) 21-6482-8021
Denmark
Berendsen Components A/S (45) 39-57-71-10
Ireland
Memec Ireland LTD (353) 61 411842
Finland
OXXO OY AB (358) 9-5842 600
France
RepDesign (33) 1 46 23 7990
A2M (33) 1 46 23 7900
Germany
Endrich Bauelemente
Vertriebs GMBH (49) 7452-60070
Metronik GmbH (49) 89-61108-0
Hong Kong
Actron Technology Co., Ltd. (852) 2727-3978
Serial System (HK) Ltd. (852) 2950-0820
Israel
Elina Electronics (972) 3-649 8543
Italy
Carla Gavazzi Cefra SpA (39) 2-4801.2355
Japan
Asahi Electronics Co., Ltd. (81) 3-3350-5418
Asahi Electronics Co., Ltd. (81) 93-511-6471
Hakuto Co., Ltd. (81) 3-3355-7615
MICROTEK Inc. (81) 3-5300-5525
Ryoden Trading Co., Ltd. (81) 3-5396-6206
Silicon Technology Co., Ltd. (81) 3-3795-6461
Korea
Bigshine Korea Co., Ltd. (82) 2-832-8881
Netherlands
Memec Benelux (31) 40-265-9399
Singapore
Serial System Ltd. (65) 286-1812
South Africa
KH Distributors (27) 11 845-5011
Spain
Tekelec Espana S.A. (34) 13 20 41 60
Sweden
Pelcon Electronics AB (46) 8.795 98 70
Switzerland
Leading Technology (41) 277-21 7-446
Taiwan, R.O.C.
Award Software (886) 22-555-0880
PCT Limited (886) 22-698-0098
Tonsam Corporation (886) 22-651-0011
United Kingdom
Ambar Components, Ltd. (44) 1844-261144
Revised 3-12-98
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.ssti.com • Literature FaxBack 888-221-1178, International 732-544-2873
© 1998 Silicon Storage Technology, Inc. 304-04 12/97
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