Datasheet SST28PC040 Datasheet (Silicon Storage Technology)

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Data Sheet

SST 28PC040

5.0V-only 4 Megabit PCMCIA Interface EEPROM

June 1997

This specification is subject to change without notice.

14.1

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Features:

SST 28PC040

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

Single 5.0-Volt Read and Write Operations CMOS SuperFlash EEPROM Technology

Endurance: 250,000 Cycles (typical) Greater than 100 Years Data Retention

Memory Organization:

512K x 8/1M x 4 PCMCIA Common Memory 1K x 8/2K x 4 Attribute Memory for User Alterable PCMCIA Attribute Memory

Low Power Consumption:

Active Current: 15 mA (typical) Standby Current: 5 µA (typical)

Fast Sector Erase/Byte Program Operation

Byte Program Time: 30 µs (typical) Sector Erase Time: 60 µs (typical) Complete Memory Rewrite: 15 sec (typical)

Fast Access Time: 150 and 250 ns

Product Description

The 28PC040 is organized as a 512K x 8 (bits) common memory array plus a 1K x 8 attribute memory array. The attribute memory can be accessed by asserting REG# or issuing an Enable_Attribute command. Either one nibble or two nibbles in a byte can be read in one cycle with internal decoding of CEL#, CEH#, and HB. The 28PC040 must be configured as a pair per 1Mbyte of PCMCIA application memory. Each byte in the PCMCIA memory map consists of two nibbles, one from each 28PC040 in the pair.

Each 28PC040 has 4M bits of common memory and 8K bits of attribute memory and is manufactured using SST’s proprietary, high performance CMOS SuperFlash EEPROM Technology. The split gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternative approaches. The 28PC040 erases and programs with a 5.0 volt only power supply.

Figure 1 shows the functional blocks of the 28PC040, and shows the memory map consisting of common memory array and the attribute memory array. Figure 2 shows the pin assignments for the TSOP package. Pin description and operation modes are described in Tables 1 through 6.

Sector Erase Capability:

256 Bytes/512 Nibbles per Sector

Selectable single Nibble & dual Nibble

Access PCMCIA Byte-wide or Word wide selection Latched Address and Data Hardware and Software Data Protection

WP Pin Hardware Write Protection

7-Read-Cycle-Sequence Software Data

Protection

End of Write Detection

Toggle Bit

Data# Polling

TTL I/O Compatibility Packages Available

40-Pin TSOP (10 mm x 14 mm)

Device Operation

Commands are used to initiate the memory operations functions of the device. Commands are written to the device using standard microprocessor write sequences. The device is selected by applying the proper input levels to CS0 and CS (see Table 2A). A command is written by asserting WE# low while keeping CEL# or CEH# low. The address bus is latched on the falling edge of WE#, CEL#, or CEH#, whichever occurs last. The data bus is latched on the rising edge of WE# or CEL#, whichever occurs first. Note, during the software data protection sequence the address are latched on the rising edge of OE# or CEL#, whichever occurs first.

Memory Map

The 28PC040 consists of two memory arrays: the common memory and the attribute memory. The common memory consists of 1M-nibbles and is used for storing data, program codes and other user files. The total available attribute memory is 2K nibbles. The selection between the common and attribute memory maps is controlled by the REG# pin. When REG# is high, the common memory is active. Alternatively, the attribute memory can be accessed through an Enable_Attribute command, which enables the attribute memory access independent of REG#.

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SST 28PC040

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

Two sectors of the attribute memory are used to store the map of nonconforming sectors. Refer to Table 9 for details. A maximum of zero nonconforming attribute memory sectors and five nonconforming common memory sectors are allowed when the 28PC040 is shipped.

Command Definitions

Table 7 contains a command list and a brief summary of the commands. The following is a detailed description of the operations initiated by each command.

Sector_Erase Operation

The Sector_Erase operation erases all byte within a sector and is initiated by a setup command and an execute command. A sector contains 512 nibbles. This sector erasability enhances the flexibility and usefulness of the 28PC040, since most applications only need to change a small number of bytes or sectors, not the entire chip.

The setup command is performed by writing 22H to the device. To execute the Sector_Erase operation, the execute command (DDH) must be written to the device. The erase operation begins with the rising edge of the WE# pulse and terminates with the Reset command. The device has an internal timer that will terminate the erase (into the read mode) after TSE if no Reset command has been sent. The end of Erase can be determined using either Data# Polling, Toggle Bit or Successive Reads detection methods. See Figure 9 for timing waveforms.

The two-step sequence of setup command followed by an execute command ensures that only memory contents within the addressed sector are erased and other sectors are not inadvertently erased.

Sector_Erase Flowchart Description

Fast and reliable erasing of the memory contents within a sector is accomplished by following the algorithmic sector erase flowchart as shown in Figure 20. The Sector_Erase operation will terminate after a maximum of 2 ms, if not interrupted. After the initial 40 µs of erase time, a Reset command can be executed to terminate the erase operation followed by an Erase_Verify operation to assure complete erasure. The algorithmic Sector_Erase operation allows for up to seven erase iterations to complete the Sector_Erase. A sector erase iteration is perform by doubling the algorithmic sector erase sector time (T

= 40 µs

ASE

, 80 µs, 160 µs, 320 µs, 640 µs, 1.28 ms and 2.56 ms). The purpose of the successive erase attempts is to optimize the total time required to erase the sector. An additional 150 erase retries at maximum T

is allowed to ensure erasure.

ASE

Byte_Program Operation

The Byte_Program operation is initiated by writing the setup command (11H). Once the program setup is performed, programming is executed by the next WE# pulse. See Figures 5 and 6 for timing waveforms. The address bus is latched on the falling edge of WE#, CEL# or CEH#, whichever occurs last. The data bus is latched on the rising edge of WE#, CEL# or CEH#, whichever occurs first. The rising edge of WE#, CEL# or CEH#, whichever occurs first, begins the program operation. The program operation is terminated automatically by an internal timer. See Figure 18 for the programming flowchart.

The two-step sequence of a setup command followed command ensures that only the addressed byte is programmed and other bytes are not inadvertently programmed.

Erase_Verify

The Erase_Verify operation is initiated by writing a single command (AAH). The address bus is latched on the falling edge of WE#, CEL#, or CEH#, whichever occurs last. The Erase_Verify is used only to verify that the device has erased prior to programming. The Erase_Verify uses an internal reference level to provide extra margin compared to normal read levels for “FF” data. This operation automatically resets after reading

The Byte_Program Flowchart Description

Programming data into the 28PC040 is accomplished by following the Byte_Program flowchart shown in Figure 18. The Byte_Program command sets up the byte for programming. The address bus is latched on the falling edge of WE#, CEL# or CEH#, whichever occurs last. The data bus is latched on the rising edge of WE#, CEL# or CEH#, whichever occurs first and begins the program operation. The end of program can be

the byte.

This specification is subject to change without notice.

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SST 28PC040

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

detected using either the Data# Polling or Toggle bit.

Reset Operation

The Reset command is provided as a means to safely abort the erase or program command sequences. Follow either setup commands (erase or program) with a write of FFH will safely abort the operation. Memory contents will not be altered. After the Reset command, the device returns to the read mode. The Reset command does not enable software data protection. See Figure 7 for timing waveforms.

Read

The Read operation is initiated by setting CEL#, CEH#, and OE# to logic low and setting WE# to logic high (See Table 3). See Figure 4 for read memory timing diagram. The read operation from the host retrieves data from the array. The device remains enabled for read until another operation mode is accessed. During initial power-up, the device is in the read mode and is software data protected. The device must be unprotected to execute a write command.

The read operation of the 28PC040 is controlled by OE# at logic low and either CEL# and/or CEH# at logic low. When CEL# and CEH# are high, the chip is deselected and only standby power will be consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when both CEL# and CEH# are high or OE# is high.

Enable_Attribute Operation

Attribute memory is access by initiating the Enable_Attribute operation with a single command (88H). Read, Sector_Erase, and Byte Program operations can be performed in the attribute memory. The 1K byte of memory includes the PCMCIA attribute memory information. The REG# pin status has no effect on the operation. To return to common memory operations, a Reset command must be issued. The Reset command enables access to the common memory. (See Figure 8)

Read_ID operation

The Read_ID operation is initiated by writing a single command (99H). A read of address 0000H

will output the manufacturer’s code (BFH). A read of address 0001H will output the device code (11H). Any other valid command will terminate this opera tion.

Data Protection

In order to protect the integrity of nonvolatile data storage, the 28PC040 provides both hardware and software features to prevent inadvertent writes to the device, for example, during system power-up or power-down. Such provisions are described below.

Hardware Data Protection

The 28PC040 is designed with hardware features to prevent inadvertent writes. This is done in the following ways:

1. Write Inhibit Mode: OE# low, CEL# high,

CEH# high, or WE# high will inhibit the write operation.

2. Noise/Glitch Protection: A WE# pulse width of

less than 15 ns will not initiate a write cycle.

3. VCC Power Up/Down Detection: The write op-

eration is inhibited when VCC is less than 2.5 V.

4. After power-down the device is in the read

mode and the device is in the software data protect state.

5. The WP pin at VIH will put the device in the

Write Protect mode.

Software Data Protection (SDP)

The 28PC040 has software methods to further prevent inadvertent writes. In order to perform an erase or program operation, a two-step command sequence consisting of a set-up command followed by an execute command avoids inadvertent erasing and programming of the device.

The 28PC040 will default to software data protection after power up. A sequence of seven consecutive reads at specific addresses will unprotect the device The address sequence is 1823H, 1820H, 1822H, 0418H, 041BH, 0419H, 041AH. The address bus is latched on the rising edge of OE# or CEL#, whichever occurs first. A similar seven read sequence of 1823H, 1820H, 1822H, 0418H, 041BH, 0419H, 040AH will protect

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SST 28PC040

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

the device. Also refer to Figures 10 and 11 for the 7 read cycle sequence Software Data Protection. The I/O pins can be in any state (i.e., high, low, or tristate).

Write Operation Status Detection

The 28PC040 provides two software means to detect the completion of a write cycle, in order to optimize the system write cycle time. The end of a write cycle (erase or program) can be detected by three means: 1) monitoring the Data# Polling bit;

2) monitoring the Toggle bit; or by two successive read of the same data. These three detection mechanisms are described below.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with the DQ used. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid.

Data# Polling (DQ3, DQ7)

The 28PC040 features Data# Polling to indicate the write operation status. During a write operation, any attempt to read the last byte loaded will receive the complement of the true data on DQ and DQ7. Once the write cycle is completed, DQ for the low nibble and DQ7 for the high nibble will show true data. The device is then ready for the next operation. See Figure 14 for Data Polling

timing waveforms. In order for Data# Polling to function correctly, the byte being polled must be erased prior to programming.

Toggle Bit (DQ2, DQ6)

An alternative means for determining the write operation status is by monitoring the Toggle Bit, DQ2 for the low nibble and DQ6 for the high nibble. During a write operation, consecutive attempts to read data from the device will result in DQ2 and DQ6 toggling between logic 0 (low) and logic 1 (high). When the write cycle is completed, the toggling will stop. The device is then ready for the next operation. See Figure 15 for Toggle Bit timing waveforms.

Successive Reads

An alternative means for determining an end of a write cycle is by reading the same address for two consecutive data matches.

Chip select (CS0, CS1)

The 28PC040 provides two user selectable chip select pins, CS0 and CS1. By ordering different part number suffix of a device, the device response only to one of the combinations of CS0 and CS1. See Table 2A. Therefore, there is no need of external decoder for up to 4 pairs of devices. Typically, the CS0 and CS1 are connected to address line A20 and A21. See application note “PCMCIA Memory Cards Made Easy with SST28PC040”.

3 3

This specification is subject to change without notice.

14.5

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SST 28PC040

Control Logic

CEH#

OE#

WE#

CS0

REG#HBWP

RST

RDY/BSY#

CS1

CEL#

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

PCMCIA Control Logic

2048 Sectors Common Memory

X-Decoder

4 Sectors Attribute Memory

(8Kbits)

(4Mbits)

A18-A

Address buffer & Latches

Figure 1: Functional Block Diagram of SST 28PC040

Pin #1 indicator

RST

REG#

A11

A8 A13 A14 A17

WE# VCC

CEH#

A16 A15 A12

A4 A18

RDY/BSY#

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Standard Pinout

Top View

Die up

Y-Decoder

I/O Buffers and Data Latches

DQ7 - DQ

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

CS1 CS0 OE# A10 CEL# DQ7 DQ3 DQ6 DQ2 DQ5 VSS DQ1 DQ4 DQ0 A0 A1 A2 A3 WP HB

Figure 2: Standard Pin Assignments for 40-pin TSOP Pac kages.

This specification is subject to change without notice.

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SST 28PC040

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

Table 1: Pin Description Symbol Pin Name Functions

A18-A

A7-A

DQ7-DQ

CEL#, CEH# Chip Enable To activate the device when CEL# or CEH# is low.

OE# Output Enable To gate the data output buffers. WE# Write Enable To control the write operations. Vcc Power Supply Vss Ground CS0 - CS

HB Half-Byte Selects Odd/Even nibble for chip. WP Write Protect To activate write protect state.

RDY/BSY# Read/Busy This open-drain output requires a 1K pull-up resistor (minimum).

REG# Attribute Memory To switch from common memory to attribute memory.

RST Reset To reset the device after power-on.

Row Address Inputs To provide memory addresses. Row addresses define a sector. Column Address Inputs Selects the byte within the sector. Data Input/Output To output data during read cycles and receive input data during

write cycles. Data is internally latched during a write cycle. The outputs are in tri-state when OE#, CEL# or CEH# is high.

CEL# to enable the low nibble of DQ0 to DQ CEH# to enable the high nibble of DQ4 to DQ

(1)

To provide 5-volt supply (± 10%)

Chip Selects Preset chip selects used for memory pair select.

(1)

When WP is high, the device becomes a ROM, acknowledging all read operation, and will ignore all operations attempting to alter memory array data. See Table 7.

(2)

This pin is low to indicate the chip is busy internally. Any new

instruction must be performed only when RDY/BSY# is high.

There are 1Kbits of attribute memory in the 28PC040 decoded by A9 to A0. REG# can be overridden by the Enable_Attribute command.

(1)

RST must be asserted after power-up. After the falling edge of the RST pulse, the 28PC040 will be ready (RDY/BSY#) in ~ 10ms.

(1)

See Table

(1)

Note:

(1)

This pin is considered as an input for the purposes of the DC Operation Characteristics Table.

(2)

This pin is considered as an output for the purposes of the DC Operation Characteristics Table.

This specification is subject to change without notice.

14.7

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SST 28PC040

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

Table 2: Operation Modes Selection Mode CEL#,

CEH#

Read V Byte Program V Sector Erase V Standby V Write Inhibit X V Write Inhibit X X V Software Chip Erase V Product Identification

Hardware Mode V

Software Mode V SDP Enable & Disable Mode V Enable_Attribute V Reset V

OE# WE# DQ Address

IL IL IL

IL IL IL IL

X X High Z X

OUT

X High Z/ D

High Z/ D

Manufacturer Code (BF)

Device Code (11) A18-A1=VIL, A9=VH, A0=V

OUT OUT

X X See Table 7

A18-A1=VIL, A9=VH, A0=V

See Table 7 See Table 7 See Table 7 See Table 7

Table 2A: Card Decode Table Device Part# Suffix CS

S00A 0 0 S01B 0 1 S10C 1 0 S11D 1 1

Note: The chip is selected by applying the listed logic levels to CS0 and CS1.

The device part # suffix indicates the preset state.

Table 3: Main Memory Read Functions Function Mode REG#CEH#CEL#HB OE# WE# DQ

7-4

(1)

3-0

(2)

A18-A

Standby Mode X H H X X X High Z High Z X Nibble Access (x4) Nibble Access (x4) Byte Access (x8) Odd Nibble Access

Note:

(1)

D15-D

(2)

D7-D

(3)

CS1 and CS0 at active state.

(3) (3)

(3)

in Figure 3

H H L L L H High Z Even Nibble A H H L H L H High Z Odd Nibble A H L L X L H Odd Nibble Even Nibble A H L H X L H Odd Nibble High Z A

(

IN IN IN IN

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This specification is subject to change without notice.

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SST 28PC040

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

Table 4: Main Memory Write Functions Function Mode REG#CEH#CEL#HB OE# WE# DQ

7-4

(1)

3-0

(2)

A18-A

Standby Mode X H H X X X X X X

(3)

H H L L H L X Even Nibble A

(3)

H H L H H L X Odd Nibble A H L L X H L Odd Nibble Even Nibble A

(3)

H L H X H L Odd Nibble X A

Nibble Access (x4) Nibble Access (x4) Byte Access (x8) Odd Nibble Access Write Inhibit X X X X L X X X X

Notes:

(1)

D15-D8 in Figure 3

(2)

D7-D0 in Figure 3

(3)

CS1 and CS0 at active state.

Table 5: Attribute Memory Read Functions Function Mode REG#CEH#CEL#HB OE# WE

7-4

(1)

3-0

(2)

A9-A

Standby Mode X H H X X X High Z High Z X

(4)

L H L L L H High Z Even Nibble A

(4)

L H L H L H High Z Odd Nibble A L L L X L H Odd Nibble Even Nibble A

(4)

L L H X L H Odd Nibble High Z A

Nibble Access (x4) Nibble Access (x4) Byte Access (x8) Odd Nibble Access

Note:

(4)

(1)

D15-D8 in Figure 3

(2)

D7-D0 in Figure 3

(3)

Other addresses are “don’t care” CS1 and CS0 at active state

IN IN IN IN

(3)

IN IN IN IN

Table 6: Attribute Memory Write Functions Function Mode REG#CEH#CEL#HB OE# WE#DQ

7-4

(1)

3-0

(2)

A9-A

Standby Mode X H H X X X X X X

(4)

L H L L H L X Even Nibble A

(4)

L H L H H L X Odd Nibble A L L L X H L Odd Nibble Even Nibble A

(4)

L L H X H L Odd Nibble X A

Nibble Access (x4) Nibble Access (x4) Byte Access (x8) Odd Nibble Access Write Inhibit X X X X L X X X X

Note:

(1)

D15-D8 in Figure 3

(2)

D7-D0 in Figure 3

(3)

Other addresses are “don’t care”

(4)

CS1 and CS0 at active state

This specification is subject to change without notice.

IN IN IN IN

(3)

14.9

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SST 28PC040

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

Table 7: Software Command Summary

Command Summary Required Setup Command Cycle Execute Command C y-

cle

Sector_Erase Byte_Program Erase_Verify

(10)

Reset Enable_Attribute Read_ID Software_Data_Protect

(10)

Software_Data_Unprotect

Cycle(s) Type

2 W X 22H W SA DDH N N 2 W X 11H W PA PD N N 2 W VA 1 W X FFH Y Y 1 W X 88H Y Y 3 W X 99H R (9) (9) Y Y

(10)

7 R (7) 7 R (8)

(1)

Addr

(2,

(5)

Data

(4)

Type

(1)

AAH R X D

Addr

(2,

Data

OUT

(4)

(6)

Y Y

SDP

(6)

Notes:

1. Type definition: W = Write, R = Read, X= don’t care

2. Addr (Address) definition: SA = Sector Address = A18 - A8, sector size = 512 nibbles; A7- A0 = X for

this command.

3. Addr (Address) definition: PA = Program Address = A18 - A0.

4. Data definition: PD = Program Data, H = number in hex.

5. Addr (Address) definition: VA = Verify Address = A18 - A0.

6. WP = Hardware Write Protect mode using WP pin, SDP = Software Data Protect mode using 7 Read

Cycle Sequence. a) Y = the operation can be executed with protection enabled b) N = the operation cannot be executed with protection enabled

7. Refer to Figure 13 for the 7 Read Cycle sequence for Software_Data_Protect.

8. Refer to Figure 12 for the 7 Read Cycle sequence for Software_Data_Unprotect.

9. Address 0000H retrieves the manufacturer’s code of BFH and address 0001H retrieves the device

code of 11H.

10. CS1 and CS0 at active state

Table 8: Memory Array Detail Memory Array Sector Select Byte Select Nibble Select

Common Memory A18 - A Attribute Memory A9 - A

14.10

This specification is subject to change without notice.

A7 - A A7 - A

0 0

HB HB

Page 11

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

Table 9: Nonconforming Sector Map

Attribute

Byte

Address

200 201 202 203

2FE 2FF

D7 D6 D5 D4 D3 D2 D1 D0

X X X X SNS SUM [3:0] X X X X SNS SUM [7:4] X X X X 16 14 12 10 X X X X 1E 1C 1A 18

. . . .

X X X X X X X X X X X X X X X X X X X X 7F6 7F4 7F2 7F0 X X X X 7FE 7FC 7FA 7F8

SST 28PC040

Attribute

Byte

Address

300 301 302 303

. . .

. 3FE 3FF

D7 D6 D5 D4 D3 D2 D1 D0

X X X X SNS SUM [3:0] X X X X SNS SUM [7:4] X X X X 17 15 13 11 X X X X 1F 1D 1B 19 X X X X X X X X X X X X X X X X X X X X 7F7 7F5 7F3 7F1 X X X X 7FF 7FD 7FB 7F9

Note: The Attribute memory bit is “0” when the corresponding Common memory sector is nonconform-

ing. The first 8 sectors of Common memory are always conforming.

Definitions:

1. The SNS sum is the sum of the number of nonconforming sectors and is calculated by summing the “0”s in the remaining bytes of the nonconforming sector map.

2. SNS Sum = Sum of Nonconforming Sector sum. The byte data from these addresses are not included in the sum.

a) [3:0] = The lower nibble of the SNS sum. b) [7:4] = The higher nibble of the SNS sum.

3. Only the lower nibble is used in the attribute memory to map the location of the nonconforming sector(s).

This specification is subject to change without notice.

14.11

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SST 28PC040

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute

Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias ........................................................................ -55°C to +125°C

Storage Temperature ............................................................................. -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential ........................................ -0.5V to VCC+ 0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential ................... -1.0V to VCC+ 1.0V

Voltage on A

Package Power Dissipation Capability (Ta = 25°C) ................................. 1.0W

Surface Mount Lead Soldering Temperature (3 Seconds) ......................240°C

Output Short Circuit Current

(1)

Note: Table 10: Operating Range Table 11: AC Conditions of Test

Range Ambient Temp V

Commercial

Pin to Ground Potential .................................................... -0.5V to 14.0V

(1)

................................................................. 100 mA

Outputs shorted for no more than one second. No more than one output shorted at a time.

0 °C to +70 °C 5V±10%

Input Rise/Fall Time...............10 ns

Output Load...........................1 TTL Gate and CL = 100

pF See Figures 16 and 17

Table 12: DC Operating Characteristics

Symbol Parameter Limits Units Test Conditions

Min Max

Power Supply Current CE# (L or H) = OE# =VIL, WE# =VIH,

all I/Os open

Read 25 mA Address input = VIL/V

= V

Max

Program and Erase 40 mA CE# (L or H) =WE# =VIL, OE# =V

I I V V V V V V V I

SB1

SB2

LI LO

IL IH IL2 IH2 OL OH H

CC =VCC

Standby VCC Current (TTL input)

Standby V

Current

(CMOS input) Input Leakage Current 1 Output Leakage Current 10 Input Low Voltage,TTL 0.8 V V Input High Voltage, TTL 2.0 V V Input Low Voltage, CMOS 0.2 V V Input High Voltage, CMOS V

CC-0.2

5 mA CE# =OE# =WE# = VIH, VCC=V

Input pins at VIL or V

CE# = OE# = WE# = V

µA

VCC=V V

µA µA

V V

OUT CC

CC CC CC

Output Low Voltage 0.4 V IOL= 3.2 mA, V Output High Voltage 2.4 V I Supervoltage for A

Supervoltage Current for A

11.6 12.4 V CE#=OE#=V

200

µA

CE#=OE#=V

Max.

Max, all Input pins at V

= GND to V

CC, VCC

=GND to V

= V

Max.

= VCC Max. = V

Max.

= VCC Max.

= 2.0 mA, V

WE#=V

IL,

WE#=V

IL,

CC, VCC

= V

at f=1/T

IH,

-0.3V,

= V

Max.

= V

Max.

Min.

, A9 = VH Max.

Min.

Max, all

or V

IL2

IH2

14.12

This specification is subject to change without notice.

Page 13

SST 28PC040

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

Table 13: Power-up Timings

Symbol Parameter Maximum Units

PU-READ

PU-WRITE

Table 14: Capacitance (Ta = 25 °°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

I/O

(1)

Power-up to Read Operation 10 ms Power-up to Write Operation 10 ms

I/O Pin Capacitance V Input Capacitance V

= 0V 12 pF

I/O

= 0v 6 pF

Note:

(1)

This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Table 15: Reliability Characteristics

Symbol Parameter Minimum

Units Test Method

Specification

END

(1)

ZAP_HBM

Endurance 100,000 Cycles MIL-STD-883, Method 1033 Data Retention 100 Years MIL-STD-883, Method 1008

(1)

ESD Susceptibility

1,000 Volts MIL-STD-883, Method 3015

Human Body Model

ZAP_MM

(1)

ESD Susceptibility

200 Volts JEDEC

Machine Model

(1)

LTH

Note:

(1)

This parameter is measured only for initial qualification and after a design or process change

Latch Up 100 mA JEDEC Standard 17

that could affect this parameter.

AC Characteristics Table 16: Read Cycle Timing Parameters

PCMCIA IEEE Industry 28PC040-150 28PC040-250 Symbol Symbol Symbol Parameter Min Max Min Max Units

tCR tAVAV T ta(A) tAVQV T ta(CE) tELQV T ta(OE) tGLQV T tdis(CE) tEHQZ T tdis(OE) tGHQZ T ten(CE) tELQX T ten(OE) tGLQX T tv(A) tAXQX T

RC AA CE OE CLZ OLZ CHZ OHZ OH

(1) (1)

(1)

Read Cycle time 150 250 ns Address Access Time 150 250 ns Chip Enable Access Time 150 250 ns Output Enable Access Time 70 100 ns CE# Low to Active Output 0 0 ns OE# Low to Active Output 0 0 ns CE# High to High-Z Output 40 40 ns OE# High to High-Z Output 40 40 ns Output Hold from Address

0 0 ns

Change

This specification is subject to change without notice.

14.13

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SST 28PC040

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

Table 17: Erase/Progarm Cycle Timing Parameters PCMCIA IEEE Industrial 28PC040-

150

Symbol Symbol Symbol Parameter Min Max Min Max Units

tCW tAVA T tw(WE) tWLWH T tsu(A) tAVWL T th(a) tWLAX T tsu(CE) tELWL T th(CE) tWHEX T tsu(OE-WE) tGHWL T th(OE-WE) tWGL T tw(CE) tWLEH T tsu(D-WEH) tDVWH T th(D) tWHDX T

tWHWL2 T

BP WP AS AH CS CH OES OEH CP DS DH SE RST

(1)

Byte Program Cycle Time 35 35 Write Pulse Width (WE#) 80 100 ns Address Setup Time 20 20 ns Address Hold Time 0 0 ns CE# Setup Time 0 0 ns CE# Hold Time 0 0 ns OE# High Setup Time 10 10 ns OE# High Hold Time 10 10 ns Write Pulse Width (CE#) 80 100 ns Data Setup Time 50 50 ns Data Hold Time 10 10 ns Sector Erase Cycle Time 2 2 ms Reset Command

4 4

Recovery Time T T T

EVD ERD ASE

Erase Verify Timing Delay .025 0.25

Erase Reset Timing Delay 4 4

Algorithmic Sector

0.04 2.56 0.04 2.56 ms

Erase Cycle Time

tEHEL T tWHWL1 T tRHRL T

CPH WPH HR

(1)

CE# High Pulse Width 50 50 ns

WE# High Pulse Width 50 50 ns

Hardware Reset

10 10

Pulse Width

tRHBL T

RBS

(1)

Hardware Reset High to

10 10

RDY/BSY# Active

(1)

PCP

Protect Chip Enable

10 10 ns

Pulse Width

(1)

PCH

Protect Chip Enable

10 10 ns

High Time

(1)

PAS

Protect Address

0 0 ns

Setup Time

(1)

PAH

Protect Address Hold

50 50 ns

Time

28PC040-

250

µs

µs µs

µs

Note:

(1)

This parameter is measured only for initial qualification and after the design or process change

that could affect this parameter.

14.14

This specification is subject to change without notice.

Page 15

SST 28PC040

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

CHIP # 0 CHIP # 1

DQ 0-3 DQ 4-7

Figure 3: Chip Pair Mapping (Nibble Access)

Table 18: Nibble Access Table

Byte Nibble Outputs CEL# CEH# HB

Even Even Nibble 0-3 L H L Even Odd Nibble 4-7 L H H

Odd Even Nibble 8-11 H L L Odd Odd Nibble 12-15 H L H

DQ 0-3 DQ 4-7

PAIR OUTPUT

DQ 0-3

DQ 4-7

DQ 8-11

DQ 12-15

Even Byte

}

Odd Byte

}

This specification is subject to change without notice.

14.15

Page 16

SST 28PC040

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

Figure 4: Read Cycle Timing Diagram

Figure 5: WE# Controlled Byte Program Timing Diagram

14.16

This specification is subject to change without notice.

Page 17

SST 28PC040

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

Figure 6: CE# Controlled Byte Program Timing Diagram

Figure 7: Reset Command Timing Diagram

This specification is subject to change without notice.

14.17

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SST 28PC040

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

Figure 8: Enable_Attribute Timing Diagram

Figure 9: Sector Erase Timing Diagram

14.18

This specification is subject to change without notice.

Page 19

SST 28PC040

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

Figure 10: Software Data Unprotect Timing Diagram

Figure 11: Software Data Protect Timing Diagram

This specification is subject to change without notice.

14.19

Page 20

RST

RDY/BSY#

SST 28PC040

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

VCC min

-READ, T

-WRITE

Figure 12: RST and RDY/BSY# waveforms - Power up to Read and Write

RST

RDY/BSY#

RBS

-READ, T

-WRITE

Figure 13: RST and RDY/BSY# waveforms - Hardware Reset

14.20

This specification is subject to change without notice.

Page 21

SST 28PC040

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

Figure 14: Data# Polling Timing Diagram

Figure 15: Toggle Bit Timing Diagram

This specification is subject to change without notice.

14.21

Page 22

SST 28PC040

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

2.4 INPUT

0.4

AC test inputs are driven at VOH (2.4 V

0.8

2.0 REFERENCE POINTS

) for a logic “1” and VOL (0.4 V

TTL

ment reference points for inputs and outputs are VIH (2.0 V times (10% ↔ 90%) are <10 ns.

Figure 16: AC Input/Output Reference Wav eform

TEST LOAD EXAMPLE

TO TESTER

2.0

0.8

TTL

) and V

OUTPUT

) for a logic “0”. Measure-

TTL

(0.8 V

). Inputs rise and fall

TTL

TO DUT

LOW

Figure 17: Test Load Example

14.22

This specification is subject to change without notice.

HIGH

Page 23

SST 28PC040

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

Figure 18: Byte Program Flowchart

This specification is subject to change without notice.

14.23

Page 24

SST 28PC040

Read byte

YesNoYes

Internal Timer

Data # Polling

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

Toggle Bit

Byte Program/

Sector Erase

Initiated

Wait T

Write

Completed

Byte Program/

Sector Erase

Initiated

Read same

byte

Does DQ

2,6

match ?

Byte Program

Initiated

Read DQ

Is DQ

3,7

true data?

Write

Completed

Write

Completed

Figure 19: Write Wait Options

14.24

This specification is subject to change without notice.

Page 25

SST 28PC040

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

Figure 20: Sector_Erase Flowchart

This specification is subject to change without notice.

14.25

Page 26

SST 28PC040

5.0V-only 4 Megabit

PCMCIA Interface EEPROM

Product Ordering Information

Device Speed Suffix1 Suffix2 Suffix3

SST28PC040 - XXX - XX - XX XXXX

Card Decode

S00A = CS1 low active

CS0 low active

S01B = CS1 low active

CS0 high active

S10C = CS1 high active

CS0 low active

S11D = CS1 high active

CS0 high active

Valid combinations

SST28PC040-250-5C-WI-S00A SST28PC040-250-5C-WI-S01B SST28PC040-150-5C-WI-S00A SST28PC040-150-5C-WI-S01B

SST28PC040-250-5C-WI-S10C SST28PC040-250-5C-WI-S11D SST28PC040-150-5C-WI-S10C SST28PC040-150-5C-WI-S11D

Package Modifier

I = 40 leads

Package Type

W = TSOP (die up)

Operating Temperature

C= Commercial = 0° to 70°C

Minimum Endurance

5 = 100,000 cycles

Read Access Speed

250 = 250 ns 150 = 150 ns

Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine avai lability of new combinations.

14.26

This specification is subject to change without notice.

Datasheet SST28PC040 Datasheet (Silicon Storage Technology)

Specifications and Main Features

Frequently Asked Questions

User Manual