Page 1
FEATURES:
16 Mbit SPI Serial Flash
SST25VF016B
SST25VF016B16Mb Serial Peripheral Interface (SPI) flash memory
Data Sheet
• Single Voltage Read and Write Operations
– 2.7-3.6V
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
–50 MHz
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Read Current: 10 mA (typical)
– Standby Current: 5 µA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
– Uniform 64 KByte overlay blocks
• Fast Erase and Byte-Program:
– Chip-Erase Time: 35 ms (typical)
– Sector-/Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 7 µs (typical)
• Auto Address Increment (AAI) Programming
– Decrease total chip programming time over
Byte-Program operations
• End-of-Write Detection
– Software polling the BUSY bit in Status Register
– Busy Status readout on SO pin in AAI Mode
• Hold Pin (HOLD#)
– Suspends a serial sequence to the memory
without deselecting the device
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the
status register
• Software Write Protection
– Write protection through Block-Protection bits in
status register
• Temperature Range
– Commercial: 0°C to +70°C
– Industrial: -40°C to +85°C
• Packages Available
– 8-lead SOIC (200 mils)
– 8-contact WSON (6mm x 5mm)
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
SST’s 25 series Serial Flash family features a four-wire,
SPI-compatible interface that allows for a low pin-count
package which occupies less board space and ultimately
lowers total system costs. The SST25VF016B devices are
enhanced with improved operating frequency and even
lower power consumption than the original SST25VFxxxA
devices. SST25VF016B SPI serial flash memories are
manufactured with SST’s proprietary, high-performance
CMOS SuperFlash technology. The split-gate cell design
and thick-oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches.
The SST25VF016B devices significantly improve performance and reliability, while lowering power consumption.
The devices write (Program or Erase) with a single power
supply of 2.7-3.6V for SST25VF016B. The total energy
consumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and
has a shorter erase time, the total energy consumed during
any Erase or Program operation is less than alternative
flash memory technologies.
The SST25VF016B device is offered in both 8-lead SOIC
(200 mils) and 8-contact WSON (6mm x 5mm) packages.
See Figure 1 for pin assignments.
©2006 Silicon Storage Technology, Inc.
S71271-02-000 1/06
1
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
Page 2
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
Address
Buffers
Latches
and
X - Decoder
16 Mbit SPI Serial Flash
SST25VF016B
SuperFlash
Memory
Y - Decoder
Control Logic
CE#
I/O Buffers
and
Data Latches
Serial Interface
1271 B1.0
SCK SI SO WP# HOLD#
©2006 Silicon Storage Technology, Inc. S71271-02-000 1/06
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16 Mbit SPI Serial Flash
SST25VF016B
PIN DESCRIPTION
Data Sheet
CE#
SO
WP#
V
SS
1
2
Top View
3
4
1271 08-soic S2A P1.0
8
V
DD
7
HOLD#
6
SCK
5
SI
CE#
SO
WP#
V
SS
1
2
Top View
3
4
1271 08-wson QA P2.0
8
7
6
5
V
DD
HOLD#
SCK
SI
8-LEAD SOIC 8-CONTACT WSON
FIGURE 1: PIN ASSIGNMENTS
TABLE 1: PIN DESCRIPTION
Symbol Pin Name Functions
SCK Serial Clock To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input,
while output data is shifted out on the falling edge of the clock input.
SI Serial Data Input To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO Serial Data Output To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Outputs Flash busy status during AAI Programming when reconfigured as RY/BY# pin.
See “Hardware End-of-Write Detection” on page 12 for details.
CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for the
duration of any command sequence.
WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting the
device.
V
DD
V
SS
Power Supply To provide power supply voltage: 2.7-3.6V for SST25VF016B
Ground
T1.0 1271
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Data Sheet
16 Mbit SPI Serial Flash
SST25VF016B
MEMORY ORGANIZATION
The SST25VF016B SuperFlash memory array is organized in uniform 4 KByte erasable sectors with 32 KByte
overlay blocks and 64 KByte overlay erasable blocks.
DEVICE OPERATION
The SST25VF016B is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI bus
consist of four control lines; Chip Enable (CE#) is used to
CE#
MODE 3
SCK
SI
SO
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
HIGH IMPEDANCE
select the device, and data is accessed through the Serial
Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK).
The SST25VF016B supports both Mode 0 (0,0) and Mode
3 (1,1) of SPI bus operations. The difference between the
two modes, as shown in Figure 2, is the state of the SCK
signal when the bus master is in Stand-by mode and no
data is being transferred. The SCK signal is low for Mode 0
and SCK signal is high for Mode 3. For both modes, the
Serial Data In (SI) is sampled at the rising edge of the SCK
clock signal and the Serial Data Output (SO) is driven after
the falling edge of the SCK clock signal.
MODE 3
MODE 0MODE 0
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1271 SPIprot.0
FIGURE 2: SPI P
ROTOCOL
©2006 Silicon Storage Technology, Inc. S71271-02-000 1/06
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16 Mbit SPI Serial Flash
SST25VF016B
Hold Operation
The HOLD# pin is used to pause a serial sequence underway with the SPI flash memory without resetting the clocking sequence. To activate the HOLD# mode, CE# must be
in active low state. The HOLD# mode begins when the
SCK active low state coincides with the falling edge of the
HOLD# signal. The HOLD mode ends when the HOLD#
signal’s rising edge coincides with the SCK active low state.
If the falling edge of the HOLD# signal does not coincide
with the SCK active low state, then the device enters Hold
mode when the SCK next reaches the active low state.
Similarly, if the rising edge of the HOLD# signal does not
SCK
Data Sheet
coincide with the SCK active low state, then the device
exits in Hold mode when the SCK next reaches the active
low state. See Figure 3 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in highimpedance state while SI and SCK can be V
IL
or V
IH.
If CE# is driven active high during a Hold condition, it resets
the internal logic of the device. As long as HOLD# signal is
low, the memory remains in the Hold condition. To resume
communication with the device, HOLD# must be driven
active high, and CE# must be driven active low. See Figure
23 for Hold timing.
HOLD#
Active
Hold
FIGURE 3: HOLD CONDITION WAVEFORM
Write Protection
SST25VF016B provides software Write protection. The
Write Protect pin (WP#) enables or disables the lock-down
function of the status register. The Block-Protection bits
(BP3, BP2, BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status
register. See Table 4 for the Block-Protection description.
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register. When WP#
is driven low, the execution of the Write-Status-Register
(WRSR) instruction is determined by the value of the BPL
bit (see Table 2). When WP# is high, the lock-down function of the BPL bit is disabled.
Active Hold Active
1271 HoldCond.0
TABLE 2: CONDITIONS TO EXECUTE WRITE-STATUS-
R
EGISTER (WRSR) INSTRUCTION
WP# BPL Execute WRSR Instruction
L 1 Not Allowed
L0Allowed
HXAllowed
T2.0 1271
©2006 Silicon Storage Technology, Inc. S71271-02-000 1/06
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Data Sheet
Status Register
The software status register provides status on whether the
flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of
the Memory Write protection. During an internal Erase or
16 Mbit SPI Serial Flash
SST25VF016B
Program operation, the status register may be read only to
determine the completion of an operation in progress.
Table 3 describes the function of each bit in the software
status register.
TABLE 3: S
Bit Name Function
0 BUSY 1 = Internal Write operation is in progress
1 WEL 1 = Device is memory Write enabled
2 BP0 Indicate current level of block write protection (See Table 4) 1 R/W
3 BP1 Indicate current level of block write protection (See Table 4) 1 R/W
4 BP2 Indicate current level of block write protection (See Table 4) 1 R/W
5 BP3 Indicate current level of block write protection (See Table 4) 0 R/W
6 AAI Auto Address Increment Programming status
7 BPL 1 = BP3, BP2, BP1, BP0 are read-only bits
Busy
The Busy bit determines whether there is an internal Erase
or Program operation in progress. A “1” for the Busy bit indicates the device is busy with an operation in progress. A “0”
indicates the device is ready for the next valid operation.
OFTWARE STATUS REGISTER
Default at
Power-up Read/Write
0R
0 = No internal Write operation is in progress
0R
0 = Device is not memory Write enabled
0R
1 = AAI programming mode
0 = Byte-Program mode
0R/W
0 = BP3, BP2, BP1, BP0 are read/writable
Auto Address Increment (AAI)
The Auto Address Increment Programming-Status bit provides status on whether the device is in AAI programming
mode or Byte-Program mode. The default at power up is
Byte-Program mode.
T3.0 1271
Write Enable Latch (WEL)
The Write-Enable-Latch bit indicates the status of the internal memor y Write Enable Latch. If the Write-Enable-Latch
bit is set to “1”, it indicates the device is Write enabled. If the
bit is set to “0” (reset), it indicates the device is not Write
enabled and does not accept any memory Write (Program/
Erase) commands. The Write-Enable-Latch bit is automatically reset under the following conditions:
• Power-up
• Write-Disable (WRDI) instruction completion
• Byte-Program instruction completion
• Auto Address Increment (AAI) programming is
completed or reached its highest unprotected
memory address
• Sector-Erase instruction completion
• Block-Erase instruction completion
• Chip-Erase instruction completion
• Write-Status-Register instructions
©2006 Silicon Storage Technology, Inc. S71271-02-000 1/06
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16 Mbit SPI Serial Flash
SST25VF016B
Data Sheet
Block Protection (BP3,BP2, BP1, BP0)
The Block-Protection (BP3, BP2, BP1, BP0) bits define the
size of the memory area, as defined in Table 4, to be software protected against any memory Write (Program or
Erase) operation. The Write-Status-Register (WRSR)
instruction is used to program the BP3, BP2, BP1 and BP0
bits as long as WP# is high or the Block-Protect-Lock
Block Protection Lock-Down (BPL)
WP# pin driven low (V
), enables the Block-Protection-
IL
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP3, BP2, BP1, and BP0 bits.
When the WP# pin is driven high (V
), the BPL bit has no
IH
effect and its value is “Don’t Care”. After power-up, the BPL
bit is reset to 0.
(BPL) bit is 0. Chip-Erase can only be executed if BlockProtection bits are all 0. After power-up, BP3, BP2, BP1
and BP0 are set to 1.
TABLE 4: S
Protection Level
None X 0 0 0 None
Upper 1/32 X 0 0 1 1F0000H-1FFFFFH
Upper 1/16 X 0 1 0 1E0000H-1FFFFFH
Upper 1/8 X 0 1 1 1C0000H-1FFFFFH
Upper 1/4 X 1 0 0 180000H-1FFFFFH
Upper 1/2 X 1 0 1 100000H-1FFFFFH
All Blocks X 1 1 0 000000H-1FFFFFH
All Blocks X 1 1 1 000000H-1FFFFFH
1. X = Don’t Care (RESERVED) default is “0
2. Default at power-up for BP2, BP1, and BP0 is ‘111’. (All Blocks Protected)
OFTWARE STATUS REGISTER BLOCK PROTECTION FOR SST25VF016B
Status Register Bit
BP3 BP2 BP1 BP0 16 Mbit
2
1
Protected Memory Address
T4.0 1271
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Data Sheet
Instructions
Instructions are used to read, write (Erase and Program),
and configure the SST25VF016B. The instruction bus
cycles are 8 bits each for commands (Op Code), data, and
addresses. Prior to executing any Byte-Program, Auto
Address Increment (AAI) programming, Sector-Erase,
Block-Erase, Write-Status-Register, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first. The complete list of instructions is provided in
Table 5. All instructions are synchronized off a high to low
transition of CE#. Inputs will be accepted on the rising edge
16 Mbit SPI Serial Flash
SST25VF016B
of SCK starting with the most significant bit. CE# must be
driven low before an instruction is entered and must be
driven high after the last bit of the instruction has been
shifted in (except for Read, Read-ID, and Read-Status-
Register instructions). Any low to high transition on CE#,
before receiving the last bit of an instruction bus cycle, will
terminate the instruction in progress and return the device
to standby mode. Instruction commands (Op Code),
addresses, and data are all input from the most significant
bit (MSB) first.
TABLE 5: D
Instruction Description Op Code Cycle
EVICE OPERATION INSTRUCTIONS
1
Address
Cycle(s)
Dummy
2
Cycle(s)
Data
Cycle(s)
Maximum
Frequency
Read Read Memory at 25 MHz 0000 0011b (03H) 3 0 1 to ∞ 25 MHz
High-Speed Read Read Memory at 50 MHz 0000 1011b (0BH) 3 1 1 to ∞ 50 MHz
4 KByte Sector-Erase
3
Erase 4 KByte of
0010 0000b (20H) 3 0 0 50 MHz
memory array
32 KByte Block-Erase
4
Erase 32 KByte block
0101 0010b (52H) 3 0 0 50 MHz
of memory array
64 KByte Block-Erase
5
Erase 64 KByte block
1101 1000b (D8H) 3 0 0 50 MHz
of memory array
Chip-Erase Erase Full Memory Array 0110 0000b (60H) or
00050 MHz
1100 0111b (C7H)
Byte-Program To Program One Data Byte 0000 0010b (02H) 3 0 1 50 MHz
AAI-Word-Program
6
Auto Address Increment
1010 1101b (ADH) 3 0 2 to ∞ 50 MHz
Programming
7
RDSR
Read-Status-Register 0000 0101b (05H) 0 0 1 to ∞ 50 MHz
EWSR Enable-Write-Status-Register 0101b 0000b (50H) 0 0 0 50 MHz
WRSR Write-Status-Register 0000 0001b (01H) 0 0 1 50 MHz
WREN Write-Enable 0000 0110b (06H) 0 0 0 50 MHz
WRDI Write-Disable 0000 0100b (04H) 0 0 0 50 MHz
8
RDID
Read-ID 1001 0000b (90H) or
301 to ∞ 50 MHz
1010 1011b (ABH)
JEDEC-ID JEDEC ID read 1001 1111b (9FH) 0 0 3 to ∞ 50 MHz
EBSY Enable SO to output RY/BY#
0111 0000b (70H) 0 0 0 50 MHz
status during AAI programming
DBSY Disable SO to output RY/BY#
1000 0000b (80H) 0 0 0 50 MHz
status during AAI programming
1. One bus cycle is eight clock periods.
2. Address bits above the most significant bit of each density can be VIL or VIH.
3. 4KByte Sector Erase addresses: use AMS-A
4. 32KByte Block Erase addresses: use AMS-A
5. 64KByte Block Erase addresses: use AMS-A
6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data to be
programmed. Data Byte 0 will be programmed into the initial address [A
initial address [A
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
8. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s ID and
device ID output stream is continuous until terminated by a low-to-high transition on CE#.
23-A1
] with A0=1.
remaining addresses are don’t care but must be set either at VIL or V
12,
remaining addresses are don’t care but must be set either at VIL or V
15,
remaining addresses are don’t care but must be set either at VIL or V
16,
] with A0=0, Data Byte 1 will be programmed into the
23-A1
IH.
IH.
IH.
T5.0 1271
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16 Mbit SPI Serial Flash
SST25VF016B
Read (25 MHz)
The Read instruction, 03H, supports up to 25 MHz Read.
The device outputs the data starting from the specified
address location. The data output stream is continuous
through all addresses until terminated by a low to high transition on CE#. The internal address pointer will automatically increment until the highest memory address is
reached. Once the highest memory address is reached,
the address pointer will automatically increment to the
CE#
Data Sheet
beginning (wrap-around) of the address space. Once the
data from address location 1FFFFFH has been read, the
next output will be from address location 000000H.
The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A
]. CE# must
23-A0
remain active low for the duration of the Read cycle. See
Figure 4 for the Read sequence.
SCK
SO
MODE 3
MODE 0
SI
012345678
03
MSB
HIGH IMPEDANCE
FIGURE 4: READ SEQUENCE
ADD.
MSB
15 16
ADD. ADD.
23
31
24
MSB
39
OUT
40
N+2 N+3 N+4N N+1
D
OUT
D
OUTDOUT
32
D
7047 48 55 56 63 64
D
OUT
1271 ReadSeq.0
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Data Sheet
High-Speed-Read (50 MHz)
The High-Speed-Read instruction supporting up to 50 MHz
Read is initiated by executing an 8-bit command, 0BH, followed by address bits [A
] and a dummy byte. CE#
23-A0
must remain active low for the duration of the High-SpeedRead cycle. See Figure 5 for the High-Speed-Read
sequence.
Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the specified address
location. The data output stream is continuous through all
CE#
16 Mbit SPI Serial Flash
SST25VF016B
addresses until terminated by a low to high transition on
CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once
the highest memory address is reached, the address
pointer will automatically increment to the beginning (wraparound) of the address space. Once the data from address
location 1FFFFFH has been read, the next output will be
from address location 000000H.
SCK
SO
MODE 3
MODE 0
SI
012345678
ADD.
MSB
HIGH IMPEDANCE
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (VIL or VIH)
MSB
FIGURE 5: HIGH-SPEED-READ SEQUENCE
15 16 23 24 31 32 39 40
ADD. ADD.0B
X
MSB
47 48 55 56 63 64
D
N
OUT
D
N+1
OUT
71 72
N+2 N+3 N+4
D
OUTDOUT
D
1271 HSRdSeq.0
80
OUT
©2006 Silicon Storage Technology, Inc. S71271-02-000 1/06
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16 Mbit SPI Serial Flash
SST25VF016B
Byte-Program
The Byte-Program instruction programs the bits in the
selected byte to the desired data. The selected byte must
be in the erased state (FFH) when initiating a Program
operation. A Byte-Program instruction applied to a protected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN)
instruction must be executed. CE# must remain active low
for the duration of the Byte-Program instruction. The Byte-
CE#
Data Sheet
Program instruction is initiated by executing an 8-bit command, 02H, followed by address bits [A
]. Following the
23-A0
address, the data is input in order from MSB (bit 7) to LSB
(bit 0). CE# must be driven high before the instruction is
executed. The user may poll the Busy bit in the software
status register or wait T
for the completion of the internal
BP
self-timed Byte-Program operation. See Figure 6 for the
Byte-Program sequence.
SCK
SO
MODE 3
MODE 0
SI
012345678
MSB
FIGURE 6: BYTE-PROGRAM SEQUENCE
02
15 16
ADD.
HIGH IMPEDANCE
ADD. ADD. D
23
31
24
39
32
IN
MSBMSB
LSB
1271 ByteProg.0
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Data Sheet
16 Mbit SPI Serial Flash
SST25VF016B
Auto Address Increment (AAI) Word-Program
The AAI program instruction allows multiple bytes of data to
be programmed without re-issuing the next sequential
address location. This feature decreases total programming time when multiple bytes or entire memory array is to
be programmed. An AAI Word program instruction pointing
to a protected memory area will be ignored. The selected
address range must be in the erased state (FFH) when initiating an AAI Word Program operation. While within AAI
Word Programming sequence, the only valid instructions
are AAI Word (ADH), RDSR (05H), or WRDI (04H). Users
have three options to determine the completion of each
AAI Word program cycle: hardware detection by reading
the Serial Output, software detection by polling the BUSY
bit in the software status register or wait T
Refer to End-
BP.
Of-Write Detection section for details.
Prior to any write operation, the Write-Enable (WREN)
instruction must be executed. The AAI Word Program
instruction is initiated by executing an 8-bit command,
ADH, followed by address bits [A
]. Following the
23-A0
addresses, two bytes of data is input sequentially, each one
from MSB (Bit 7) to LSB (Bit 0). The first byte of data (D0)
will be programmed into the initial address [A
A
=0, the second byte of Data (D1) will be programmed
0
into the initial address [A
] with A0=1. CE# must be
23-A1
23-A1
] with
driven high before the AAI Word Program instruction is executed. The user must check the BUSY status before entering the next valid command. Once the device indicates it is
no longer busy, data for the next two sequential addresses
may be programmed and so on. When the last desired
byte had been entered, check the busy status using the
hardware method or the RDSR instruction and execute the
Write-Disable (WRDI) instruction, 04H, to terminate AAI.
User must check busy status after WRDI to determine if the
device is ready for any command. See Figures 9 and 10 for
AAI Word programming sequence.
There is no wrap mode during AAI programming; once the
highest unprotected memory address is reached, the
device will exit AAI operation and reset the Write-EnableLatch bit (WEL = 0) and the AAI bit (AAI=0).
End-of-Write Detection
There are three methods to determine completion of a program cycle during AAI Word programming: hardware
detection by reading the Serial Output, software detection
by polling the BUSY bit in the Software Status Register or
wait T
The hardware end-of-write detection method is
BP.
described in the section below.
Hardware End-of-Write Detection
The hardware end-of-write detection method eliminates the
overhead of polling the Busy bit in the Software Status
Register during an AAI Word program operation. The 8-bit
command, 70H, configures the Serial Output (SO) pin to
indicate Flash Busy status during AAI Word programming.
(see Figure 7) The 8-bit command, 70H, must be executed
prior to executing an AAI Word-Program instruction. Once
an internal programming operation begins, asserting CE#
will immediately drive the status of the internal flash status
on the SO pin. A “0” indicates the device is busy and a “1”
indicates the device is ready for the next instruction. Deasserting CE# will return the SO pin to tri-state.
The 8-bit command, 80H, disables the Serial Output (SO)
pin to output busy status during AAI-Word-program operation and return SO pin to output Software Status Register
data during AAI Word programming. (see Figure 8)
CE#
MODE 3
MODE 0
SCK
SI
SO
FIGURE 7: E
CE#
MODE 3
MODE 0
SCK
SI
SO
DURING AAI PROGRAMMING
01234567
70
MSB
HIGH IMPEDANCE
1271 EnableSO.0
NABLE SO AS HARDWARE RY/BY#
01234567
80
MSB
HIGH IMPEDANCE
1271 DisableSO.0
FIGURE 8: DISABLE SO AS HARDWARE RY/BY#
DURING AAI PROGRAMMING
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16 Mbit SPI Serial Flash
SST25VF016B
CE#
078 32 474815 16 23 24 31 04039 7 8 15 16 23 24 7 8 15 16 23 24 70 157800
MODE 3
MODE 0
SCK
Data Sheet
D
n-1Dn
Last 2
Data Bytes
1
command
SO
SI
2
AAAAD D0 AD
Load AAI command, Address, 2 bytes data
Note: 1. Valid commands during AAI programming: AAI command or WRDI command
2. User must configure the SO pin to output Flash Busy status during AAI programming
D1 D2 D3 AD
Check for Flash Busy Status to load next valid
FIGURE 9: AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH
HARDWARE END-OF-WRITE DETECTION
Wait T
or poll Software Status
BP
register to load next valid
1
command
WRDI
WDRI to exit
AAI Mode
RDSR
Wait T
Software Status register
to load any command
1271 AAI.HW.0
BP
D
or poll
OUT
CE#
078 32 474815 16 23 24 31 04039 7 8 15 16 23 24 7 8 15 16 23 24 70 157800
MODE 3
MODE 0
SCK
SI
SO
AAAAD D0 AD
Load AAI command, Address, 2 bytes data
Note: 1. Valid commands during AAI programming: AAI command or WRDI command
D1 D2 D3 AD
D
n-1Dn
Last 2
Data Bytes
WRDI
WDRI to exit
AAI Mode
RDSR
Wait T
Software Status register
to load any command
1271 AAI.SW.0
BP
D
or poll
OUT
FIGURE 10: AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH
S
OFTWARE END-OF-WRITE DETECTION
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13
Page 14
Data Sheet
4-KByte Sector-Erase
The Sector-Erase instruction clears all bits in the selected 4
KByte sector to FFH. A Sector-Erase instruction applied to
a protected memory area will be ignored. Prior to any Write
operation, the Write-Enable (WREN) instruction must be
executed. CE# must remain active low for the duration of
any command sequence. The Sector-Erase instruction is
initiated by executing an 8-bit command, 20H, followed by
address bits [A
]. Address bits [AMS-A12] (AMS=Most
23-A0
CE#
16 Mbit SPI Serial Flash
SST25VF016B
Significant address) are used to determine the sector
address (SA
CE# must be driven high before the instruction is executed.
The user may poll the Busy bit in the software status register or wait T
Sector-Erase cycle. See Figure 11 for the Sector-Erase
sequence.
), remaining address bits can be VIL or V
X
for the completion of the internal self-timed
SE
IH.
MODE 3
MODE 0
SCK
SI
SO
FIGURE 11: SECTOR-ERASE SEQUENCE
012345678
20
HIGH IMPEDANCE
ADD.
MSBMSB
15 16
ADD. ADD.
23
24
1271 SecErase.0
31
©2006 Silicon Storage Technology, Inc. S71271-02-000 1/06
14
Page 15
16 Mbit SPI Serial Flash
SST25VF016B
32-KByte and 64-KByte Block-Erase
The 32-KByte Block-Erase instruction clears all bits in the
selected 32 KByte block to FFH. A Block-Erase instruction
applied to a protected memory area will be ignored. The
64-KByte Block-Erase instruction clears all bits in the
selected 64 KByte block to FFH. A Block-Erase instruction
applied to a protected memory area will be ignored. Prior to
any Write operation, the Write-Enable (WREN) instruction
must be executed. CE# must remain active low for the
duration of any command sequence. The 32-Kbyte BlockErase instruction is initiated by executing an 8-bit command, 52H, followed by address bits [A
[A
] (AMS= Most Significant Address) are used to
MS-A15
CE#
]. Address bits
23-A0
Data Sheet
determine block address (BA
be V
or V
IL
CE# must be driven high before the instruction
IH.
), remaining address bits can
X
is executed. The 64-Kbyte Block-Erase instruction is initiated by executing an 8-bit command D8H, followed by
address bits [A
determine block address (BA
be V
or V
IL
CE# must be driven high before the instruction
IH.
]. Address bits [AMS-A15] are used to
23-A0
), remaining address bits can
X
is executed. The user may poll the Busy bit in the software
status register or wait T
for the completion of the internal
BE
self-timed 32-KByte Block-Erase or 64-KByte Block-Erase
cycles. See Figures 12 and 13 for the 32-KByte BlockErase and 64-KByte Block-Erase sequences.
FIGURE 12: 32-KB
MODE 3
MODE 0
SCK
SI
SO
YTE BLOCK-ERASE SEQUENCE
CE#
MODE 3
MODE 0
SCK
SI
SO
012345678
52
MSB MSB
012345678
D8
MSB MSB
15 16
ADDR
HIGH IMPEDANCE
15 16
ADDR
HIGH IMPEDANCE
23
24
ADDR ADDR
1271 32KBklEr.0
23
24
ADDR ADDR
1271 63KBlkEr.0
31
31
FIGURE 13: 64-KBYTE BLOCK-ERASE SEQUENCE
©2006 Silicon Storage Technology, Inc. S71271-02-000 1/06
15
Page 16
Data Sheet
Chip-Erase
The Chip-Erase instruction clears all bits in the device to
FFH. A Chip-Erase instruction will be ignored if any of the
memory area is protected. Prior to any Write operation, the
Write-Enable (WREN) instruction must be executed. CE#
must remain active low for the duration of the Chip-Erase
instruction sequence. The Chip-Erase instruction is initiated
CE#
16 Mbit SPI Serial Flash
SST25VF016B
by executing an 8-bit command, 60H or C7H. CE# must be
driven high before the instruction is executed. The user may
poll the Busy bit in the software status register or wait T
for the completion of the internal self-timed Chip-Erase
cycle. See Figure 14 for the Chip-Erase sequence.
CE
MODE 3
MODE 0
SCK
SI
SO
HIGH IMPEDANCE
FIGURE 14: CHIP-ERASE SEQUENCE
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows reading of the status register. The status register may be read at
any time even during a Write (Program/Erase) operation.
When a Write operation is in progress, the Busy bit may be
checked before sending any new commands to assure that
the new commands are properly received by the device.
01234567
60 or C7
MSB
1271 ChEr.0
CE# must be driven low before the RDSR instruction is
entered and remain low until the status data is read. ReadStatus-Register is continuous with ongoing clock cycles
until it is terminated by a low to high transition of the CE#.
See Figure 15 for the RDSR instruction sequence.
CE#
MODE 3
MODE 0
SCK
SI
SO
FIGURE 15: R
©2006 Silicon Storage Technology, Inc. S71271-02-000 1/06
EAD-STATUS-REGISTER (RDSR) SEQUENCE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
MSB
HIGH IMPEDANCE
05
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
Status
Register Out
1271 RDSRseq.0
16
Page 17
16 Mbit SPI Serial Flash
SST25VF016B
Data Sheet
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the WriteEnable-Latch bit in the Status Register to 1 allowing Write
operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. The
WREN instruction may also be used to allow execution of
CE#
MODE 3
MODE 0
SCK
SI
SO
HIGH IMPEDANCE
FIGURE 16: WRITE ENABLE (WREN) SEQUENCE
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the WriteEnable-Latch bit and AAI bit to 0 disabling any new Write
operations from occurring. The WRDI instruction will not
the Write-Status-Register (WRSR) instruction; however,
the Write-Enable-Latch bit in the Status Register will be
cleared upon the rising edge CE# of the WRSR instruction.
CE# must be driven high before the WREN instruction is
executed.
01234567
06
MSB
1271 WREN.0
terminate any programming operation in progress. Any program operation in progress may continue up to T
executing the WRDI instruction. CE# must be driven high
before the WRDI instruction is executed.
BP
after
CE#
SCK
SO
MODE 3
MODE 0
SI
01234567
04
MSB
HIGH IMPEDANCE
1271 WRDI.0
FIGURE 17: WRITE DISABLE (WRDI) SEQUENCE
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction
arms the Write-Status-Register (WRSR) instruction and
opens the status register for alteration. The Write-StatusRegister instruction must be executed immediately after the
execution of the Enable-Write-Status-Register instruction.
This two-step instruction sequence of the EWSR instruc-
©2006 Silicon Storage Technology, Inc. S71271-02-000 1/06
tion followed by the WRSR instruction works like SDP (software data protection) command structure which prevents
any accidental alteration of the status register values. CE#
must be driven low before the EWSR instruction is entered
and must be driven high before the EWSR instruction is
executed.
17
Page 18
Data Sheet
16 Mbit SPI Serial Flash
SST25VF016B
Write-Status-Register (WRSR)
The Write-Status-Register instruction writes new values to
the BP3, BP2, BP1, BP0, and BPL bits of the status register. CE# must be driven low before the command
sequence of the WRSR instruction is entered and driven
high before the WRSR instruction is executed. See Figure
18 for EWSR or WREN and WRSR instruction sequences.
Executing the Write-Status-Register instruction will be
ignored when WP# is low and BPL bit is set to “1”. When
the WP# is low, the BPL bit can only be set from “0” to “1” to
lock-down the status register, but cannot be reset from “1”
CE#
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
50 or 06
MODE 3
MODE 0
HIGH IMPEDANCE
SCK
SI
SO
MODE 3
MODE 0
to “0”. When WP# is high, the lock-down function of the
BPL bit is disabled and the BPL, BP0, and BP1 and BP2
bits in the status register can all be changed. As long as
BPL bit is set to 0 or WP# pin is driven high (V
) prior to the
IH
low-to-high transition of the CE# pin at the end of the
WRSR instruction, the bits in the status register can all be
altered by the WRSR instruction. In this case, a single
WRSR instruction can set the BPL bit to “1” to lock down
the status register as well as altering the BP0, BP1, and
BP2 bits at the same time. See Table 2 for a summary
description of WP# and BPL functions.
STATUS
REGISTER IN
01
76543210
MSBMSBMSB
1271 EWSR.0
FIGURE 18: E
NABLE-WRITE-STATUS-REGISTER (EWSR) OR
WRITE-ENABLE (WREN) AND WRITE-STATUS-REGISTER (WRSR) SEQUENCE
©2006 Silicon Storage Technology, Inc. S71271-02-000 1/06
18
Page 19
16 Mbit SPI Serial Flash
SST25VF016B
JEDEC Read-ID
The JEDEC Read-ID instruction identifies the device as
SST25VF016B and the manufacturer as SST. The device
information can be read from executing the 8-bit command,
9FH. Following the JEDEC Read-ID instruction, the 8-bit
manufacturer’s ID, BFH, is output from the device. After
that, a 16-bit device ID is shifted out on the SO pin. Byte 1,
BFH, identifies the manufacturer as SST. Byte 2, 25H, identifies the memory type as SPI Serial Flash. Byte 3, 41H,
identifies the device as SST25VF016B. The instruction
CE#
Data Sheet
sequence is shown in Figure 19. The JEDEC Read ID
instruction is terminated by a low to high transition on CE#
at any time during data output. If no other command is
issued after executing the JEDEC Read-ID instruction,
issue a 00H (NOP) command before going into Standby
Mode (CE#=V
).
IH
MODE 3
MODE 0
SCK
SI
HIGH IMPEDANCE
SO
FIGURE 19: JEDEC R
012345678
9F
EAD-ID SEQUENCE
TABLE 6: JEDEC READ-ID DATA
Manufacturer’s ID Device ID
Memory Type Memory Capacity
Byte1 Byte 2 Byte 3
BFH 25H 41H
9 10111213 1718 32 34
BF
T6.0 1271
15 1614 28 29 30 31
MSBMSB
19 20 21 22 23 3324 25 26 27
25 41
1271 JEDECID.1
©2006 Silicon Storage Technology, Inc. S71271-02-000 1/06
19
Page 20
Data Sheet
Read-ID (RDID)
The Read-ID instruction (RDID) identifies the devices as
SST25VF016B and manufacturer as SST. This command
is backward compatible to all SST25xFxxxA devices and
should be used as default device identification when multiple versions of SPI Serial Flash devices are used in a
design. The device information can be read from executing
an 8-bit command, 90H or ABH, followed by address bits
[A
]. Following the Read-ID instruction, the manufac-
23-A0
CE#
16 Mbit SPI Serial Flash
SST25VF016B
turer’s ID is located in address 00000H and the device ID is
located in address 00001H. Once the device is in Read-ID
mode, the manufacturer’s and device ID output data toggles between address 00000H and 00001H until terminated by a low to high transition on CE#.
Refer to Tables 6 and 7 for device identification data.
MODE 3
MODE 0
SCK
SI
SO
Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#.
Device ID = 41H for SST25VF016B
1. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two.
FIGURE 20: R
012345678
90 or AB
MSB MSB
HIGH IMPEDANCE
EAD-ID SEQUENCE
15 16
00
TABLE 7: PRODUCT IDENTIFICATION
Address Data
Manufacturer’s ID 00000H BFH
Device ID
SST25VF016B 00001H 41H
23
00 ADD
T7.0 1271
31
24
1
MSB
39
32
BF
47 48 55 56 63
40
Device ID
BF
Device ID
HIGH
IMPEDANCE
1271 RdID.0
©2006 Silicon Storage Technology, Inc. S71271-02-000 1/06
20
Page 21
16 Mbit SPI Serial Flash
SST25VF016B
Data Sheet
ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to V
Package Power Dissipation Capability (T
= 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
A
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current
1. Output shorted for no more than one second. No more than one output shorted at a time.
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
DD
DD
+0.5V
+2.0V
OPERATING RANGE
Range Ambient Temp V
Commercial 0°C to +70°C 2.7-3.6V
Industrial -40°C to +85°C 2.7-3.6V
DD
TABLE 8: DC OPERATING CHARACTERISTICS
Symbol Parameter
I
DDR
I
DDR2
I
DDW
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL
V
OL2
V
OH
Read Current 10 mA CE#=0.1 VDD/0.9 VDD@25 MHz, SO=open
Read Current 15 mA CE#=0.1 VDD/0.9 VDD@50 MHz, SO=open
Program and Erase Current 30 mA CE#=V
Standby Current 20 µA CE#=VDD, VIN=VDD or V
Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
Output Leakage Current 1 µA V
Input Low Voltage 0.8 V VDD=VDD Min
Input High Voltage 0.7 V
Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min
Output Low Voltage 0.4 V IOL=1.6 mA, VDD=VDD Min
Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min
DD
Limits
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . . C
See Figures 25 and 26
Test ConditionsMin Max Units
DD
SS
=GND to VDD, VDD=VDD Max
OUT
VVDD=VDD Max
= 30 pF
L
T8.0 1271
TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol Parameter Minimum Units
T
PU-READ
T
PU-WRITE
©2006 Silicon Storage Technology, Inc. S71271-02-000 1/06
1
1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
VDD Min to Read Operation 10 µs
VDD Min to Write Operation 10 µs
21
T9.0 1271
Page 22
Data Sheet
16 Mbit SPI Serial Flash
SST25VF016B
TABLE 10: CAPACITANCE (T
= 25°C, f=1 Mhz, other pins open)
A
Parameter Description Test Condition Maximum
1
C
OUT
1
C
IN
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Output Pin Capacitance V
= 0V 12 pF
OUT
Input Capacitance VIN = 0V 6 pF
T10.0 1271
TABLE 11: RELIABILITY CHARACTERISTICS
Symbol Parameter Minimum Specification Units Test Method
1
N
END
1
T
DR
1
I
LT H
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Endurance 10,000 Cycles JEDEC Standard A117
Data Retention 100 Years JEDEC Standard A103
Latch Up 100 + I
DD
mA JEDEC Standard 78
T11.0 1271
TABLE 12: AC OPERATING CHARACTERISTICS
25 MHz 50 MHz
Symbol Parameter Min Max Min Max Units
1
F
CLK
T
SCKH
T
SCKL
2
T
SCKR
T
SCKF
3
T
CES
3
T
CEH
3
T
CHS
3
T
CHH
T
CPH
T
CHZ
T
CLZ
T
DS
T
DH
T
HLS
T
HHS
T
HLH
T
HHH
T
HZ
T
LZ
T
OH
T
V
T
SE
T
BE
T
SCE
T
BP
1. Maximum clock frequency for Read Instruction, 03H, is 25 MHz
2. Maximum Rise and Fall time may be limited by T
3. Relative to SCK.
Serial Clock Frequency 25 50 MHz
Serial Clock High Time 18 9 ns
Serial Clock Low Time 18 9 ns
Serial Clock Rise Time (Slew Rate) 0.1 0.1 V/ns
Serial Clock Fall Time (Slew Rate) 0.1 0.1 V/ns
CE# Active Setup Time 10 5 ns
CE# Active Hold Time 10 5 ns
CE# Not Active Setup Time 10 5 ns
CE# Not Active Hold Time 10 5 ns
CE# High Time 100 50 ns
CE# High to High-Z Output 15 8 ns
SCK Low to Low-Z Output 0 0 ns
Data In Setup Time 5 2 ns
Data In Hold Time 5 5 ns
HOLD# Low Setup Time 10 5 ns
HOLD# High Setup Time 10 5 ns
HOLD# Low Hold Time 10 5 ns
HOLD# High Hold Time 10 5 ns
HOLD# Low to High-Z Output 20 8 ns
HOLD# High to Low-Z Output 15 8 ns
Output Hold from SCK Change 0 0 ns
Output Valid from SCK 15 8 ns
Sector-Erase 25 25 ms
Block-Erase 25 25 ms
Chip-Erase 50 50 ms
Byte-Program 10 10 µs
T12.0 1271
SCKH
and T
requirements
SCKL
©2006 Silicon Storage Technology, Inc. S71271-02-000 1/06
22
Page 23
16 Mbit SPI Serial Flash
SST25VF016B
T
Data Sheet
CPH
CE#
T
CHH
T
CES
SCK
T
DSTDH
SI
SO
MSB
HIGH-Z
FIGURE 21: SERIAL INPUT TIMING DIAGRAM
T
SCKR
T
SCKF
T
CEH
LSB
HIGH-Z
T
CHS
1271 SerIn.0
CE#
T
SCKH
T
SCKL
SCK
T
SO
T
CLZ
OH
MSB
T
V
LSB
T
CHZ
SI
1271 SerOut.0
FIGURE 22: SERIAL OUTPUT TIMING DIAGRAM
©2006 Silicon Storage Technology, Inc. S71271-02-000 1/06
23
Page 24
Data Sheet
CE#
SCK
SO
SI
HOLD#
T
HHH
T
HLS
T
HZ
T
HLH
16 Mbit SPI Serial Flash
SST25VF016B
T
HHS
T
LZ
1271 Hold.0
FIGURE 23: HOLD TIMING DIAGRAM
V
DD
Max
V
DD
Commands may not be accepted or properly
VDD Min
Chip selection is not allowed.
interpreted by the device.
T
PU-READ
T
PU-WRITE
Device fully accessible
1271 PwrUp.0
Time
FIGURE 24: POWER-UP TIMING DIAGRAM
©2006 Silicon Storage Technology, Inc. S71271-02-000 1/06
24
Page 25
16 Mbit SPI Serial Flash
SST25VF016B
V
IHT
V
ILT
Data Sheet
V
HT
REFERENCE POINTS OUTPUTINPUT
V
LT
V
HT
V
LT
1271 IORef.0
AC test inputs are driven at V
for inputs and outputs are V
(0.9VDD) for a logic “1” and V
IHT
(0.6VDD) and VLT (0.4VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
HT
FIGURE 25: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO DUT
1271 TstLd.0
(0.1VDD) for a logic “0”. Measurement reference points
ILT
TO TESTER
Note: V
C
L
- V
- V
- V
- V
HIGH
LOW
INPUT
INPUT
Tes t
Tes t
HIGH Test
LOW Test
HT
V
LT
V
IHT
V
ILT
FIGURE 26: A TEST LOAD EXAMPLE
©2006 Silicon Storage Technology, Inc. S71271-02-000 1/06
25
Page 26
Data Sheet
PRODUCT ORDERING INFORMATION
SST 25 VF 016 B - 50 - 4C - S2A F
XX
XXXXXX- XX -XX- XXX X
16 Mbit SPI Serial Flash
SST25VF016B
Environmental Attribute
1
F
= non-Pb / non-Sn contact (lead) finish:
Nickel plating with Gold top (outer) layer
Package Modifier
A = 8 leads or contacts
Package Type
S2 = SOIC 200 mil body width
Q = WSON
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Operating Frequency
50 = 50 MHz
Device Density
016 = 16 Mbit
Volt ag e
V = 2.7-3.6V
Product Series
25 = Serial Peripheral Interface flash memory
1. Environmental suffix “F” denotes non-Pb/non-SN solder.
SST non-Pb/non-Sn solder devices are “RoHS Compliant”.
Valid combinations for SST25VF016B
SST25VF016B-50-4C-S2AF SST25VF016B-50-4C-QAF
SST25VF016B-50-4I-S2AF SST25VF016B-50-4I-QAF
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2006 Silicon Storage Technology, Inc. S71271-02-000 1/06
26
Page 27
16 Mbit SPI Serial Flash
SST25VF016B
PACKAGING DIAGRAMS
Data Sheet
Pin #1
Identifier
5.40
5.15
Note: 1. All linear dimensions are in millimeters (max/min).
2. Coplanarity: 0.1 mm
3. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.
TOP VIEW SIDE VIEW
1.27 BSC
0.25
5.40
5.15
8.10
7.70
2.16
1.75
0.05
0.25
0.19
0.50
0.35
END VIEW
08-soic-EIAJ-S2A-3
1mm
0˚
8˚
0.80
0.50
8-LEAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) 200 MIL BODY WIDTH (5.2MM X 8MM)
SST P
ACKAGE CODE: S2A
©2006 Silicon Storage Technology, Inc. S71271-02-000 1/06
27
Page 28
Data Sheet
16 Mbit SPI Serial Flash
SST25VF016B
TOP VIEW BOTTOM VIEW
Pin #1
Corner
5.00 ± 0.10
6.00 ± 0.10
Note: 1. All linear dimensions are in millimeters (max/min).
2. Untoleranced dimensions (shown with box surround)
are nominal target dimensions.
3. The external paddle is electrically connected to the
die back-side and possibly to certain V
This paddle can be soldered to the PC board;
it is suggested to connect this paddle to the V
Connection of this paddle to any other voltage potential can
result in shorts and/or electrical malfunction of the device.
SS
leads.
of the unit.
SS
SIDE VIEW
0.2
0.076
0.05 Max
0.80
0.70
1mm
8-CONTACT VERY-VERY-THIN SMALL OUTLINE NO-LEAD (WSON)
SST P
ACKAGE CODE: QA
4.0
3.4
CROSS SECTION
Pin #1
1.27 BSC
0.48
0.35
0.70
0.50
0.80
0.70
8-wson-5x6-QA-9.0
TABLE 13: R
EVISION HISTORY
Number Description Date
00
01
02
• Initial release of data sheet
• Corrected “JEDEC Read-ID” on page 19 including timing diagram
• Corrected V
and VLT values in Figure 25 on page 25
HT
• Migrated document to a Data Sheet
Apr 2005
Sep 2005
Jan 2006
• Updated Surface Mount Solder Reflow Temperature information
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2006 Silicon Storage Technology, Inc. S71271-02-000 1/06
28
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