Page 1
©2002 Fairchild Semiconductor Corporation Rev. B, May 2002
SSP1N50B
SSP1N50B
520V N-Channel M OSFET
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switch mode power supplies,
power factor correction and electronic lamp ballasts based
on half bridge.
Features
• 1.5A, 520V, R
DS(on)
= 5.3Ω @VGS = 10 V
• Low gate charge ( typical 8.3 nC)
• Low Crss ( typical 5.5 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
Absolute Maximum Ratings T
C
= 25°C unless otherwise noted
Thermal Characteristics
Symbol Parameter SSP1N50B Units
V
DSS
Drain-Source Voltage 520 V
I
D
Drain Current
- Continuous (T
C
= 25°C)
1.5 A
- Continuous (T
C
= 100°C)
0.97 A
I
DM
Drain Current - Pulsed
(Note 1)
5.0 A
V
GSS
Gate-Source Voltage ± 30 V
E
AS
Single Pulsed Avalanche Energy
(Note 2)
100 mJ
I
AR
Avalanche Current
(Note 1)
1.5 A
E
AR
Repetitive Avalanche Energy
(Note 1)
3.6 mJ
dv/dt Peak Diode Recovery dv/dt
(Note 3)
3.5 V/ns
P
D
Power Dissipation (TC = 25°C)
36 W
- Derate above 25°C 0.29 W/°C
T
J
, T
STG
Operating and Storage Temperature Range -55 to +150 °C
T
L
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
300 °C
Symbol Parameter Typ Max Units
R
θJC
Thermal Resistance, Junction-to-Case -- 3.44 °C/W
R
θCS
Thermal Resistance, Case-to-Sink 0.5 -- °C/W
R
θJA
Thermal Resistance, Junction-to-Ambient -- 62.5 °C/W
TO-220
SSP Series
G
S
D
!!!!
!!!!
!!!!
""""
!!!!
!!!!
!!!!
####
!!!!
!!!!
!!!!
""""
!!!!
!!!!
!!!!
####
S
D
G
Page 2
Rev. B, May 2002
SSP1N50B
©2002 Fairchild Semiconductor Corporation
Electrical Characteristics T
C
= 25°C unless otherwise noted
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 80mH, IAS = 1.5A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD ≤ 1.5A, di/dt ≤ 200A/µs, VDD ≤ BV
DSS,
Starting TJ = 25°C
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
Symbol Parameter Te st Conditions Min Typ Max Units
Off Characteristics
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, ID = 250 µA
520 -- -- V
∆BV
DSS
/ ∆T
J
Breakdown Voltage Temperature
Coefficient
I
D
= 250 µA, Referenced to 25°C
-- 0.54 -- V/°C
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 520 V, VGS = 0 V
-- -- 10 µA
V
DS
= 400 V, TC = 125°C
-- -- 100 µA
I
GSSF
Gate-Body Leakage Current, Forward
V
GS
= 30 V, VDS = 0 V
-- -- 100 nA
I
GSSR
Gate-Body Leakage Current, Reverse
V
GS
= -30 V, VDS = 0 V
-- -- -100 nA
On Characteristics
V
GS(th)
Gate Threshold Voltage
V
DS
= VGS, ID = 250 µA
2.0 -- 4.0 V
R
DS(on)
Static Drain-Source
On-Resistance
V
GS
= 10 V, ID = 0.75 A
-- 4.1 5.3 Ω
g
FS
Forward Transconductance
V
DS
= 40 V, ID = 0.75 A
-- 1.8 -- S
Dynamic Characteristics
C
iss
Input Capacitance
V
DS
= 25 V, VGS = 0 V,
f = 1.0 MHz
-- 260 340 pF
C
oss
Output Capacitance -- 25 33 pF
C
rss
Reverse Transfer Capacitance -- 5.5 7.2 pF
Switching Characteristics
t
d(on)
Turn-On Delay Time
V
DD
= 250 V, ID = 1.5 A,
R
G
= 25 Ω
-- 14 40 ns
t
r
Turn-On Rise Time -- 40 90 ns
t
d(off)
Turn-Off Delay Time -- 35 80 ns
t
f
Turn-Off Fall Time -- 35 80 ns
Q
g
Total Gate Charge
V
DS
= 400 V, ID = 1.5 A,
V
GS
= 10 V
-- 8.3 11 nC
Q
gs
Gate-Source Charge -- 1.5 -- nC
Q
gd
Gate-Drain Charge -- 3.4 -- nC
Drain-Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain-Source Diode Forward Current -- -- 1.5 A
I
SM
Maximum Pulsed Drain-Source Diode Forward Current -- -- 5.0 A
V
SD
Drain-Source Diode Forward Voltage
V
GS
= 0 V, IS = 1.5 A
-- -- 1.4 V
t
rr
Reverse Recovery Time
V
GS
= 0 V, IS = 1.5 A,
dI
F
/ dt = 100 A/µs
-- 230 -- ns
Q
rr
Reverse Recovery Charge -- 0.94 -- µC
Page 3
Rev. B, May 2002
SSP1N50B
©2002 Fairchild Semiconductor Corporation
0.2 0.4 0.6 0.8 1.0 1.2 1.4
10
-1
10
0
150
$
%
Note s :
1. V
GS
= 0V
2. 250&s Pulse Test
25
$
I
DR
, Reverse Drain Current [A]
VSD, Source-Drain voltage [V]
012345
3
6
9
12
15
VGS = 20V
VGS = 10V
%
Note : T
J
= 25
$
R
DS(ON)
[
'
],
Drain-Source On-Resistance
ID, Drain Current [A]
246810
10
-1
10
0
150oC
25oC
-55oC
%
Note s :
1. V
DS
= 40V
2. 250&s Pulse Test
I
D
, Drain Current [A]
VGS, Gate-Source Voltage [V]
10
-1
10
0
10
1
10
-2
10
-1
10
0
V
GS
Top : 1 5 .0 V
10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
5.5 V
Botto m : 5.0 V
%
Note s :
1. 25 0&s Pulse Test
2. TC = 25
$
I
D
, Drain Current [A]
VDS, Drain-Source Voltage [V]
0.0 1.5 3.0 4.5 6.0 7.5 9.0
0
2
4
6
8
10
12
VDS = 250V
VDS = 100V
VDS = 400V
%
Note : I
D
= 1.5 A
V
GS
, Gate-Source Voltage [V]
QG, Tota l G a te C h a rg e [n C ]
10
-1
10
0
10
1
0
100
200
300
400
500
C
oss
C
iss
= Cgs + Cgd (Cds = shorted)
C
oss
= Cds + C
gd
C
rss
= C
gd
%
Note s :
1. V
GS
= 0 V
2. f = 1 MHz
C
rss
C
iss
Capacitance [pF]
VDS, Drain-Source Voltage [V]
Typical Characteristics
Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics
Figure 3. On-Resistance Variation vs
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation with Source Current
and Temperature
Figure 2. Transfer CharacteristicsFigure 1. On-Region Charact eristics
Page 4
©2002 Fairchild Semiconductor Corporation Rev. B, May 2002
SSP1N50B
-100 -50 0 50 100 150 200
0.0
0.5
1.0
1.5
2.0
2.5
3.0
%
Note s :
1. V
GS
= 10 V
2. I
D
= 0.75 A
R
DS(ON)
, (Normalized)
Drain-Source On-Resistance
TJ, Junction Temperature [oC]
-100 -50 0 50 100 150 200
0.8
0.9
1.0
1.1
1.2
%
Note s :
1. V
GS
= 0 V
2. I
D
= 250 &A
BV
DSS
, (N orma liz e d )
Drain-Source Breakdown Voltage
TJ, Junction Temperature [oC]
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
-1
10
0
%
Notes :
1. Z
(
JC
(t) = 3.44 $/W M a x.
2. D uty F a c to r, D = t
1/t2
3. TJM - TC = PDM * Z
(
JC
(t)
sin g le p u ls e
D=0.5
0.02
0.2
0.05
0.1
0.01
Z
(
JC
(t), The rm al Re s p o ns e
t1, Square Wave Pulse Duration [sec]
25 50 75 100 125 150
0.0
0.3
0.6
0.9
1.2
1.5
1.8
I
D
, Dra in Curre n t [A ]
TC, Case Temperature [$]
10
0
10
1
10
2
10
3
10
-2
10
-1
10
0
10
1
DC
10 ms
1 ms
100 µs
Operation in This Area
is Limited by R
DS(on)
%
Note s :
1. T
C
= 25 oC
2. T
J
= 150 oC
3. Single Pulse
I
D
, Drain Current [A]
VDS, Drain-Source Voltage [V]
Typical Characteristics (Continued)
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
vs Case Temperature
Figure 7. Breakdo w n Voltage Variation
vs Temperature
Figure 8. On-Resistance Variation
vs Temperature
Figure 11. Transient Thermal Response Cur ve
t
1
P
DM
t
2
Page 5
Rev. B, May 2002
SSP1N50B
©2002 Fairchild Semiconductor Corporation
Charge
V
GS
10V
Q
g
Q
gs
Q
gd
3mA
V
GS
DUT
V
DS
300nF
50K)
200nF
12V
Same Type
as DUT
Charge
V
GS
10V
Q
g
Q
gs
Q
gd
3mA
V
GS
DUT
V
DS
300nF
50K)
200nF
12V
Same Type
as DUT
V
GS
V
DS
10%
90%
t
d(on)tr
t
on
t
off
t
d(off)
t
f
V
DD
10V
V
DS
R
L
DUT
R
G
V
GS
V
GS
V
DS
10%
90%
t
d(on)tr
t
on
t
off
t
d(off)
t
f
V
DD
10V
V
DS
R
L
DUT
R
G
V
GS
E
AS
=LI
AS
2
---2
1
-------------------BV
DSS-VDD
BV
DSS
V
DD
V
DS
BV
DSS
t
p
V
DD
I
AS
V
DS
(t)
ID (t)
Time
10V
DUT
R
G
L
I
D
t
p
E
AS
=LI
AS
2
---2
1
E
AS
=LI
AS
2
---2
1
---2
1
-------------------BV
DSS-VDD
BV
DSS
V
DD
V
DS
BV
DSS
t
p
V
DD
I
AS
V
DS
(t)
ID (t)
Time
10V
DUT
R
G
LL
IDI
D
t
p
Gate Charge Test Circuit & Waveform
Resistive Switching Test Circuit & Waveforms
Unclamped Inductive Switching Test Circuit & Waveforms
Page 6
©2002 Fairchild Semiconductor Corporation Rev. B, May 2002
SSP1N50B
Peak Diode Recovery dv/d t Test Circuit & Waveforms
DUT
V
DS
+
_
Driver
R
G
Same Type
as DUT
V
GS
• dv/dt controlled by R
G
•ISDcontroll e d by pulse period
V
DD
L
I
SD
10V
V
GS
( Driver )
I
SD
( DUT )
V
DS
( DUT )
V
DD
Body Diode
Forward Voltage Drop
V
SD
IFM, Body Diode Forward Current
Body Diode Reverse Current
I
RM
Body Diode Recoverydv/dt
di/dt
D =
Gate Pulse Width
Gate Pulse Period
--------------------------
DUT
V
DS
+
_
Driver
R
G
Same Type
as DUT
V
GS
• dv/dt controlled by R
G
•ISDcontroll e d by pulse period
V
DD
LL
I
SD
10V
V
GS
( Driver )
I
SD
( DUT )
V
DS
( DUT )
V
DD
Body Diode
Forward Voltage Drop
V
SD
IFM, Body Diode Forward Current
Body Diode Reverse Current
I
RM
Body Diode Recoverydv/dt
di/dt
D =
Gate Pulse Width
Gate Pulse Period
--------------------------
D =
Gate Pulse Width
Gate Pulse Period
--------------------------
Page 7
Rev. B, May 2002©2002 Fairchild Semiconductor Corporation
SSP1N50B
Dimensions in Millimeters
Package Dimensions
4.50 ±0.20
9.90 ±0.20
1.52 ±0.10
0.80 ±0.10
2.40 ±0.20
10.00 ±0.20
1.27 ±0.10
ø3.60 ±0.10
(8.70)
2.80 ±0.1015.90 ±0.20
10.08 ±0.30
18.95MAX.
(1.70)
(3.70)(3.00)
(1.46)
(1.00)
(45°)
9.20 ±0.2013.08 ±0.20
1.30 ±0.10
1.30
+0.10
–0.05
0.50
+0.10
–0.05
2.54TYP
[2.54
±0.20]
2.54TYP
[2.54
±0.20]
TO-220
Page 8
©2002 Fairchild Semiconductor Corporation
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary First Production This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete Not In Production This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H5
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not
intended to be an exhaustive list of all such trademarks.
STAR*POWER is used under license
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E
2
CMOS™
EnSigna™
FACT™
FACT Quiet Series™
FAST
®
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
I
2
C™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench
®
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SLIENT SWITCHER
®
SMART START™
SPM™
STAR*POWER™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™
UHC™
UltraFET
®
VCX™
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