Datasheet SSM2375 Datasheet (ANALOG DEVICES)

Filterless, High Efficiency,

FEATURES

Filterless Class-D amplifier with spread-spectrum

Σ-Δ modulation

3 W into 3 Ω load and 1.4 W into 8 Ω load at 5.0 V supply

with <1% total harmonic distortion (THD + N)
93% efficiency at 5.0 V, 1.4 W into 8 Ω speaker
>100 dB signal-to-noise ratio (SNR)
High PSSR at 217 Hz: 80 dB
Flexible gain adjustment pin: 0 dB to 12 dB in 3 dB steps
Fixed input impedance: 80 kΩ
User-selectable ultralow EMI emissions mode
Single-supply operation from 2.5 V to 5.5 V
20 nA shutdown current
Short-circuit and thermal protection with autorecovery
Available in 9-ball, 1.5 mm × 1.5 mm WLCSP
Pop-and-click suppression

APPLICATIONS

Mobile phones
MP3 players
Portable electronics

GENERAL DESCRIPTION

The SSM2375 is a fully integrated, high efficiency, Class-D audio
amplifier. It is designed to maximize performance for mobile
phone applications. The application circuit requires a minimum
of external components and operates from a single 2.5 V to 5.5 V
supply. It is capable of delivering 3 W of continuous output power
with <1% THD + N driving a 3 Ω load from a 5.0 V supply.

The SSM2375 features a high efficiency, low noise modulation
scheme that requires no external LC output filters. The modulation
continues to provide high efficiency even at low output power.
The SSM2375 operates with 93% efficiency at 1.4 W into 8 Ω
or with 85% efficiency at 3 W into 3 Ω from a 5.0 V supply and
has an SNR of >100 dB.

FUNCTIONAL BLOCK DIAGRAM

10µF

SSM2375

22nF

IN+
IN–

SHUTDOWN

GAIN SELECT

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

IN+
IN–

22nF

SD

R

GAIN = 0dB, 3dB, 6dB, 9dB, O R 12dB

GAIN

GAIN

CONTROL

GAIN

BIAS

Mono 3 W Class-D Audio Amplifier

SSM2375

Spread-spectrum pulse density modulation (PDM) is used to
provide lower EMI-radiated emissions compared with other
Class-D architectures. The inherent randomized nature of
spread-spectrum PDM eliminates the clock intermodulation
(beating effect) of several amplifiers in close proximity.

The SSM2375 includes an optional modulation select pin
(ultralow EMI emissions mode) that significantly reduces the
radiated emissions at the Class-D outputs, particularly above
100 MHz. In ultralow EMI emissions mode, the SSM2375
can pass FCC Class B radiated emission testing with 50 cm,
unshielded speaker cable without any external filtering.

The device also includes a highly flexible gain select pin that
allows the user to select a gain of 0 dB, 3 dB, 6 dB, 9 dB, or
12 dB. The gain selection feature improves gain matching
between multiple SSM2375 devices within a single application
as compared to using external resistors to set the gain.

The SSM2375 has a micropower shutdown mode with a typical
shutdown current of 20 nA. Shutdown is enabled by applying

EDGE

SD

pin.

OUT+
OUT–

EDGE

GND

EMISSION
CONTROL

09011-001

0.1µF

MODULATOR

(Σ-Δ)

INTERNAL

OSCILLATOR

Figure 1.

a logic low to the

The device also includes pop-and-click suppression circuitry.
This suppression circuitry minimizes voltage glitches at the
output during turn-on and turn-off, reducing audible noise
on activation and deactivation.

Other features that simplify system-level integration of the
SSM2375 include input low-pass filtering to suppress out-of-band
DAC noise interference to the PDM modulator and fixed-input
impedance to simplify component selection across multiple
platform production builds.

The SSM2375 is specified over the industrial temperature range
of −40°C to +85°C. It has built-in thermal shutdown and output
short-circuit protection. It is available in a halide-free, 9-ball,

1.5 mm × 1.5 mm wafer level chip scale package (WLCSP).

POWER SUPPLY

2.5V TO 5.5V

VDD

FET

DRIVER

CONTROL

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2010 Analog Devices, Inc. All rights reserved.

SSM2375

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

Typical Performance Characteristics ............................................. 7

Typical Application Circuits .......................................................... 12

REVISION HISTORY

9/10—Revision 0: Initial Version

Theory of Operation ...................................................................... 13

Overview ..................................................................................... 13

Gain Selection ............................................................................. 13

Pop-and-Click Suppression ...................................................... 13

EMI Noise .................................................................................... 13

Output Modulation Description .............................................. 13

Layout .......................................................................................... 14

Input Capacitor Selection .......................................................... 14

Power Supply Decoupling ......................................................... 14

Outline Dimensions ....................................................................... 15

Ordering Guide .......................................................................... 15

Rev. 0 | Page 2 of 16

SSM2375

SPECIFICATIONS

VDD = 5.0 V, TA = 25°C, RL = 8 Ω +33 μH, EDGE = GND, unless otherwise noted.

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

DEVICE CHARACTERISTICS

Output Power P

O

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

Efficiency η PO = 1.4 W into 8 Ω, VDD = 5.0 V 93 %

Total Harmonic Distortion + Noise THD + N PO = 1 W into 8 Ω, f = 1 kHz, VDD = 5.0 V 0.01 %

P

1.0 VDD − 1 V

Input Common-Mode Voltage

V

CM

Range
Common-Mode Rejection Ratio CMRR
Average Switching Frequency fSW 250 kHz
Differential Output Offset Voltage V

OOS

POWER SUPPLY

Supply Voltage Range V

DD

Power Supply Rejection Ratio PSRR Inputs are ac-grounded, CIN = 0.1 μF
V
V
Supply Current I

SY

V
V
V
V
V
Shutdown Current ISD

GAIN CONTROL

Closed-Loop Gain Gain 0 12 dB
Input Impedance Z

IN

SHUTDOWN CONTROL

Input Voltage High V
Input Voltage Low V
Turn-On Time t

Turn-Off Time t
Output Impedance Z

IH

IL

WU

SD

OUT

f = 1 kHz, 20 kHz BW

= 8 Ω, THD = 1%, VDD = 5.0 V 1.42 W

L

= 8 Ω, THD = 1%, VDD = 3.6 V 0.72 W

L

= 8 Ω, THD = 1%, VDD = 2.5 V 0.33 W

L

= 8 Ω, THD = 10%, VDD = 5.0 V 1.77 W

L

= 8 Ω, THD = 10%, VDD = 3.6 V 0.91 W

L

= 8 Ω, THD = 10%, VDD = 2.5 V 0.42 W

L

= 4 Ω, THD = 1%, VDD = 5.0 V 2.52 W

L

= 4 Ω, THD = 1%, VDD = 3.6 V 1.28 W

L

= 4 Ω, THD = 1%, VDD = 2.5 V 0.56 W

L

= 4 Ω, THD = 10%, VDD = 5.0 V 3.171 W

L

= 4 Ω, THD = 10%, VDD = 3.6 V 1.6 W

L

= 4 Ω, THD = 10%, VDD = 2.5 V 0.72 W

L

= 3 Ω, THD = 1%, VDD = 5.0 V 3.21 W

L

= 3 Ω, THD = 1%, VDD = 3.6 V 1.52 W

L

= 3 Ω, THD = 1%, VDD = 2.5 V 0.68 W

L

= 3 Ω, THD = 10%, VDD = 5.0 V 3.71 W

L

= 3 Ω, THD = 10%, VDD = 3.6 V 1.9 W

L

= 3 Ω, THD = 10%, VDD = 2.5 V 0.85 W

L

= 0.5 W into 8 Ω, f = 1 kHz, VDD = 3.6 V 0.01 %

O

GSM VCM

= 2.5 V ± 100 mV, f = 217 Hz, output referred 55 dB

Gain = 6 dB 0.1 2.0 mV

Guaranteed from PSRR test 2.5 5.5 V

= 100 mV at 217 Hz 80 dB

RIPPLE

= 100 mV at 1 kHz 80 dB

RIPPLE

VIN = 0 V, no load, VDD = 5.0 V 3.0 mA

= 0 V, no load, VDD = 3.6 V 2.7 mA

IN

= 0 V, no load, VDD = 2.5 V 2.5 mA

IN

= 0 V, RL = 8 Ω + 33 μH, VDD = 5.0 V 3.1 mA

IN

= 0 V, RL = 8 Ω + 33 μH, VDD = 3.6 V 2.8 mA

IN

= 0 V, RL = 8 Ω + 33 μH, VDD = 2.5 V 2.6 mA

IN

= GND

SD

SD = VDD, fixed input impedance (0 dB to 12 dB)

20 nA

80 kΩ

1.35 V

0.35 V
SD rising edge from GND to VDD
SD falling edge from VDD to GND

= GND

SD

Rev. 0 | Page 3 of 16

12.5 ms
5 μs
>100 kΩ

SSM2375

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

NOISE PERFORMANCE

Output Voltage Noise en

= 5.0 V, f = 20 Hz to 20 kHz, inputs are

V

DD

ac-grounded, gain = 6 dB, A-weighted

Signal-to-Noise Ratio SNR PO = 1.4 W, RL = 8 Ω 100 dB

1

Although the SSM2375 has good audio quality above 3 W, continuous output power beyond 3 W without a heat sink must be avoided due to device packaging limitations.

30 μV rms

Rev. 0 | Page 4 of 16

SSM2375

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings apply at 25°C, unless otherwise noted.

Table 2.

Parameter Rating

Supply Voltage 6 V
Input Voltage V
Common-Mode Input Voltage V
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +165°C
Lead Temperature (Soldering, 60 sec) 300°C
ESD Susceptibility 4 kV

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

DD

DD

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type PCB θJA θJB Unit

9-Ball, 1.5 mm × 1.5 mm WLCSP 1S0P 162 39 °C/W
2S0P 76 21 °C/W

ESD CAUTION

Rev. 0 | Page 5 of 16

SSM2375

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

BALL A1
CORNER

321

IN–

A

IN+ EDGE OUT–

B

GND VDD OUT+

C

TOP VIEW

(BALL SIDE DOWN)

Not to Scale

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1A IN− Inverting Input.
1B IN+ Noninverting Input.
1C GND Ground.
2A

SD

Shutdown Input. Active low digital input.

2B EDGE Edge Rate Control. Active high.
2C VDD Power Supply.
3A GAIN Gain Control Pin.
3B OUT− Inverting Output.
3C OUT+ Noninverting Output.

SD

GAIN

09011-002

Rev. 0 | Page 6 of 16

SSM2375

TYPICAL PERFORMANCE CHARACTERISTICS

100

10

1

RL = 8Ω + 33µH
GAIN = 6dB

VDD = 3.6V

100

10

1

RL = 8Ω + 33µH
GAIN = 12dB

VDD = 3.6V

0.1

THD + N (%)

0.01

0.001

0.0001 10

0.001 0.01 0.1 1

VDD = 2.5V

VDD = 5V

OUTPUT POWER (W)

09011-003

0.1

THD + N (%)

0.01

0.001

0.0001 10

0.001 0.01 0.1 1

VDD = 2.5V

OUTPUT POWER (W)

Figure 3. THD + N vs. Output Power into 8 Ω, Gain = 6 dB Figure 6. THD + N vs. Output Power into 8 Ω, Gain = 12 dB

100

RL = 4Ω + 15µH
GAIN = 6dB

10

VDD = 3.6V

1

0.1

THD + N (%)

0.01

0.001

0.0001 10

0.001 0.01 0.1 1
OUTPUT POWER (W)

VDD = 2.5V

VDD = 5V

09011-010

100

RL = 4Ω + 15µH
GAIN = 12dB

10

1

0.1

THD + N (%)

0.01

0.001

0.0001 10

0.001 0.01 0.1 1
OUTPUT POWER (W)

VDD = 3.6V

VDD = 2.5V

Figure 4. THD + N vs. Output Power into 4 Ω, Gain = 6 dB Figure 7. THD + N vs. Output Power into 4 Ω, Gain = 12 dB

VDD = 5V

09011-004

VDD = 5V

09011-011

100

VDD = 5V
GAIN = 6dB
R

= 8Ω + 33µH

L

10

1

0.1

THD + N (%)

0.01

0.001
10 100k

1W

0.25W

0.5W

100 1k 10k

FREQUENCY (Hz)

09011-012

100

VDD = 5V
GAIN = 12dB
R

= 8Ω + 33µH

L

10

1

0.1

THD + N (%)

0.01

0.001
10 100k

1W

0.25W

0.5W

100 1k 10k

FREQUENCY (Hz)

Figure 5. THD + N vs. Frequency, VDD = 5 V, RL = 8 Ω, Gain = 6 dB Figure 8. THD + N vs. Frequency, VDD = 5 V, RL = 8 Ω, Gain = 12 dB

Rev. 0 | Page 7 of 16

09011-013

SSM2375

100

10

VDD = 5V
GAIN = 6dB
R

= 4Ω + 15µH

L

100

10

VDD = 5V
GAIN = 12dB
R

= 4Ω + 15µH

L

1

0.1

THD + N (%)

0.01

0.001
10 100k

2W

0.5W

1W

100 1k 10k

FREQUENCY (Hz)

Figure 9. THD + N vs. Frequency, VDD = 5 V, RL = 4 Ω, Gain = 6 dB

100

VDD = 3.6V
GAIN = 6dB
R

=8Ω + 33µ H

L

10

1

0.5W

0.1

THD + N (%)

0.01

0.25W

1

0.1

THD + N (%)

0.01

0.001

09011-014

10 100k

2W

0.5W

1W

100 1k 10k

FREQUENCY (Hz)

09011-015

Figure 12. THD + N vs. Frequency, VDD = 5 V, RL = 4 Ω, Gain = 12 dB

100

VDD = 3.6V
GAIN = 12dB
R

=8Ω + 33µ H

L

10

1

0.5W

0.1

THD + N (%)

0.01

0.25W

0.125W

0.001
10 100k

100 1k 10k

FREQUENCY (Hz)

Figure 10. THD + N vs. Frequency, VDD = 3.6 V, RL = 8 Ω, Gain = 6 dB

100

VDD = 3.6V
GAIN = 6dB
R

= 4Ω + 15µH

L

10

1

0.1

THD + N (%)

0.01

0.001
10 100k

1W

0.25W

0.5W

100 1k 10k

FREQUENCY (Hz)

Figure 11. THD + N vs. Frequency, VDD = 3.6 V, RL = 4 Ω, Gain = 6 dB

0.001

09011-016

10 100k

100 1k 10k

FREQUENCY (Hz)

0.125W

09011-017

Figure 13. THD + N vs. Frequency, VDD = 3.6 V, RL = 8 Ω, Gain = 12 dB

100

VDD = 3.6V
GAIN = 12dB
R

= 4Ω + 15µH

L

10

1

0.1

THD + N (%)

0.01

0.001

09011-018

10 100k

1W

0.25W

0.5W

100 1k 10k

FREQUENCY (Hz)

09011-019

Figure 14. THD + N vs. Frequency, VDD = 3.6 V, RL = 4 Ω, Gain = 12 dB

Rev. 0 | Page 8 of 16

SSM2375

100

10

VDD = 2.5V
GAIN = 6dB
R

= 8Ω + 33µH

L

100

10

VDD = 2.5V
GAIN = 12dB
R

= 8Ω + 33µH

L

1

0.1

THD + N (%)

0.01

0.001
10 100k

0.25W

0.0625W

0.125W

100 1k 10k

FREQUENCY (Hz)

Figure 15. THD + N vs. Frequency, VDD = 2.5 V, RL = 8 Ω, Gain = 6 dB

100

VDD = 2.5V
GAIN = 6dB
R

= 4Ω + 15µH

L

10

1

0.1

THD + N (%)

0.01

0.001
10 100k

0.25W

0.0625W

0.125W

100 1k 10k

FREQUENCY (Hz)

Figure 16. THD + N vs. Frequency, VDD = 2.5 V, RL = 4 Ω, Gain = 6 dB

1

0.1

THD + N (%)

0.01

0.001

09011-020

10 100k

0.25W

0.0625W

0.125W

100 1k 10k

FREQUENCY (Hz)

09011-021

Figure 18. THD + N vs. Frequency, VDD = 2.5 V, RL = 8 Ω, Gain = 12 dB

100

VDD = 2.5V
GAIN = 12dB
R

= 4Ω + 15µH

L

10

1

0.1

THD + N (%)

0.01

0.001

09011-022

10 100k

0.25W

0.0625W

0.125W

100 1k 10k

FREQUENCY (Hz)

09011-023

Figure 19. THD + N vs. Frequency, VDD = 2.5 V, RL = 4 Ω, Gain = 12 dB

3.8
GAIN = 0dB

3.6

3.4

3.2

3.0

2.8

2.6

QUIESCENT CURRENT (mA)

2.4

2.2

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

8Ω + 33µH

4Ω + 15µH

NO LOAD

SUPPLY VOLTAGE (V)

Figure 17. Quiescent Current vs. Supply Voltage, Gain = 0 dB

09011-024

Rev. 0 | Page 9 of 16

3.8
GAIN = 12dB

3.6

3.4

3.2

3.0

2.8

2.6

QUIESCENT CURRENT (mA)

2.4

2.2

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

8Ω + 33µH

4Ω + 15µH

NO LOAD

SUPPLY VOLTAGE (V)

Figure 20. Quiescent Current vs. Supply Voltage, Gain = 12 dB

09011-025

SSM2375

2.0
f = 1kHz

1.8
GAIN = 0dB

R

= 8Ω + 33µH

L

1.6

1.4

1.2

1.0

0.8

0.6

OUTPUT POWER (W)

0.4

0.2

THD + N = 10%

THD + N = 1%

0

2.5 3.0 3.5 4.0 4.5 5.0
SUPPLY VOLTAGE (V)

09011-026

Figure 21. Maximum Output Power vs. Supply Voltage, RL = 8 Ω, Gain = 0 dB

2.0
f = 1kHz

1.8
GAIN = 12dB

R

= 8Ω + 33µH

1.6

1.4

1.2

1.0

0.8

0.6

OUTPUT POWER (W)

0.4

0.2

L

THD + N = 10%

THD + N = 1%

0

2.5 3.0 3.5 4.0 4.5 5.0
SUPPLY VOLTAGE (V)

09011-027

Figure 24. Maximum Output Power vs. Supply Voltage, RL = 8 Ω, Gain = 12 dB

3.5
f = 1kHz

3.0

GAIN = 0dB
R

= 4Ω + 15µH

L

2.5

2.0

1.5

OUTPUT POWER (W)

1.0

0.5

0

2.5 3.0 3.5 4.0 4.5 5.0

THD + N = 10%

SUPPLY VOLTAGE (V)

THD + N = 1%

09011-028

Figure 22. Maximum Output Power vs. Supply Voltage, RL = 4 Ω, Gain = 0 dB

100

VDD = 2.5V

90

80

70

60

50

40

EFFICIENCY (%)

30

20

10

0

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

VDD = 3.6V

OUTPUT POWER (W)

VDD = 5V

RL = 8Ω + 33µH
GAIN = 6dB

09011-030

Figure 23. Efficiency vs. Output Power into 8 Ω, Gain = 6 dB

3.5

f = 1kHz

3.0

GAIN = 12dB
R

= 4Ω + 15µH

L

2.5

2.0

1.5

OUTPUT POWER (W)

1.0

0.5

0

2.5 3.0 3.5 4.0 4.5 5.0

THD + N = 10%

SUPPLY VOLTAGE (V)

THD + N = 1%

09011-029

Figure 25. Maximum Output Power vs. Supply Voltage, RL = 4 Ω, Gain = 12 dB

100

VDD = 2.5V

90

80

70

60

50

40

EFFICIENCY (%)

30

20

10

0

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

VDD = 3.6V

OUTPUT POWER (W)

VDD = 5V

RL = 4Ω + 15µH
GAIN = 6dB

09011-031

Figure 26. Efficiency vs. Output Power into 4 Ω, Gain = 6 dB

Rev. 0 | Page 10 of 16

SSM2375

400

350

RL = 8Ω + 33µH
GAIN = 6dB

VDD= 5V

800

700

RL = 4Ω + 15µH
GAIN = 6dB

VDD= 5V

300

250

VDD= 2.5V

200

150

SUPPLY CURRENT ( mA)

100

50

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

02

VDD = 3.6V

OUTPUT POWER (W)

.0

09011-032

600

500

400

VDD= 2.5V

300

SUPPLY CURRENT ( mA)

200

100

0

03

VDD = 3.6V

0.5 1.0 1.5 2.0 2.5 3.0
OUTPUT POWER (W)

Figure 27. Supply Current vs. Output Power into 8 Ω, Gain = 6 dB Figure 30. Supply Current vs. Output Power into 4 Ω, Gain = 6 dB

0
–10

–20

–30

–40

–50

CMRR (dB)

–60

–70

–80

–90

–100

10 100k

100 1k 10k

FREQUENCY (Hz)

09011-036

0
–10

–20

–30

–40

–50

PSRR (dB)

–60

–70

–80

–90

–100

10 100k

100 1k 10k

FREQUENCY (Hz)

Figure 28. Common-Mode Rejection Ratio (CMRR) vs. Frequency Figure 31. Power Supply Rejection Ratio (PSRR) vs. Frequency

.5

09011-033

09011-037

VOLTAGE (V)

7

6

5

4

3

2

1

0

–1

–8 –4 36322824201612840

SD INPUT

OUTPUT

TIME (ms)

09011-038

7

SD INPUT
OUTPUT

6

5

4

3

VOLTAGE (V)

2

1

0

–50 –30 –10 10 30 50 70

TIME (µs)

09011-039

Figure 29. Turn-On Response Figure 32. Turn-Off Response

Rev. 0 | Page 11 of 16

SSM2375

G

G

G

G

TYPICAL APPLICATION CIRCUITS

10µF

SSM2375

22nF

IN+
IN–

SHUTDOWN

AIN SELECT
AIN = 0dB (G ND) , 3dB (OPEN) , 6dB (VDD), 9dB (GND), O R 12dB (VDD)

R

IN+
IN–

22nF

SD

(9dB/12dB ONLY)

GAIN

GAIN

CONTROL

GAIN

MODULATOR

BIAS

0.1µF

(Σ-Δ)

INTERNAL

OSCILLATOR

Figure 33. Monaural Differential Input Configuration

10µF

SSM2375

22nF

IN+

SHUTDOWN

R

AIN SELECT
AIN = 0dB (G ND) , 3dB (OPEN) , 6dB (VDD), 9dB (GND), O R 12dB (VDD)

GAIN

IN+
IN–

22nF

SD

(9dB/12dB ONLY)

GAIN

CONTROL

GAIN

Figure 34. Monaural Single-Ended Input Configuration

MODULATOR

BIAS

0.1µF

(Σ-Δ)

INTERNAL

OSCILLATOR

POWER SUPPLY

2.5V TO 5.5V

VDD

FET

DRIVER

EDGE

CONTROL

POWER SUPPLY

2.5V TO 5.5V

VDD

FET

DRIVER

EDGE

CONTROL

OUT+
OUT–

EDGE

GND

OUT+
OUT–

EDGE

GND

09011-005

09011-006

Rev. 0 | Page 12 of 16

SSM2375

THEORY OF OPERATION

OVERVIEW

The SSM2375 mono Class-D audio amplifier features a filterless
modulation scheme that greatly reduces the external component
count, conserving board space and, thus, reducing systems cost.
The SSM2375 does not require an output filter but, instead, relies
on the inherent inductance of the speaker coil and the natural
filtering of the speaker and human ear to fully recover the audio
component of the switching output.

Most Class-D amplifiers use some variation of pulse-width
modulation (PWM), but the SSM2375 uses Σ-Δ modulation to
determine the switching pattern of the output devices, resulting
in a number of important benefits.

• Σ-Δ modulators do not produce a sharp peak with many

harmonics in the AM frequency band, as pulse-width
modulators often do.

• Σ-Δ modulation provides the benefits of reducing the

amplitude of spectral components at high frequencies,
that is, reducing EMI emissions that might otherwise be
radiated by speakers and long cable traces.

• Due to the inherent spread-spectrum nature of Σ-Δ modu-

lation, the need for oscillator synchronization is eliminated
for designs that incorporate multiple SSM2375 amplifiers.

The SSM2375 also integrates overcurrent and overtemperature
protection.

GAIN SELECTION

The preset gain of the SSM2375 can be set from 0 dB to 12 dB
in 3 dB steps with one external resistor (optional). The external
resistor is used to select the 9 dB or 12 dB gain setting, as shown
in Tab l e 5.

Table 5. Gain Function Descriptions

Gain Setting (dB) GAIN Pin Configuration

12 Tie to VDD through 47 kΩ resistor
9 Tie to GND through 47 kΩ resistor
6 Tie to VDD
3 Open
0 Tie to GND

POP-AND-CLICK SUPPRESSION

Voltage transients at the output of audio amplifiers can occur
when shutdown is activated or deactivated. Voltage transients as
low as 10 mV can be heard as an audio pop in a low sensitivity
handset speaker. Clicks and pops can also be classified as undesir­able audible transients generated by the amplifier system and,
therefore, as not coming from the system input signal.

The SSM2375 has a pop-and-click suppression architecture that
reduces these output transients, resulting in noiseless activation
and deactivation from the
typical audio configuration.

SD

control pin while operating in a

EMI NOISE

The SSM2375 uses a proprietary modulation and spread-spectrum
technology to minimize EMI emissions from the device. For
applications that have difficulty passing FCC Class B emission
tests, the SSM2375 includes a modulation select pin (ultralow
EMI emissions mode) that significantly reduces the radiated
emissions at the Class-D outputs, particularly above 100 MHz.

EMI emission tests on the SSM2375 were performed in a certified
FCC Class B laboratory in low emissions mode (EDGE = VDD).
With a pink noise source, an 8 Ω speaker load, and a 5 V supply,
the SSM2375 was able to pass FCC Class B limits with 50 cm,
unshielded twisted pair speaker cable. Note that reducing the
power supply voltage greatly reduces radiated emissions.

OUTPUT MODULATION DESCRIPTION

The SSM2375 uses three-level, Σ-Δ output modulation. Each
output can swing from GND to V
no input signal is present, the output differential voltage is 0 V
because there is no need to generate a pulse. In a real-world
situation, there are always noise sources present.

Due to this constant presence of noise, a differential pulse is
generated, when required, in response to this stimulus. A small
amount of current flows into the inductive load when the differ­ential pulse is generated.

Most of the time, however, the output differential voltage is 0 V,
due to the Analog Devices, Inc., three-level, Σ-Δ output modula­tion. This feature ensures that the current flowing through the
inductive load is small.

When the user wants to send an input signal, an output pulse
is generated to follow the input voltage. The differential pulse
density is increased by raising the input signal level. Figure 35
depicts three-level, Σ-Δ output modulation with and without
input stimulus.

OUTPUT = 0V

OUT+

OUT–

VOUT

OUTPUT > 0V

OUT+

OUT–

VOUT

OUTPUT < 0V

OUT+

OUT–

VOUT

Figure 35. Three-Level, Σ-Δ Output Modulation With and Without Input Stimulus

and vice versa. Ideally, when

DD

+5V
0V

+5V
0V

+5V
0V
–5V

+5V
0V

+5V
0V

+5V
0V

+5V
0V

+5V
0V

0V
–5V

9011-009

Rev. 0 | Page 13 of 16

SSM2375

LAYOUT

As output power increases, care must be taken to lay out PCB
traces and wires properly among the amplifier, load, and power
supply. A good practice is to use short, wide PCB tracks to
decrease voltage drops and minimize inductance. The PCB
layout engineer must avoid ground loops where possible to
minimize common-mode current associated with separate paths
to ground. Ensure that track widths are at least 200 mil for every
inch of track length for lowest DCR, and use 1 oz or 2 oz copper
PCB traces to further reduce IR drops and inductance. A poor
layout increases voltage drops, consequently affecting efficiency.
Use large traces for the power supply inputs and amplifier outputs
to minimize losses due to parasitic trace resistance.

Proper grounding guidelines help to improve audio performance,
minimize crosstalk between channels, and prevent switching
noise from coupling into the audio signal. To maintain high
output swing and high peak output power, the PCB traces that
connect the output pins to the load, as well as the PCB traces to
the supply pins, should be as wide as possible to maintain the
minimum trace resistances. It is also recommended that a large
ground plane be used for minimum impedances.

In addition, good PCB layout isolates critical analog paths from
sources of high interference. High frequency circuits (analog
and digital) should be separated from low frequency circuits.

Properly designed multilayer PCBs can reduce EMI emissions
and increase immunity to the RF field by a factor of 10 or more,
compared with double-sided boards. A multilayer board allows
a complete layer to be used for the ground plane, whereas the
ground plane side of a double-sided board is often disrupted by
signal crossover.

INPUT CAPACITOR SELECTION

The SSM2375 does not require input coupling capacitors if the
input signal is biased from 1.0 V to V
are required if the input signal is not biased within this recom­mended input dc common-mode voltage range, if high-pass
filtering is needed, or if a single-ended source is used. If high­pass filtering is needed at the input, the input capacitor and the
input resistor of the SSM2375 form a high-pass filter whose
corner frequency is determined by the following equation:

f

= 1/(2π × RIN × CIN)

C

The input capacitor can significantly affect the performance of
the circuit. Not using input capacitors degrades both the output
offset of the amplifier and the dc PSRR performance.

− 1.0 V. Input capacitors

DD

POWER SUPPLY DECOUPLING

To ensure high efficiency, low total harmonic distortion (THD),
and high PSRR, proper power supply decoupling is necessary.
Noise transients on the power supply lines are short-duration
voltage spikes. These spikes can contain frequency components
that extend into the hundreds of megahertz. The power supply
input must be decoupled with a good quality, low ESL, low ESR
capacitor, with a minimum value of 4.7 μF. This capacitor
bypasses low frequency noises to the ground plane. For high
frequency transient noises, use a 0.1 μF capacitor as close as
possible to the VDD pin of the device. Placing the decoupling
capacitors as close as possible to the SSM2375 helps to maintain
efficient performance.

Rev. 0 | Page 14 of 16

SSM2375

OUTLINE DIMENSIONS

0.655

0.600

0.545
SEATING

PLANE

0.350

0.320

0.290

123

A

B

A1 BALL
CORNER

1.490

1.460 SQ

1.430

C

C

101507-

TOP VIEW

(BALL SIDE DOWN )

0.385

0.360

0.335

0.50
BALL PI TCH

0.270

0.240

0.210

BOTTOM VIEW

(BALL SIDE UP)

Figure 36. 9-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-9-2)

Dimensions shown in millimeters

ORDERING GUIDE

1

Model

SSM2375CBZ-REEL −40°C to +85°C 9-Ball Wafer Level Chip Scale Package [WLCSP] CB-9-2
SSM2375CBZ-REEL7 −40°C to +85°C 9-Ball Wafer Level Chip Scale Package [WLCSP] CB-9-2
EVAL-SSM2375Z Evaluation Board

1

Z = RoHS Compliant Part.

2

This package option is halide free.

Temperature Range Package Description Package Option

2

Rev. 0 | Page 15 of 16

SSM2375

NOTES

©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09011-0-9/10(0)

Rev. 0 | Page 16 of 16