Datasheet SSM2335 Datasheet (ANALOG DEVICES)

Filterless, High Efficiency,

www.BDTIC.com/ADI

FEATURES

Filterless Class-D amplifier with Σ-Δ modulation
No sync necessary when using multiple Class-D amplifiers

from Analog Devices, Inc.

3 W into 3 Ω load and 1.4 W into 8 Ω load at 5.0 V supply

with <1% total harmonic distortion (THD + N)
93% efficiency at 5.0 V, 1.4 W into 8 Ω speaker
>96 dB signal-to-noise ratio (SNR)
Single-supply operation from 2.5 V to 5.5 V
20 nA ultralow shutdown current
Short-circuit and thermal protection
Available in 9-ball, 1.5 mm × 1.5 mm WLCSP
Pop-and-click suppression
Built-in resistors reduce board component count
Default fixed 18 dB or user-adjustable gain setting

APPLICATIONS

Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys

GENERAL DESCRIPTION

The SSM2335 is a fully integrated, high efficiency, Class-D audio
amplifier. It is designed to maximize performance for mobile
phone applications. The application circuit requires a minimum
of external components and operates from a single 2.5 V to 5.5 V
supply. It is capable of delivering 3 W of continuous output power
with <1% THD + N driving a 3 Ω load from a 5.0 V supply.

Mono 3 W Class-D Audio Amplifier

SSM2335

The SSM2335 features a high efficiency, low noise modulation
scheme that requires no external LC output filters. The modu­lation continues to provide high efficiency even at low output
power. It operates with 93% efficiency at 1.4 W into 8 Ω or 85%
efficiency at 3 W into 3 Ω from a 5.0 V supply and has an SNR
of >96 dB. Spread-spectrum pulse density modulation is used
to provide lower EMI-radiated emissions compared with other
Class-D architectures.

The SSM2335 has a micropower shutdown mode with a typical
shutdown current of 20 nA. Shutdown is enabled by applying
a logic low to the

The device also includes pop-and-click suppression circuitry.
This suppression circuitry minimizes voltage glitches at the
output during turn-on and turn-off, reducing audible noise
on activation and deactivation.

The fully differential input of the SSM2335 provides excellent
rejection of common-mode noise on the input. Input coupling
capacitors can be omitted if the input dc common-mode voltage
is approximately V

The default gain of the SSM2335 is 18 dB, but users can reduce the
gain by using a pair of external resistors (see the Gain section).

The SSM2335 is specified over the industrial temperature range
of −40°C to +85°C. It has built-in thermal shutdown and output
short-circuit protection. It is available in a 9-ball, 1.5 mm ×

1.5 mm wafer level chip scale package (WLCSP).

SD

DD

pin.

/2.

FUNCTIONAL BLOCK DIAGRAM

SSM2335

AUDIO IN+

AUDIO IN–

SHUTDOWN

*INPUT CAPACITORS ARE O PTIONAL IF INPUT DC COMMON-MO DE

VOLTAGE IS APPROXIMATELY V

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

47nF*

47nF*

IN+

IN–

SD

20kΩ

20kΩ

/2.

DD

MODULATOR

BIAS

10µF

160kΩ

(Σ-Δ)

160kΩ

Figure 1.

0.1µF

VDD

FET

DRIVER

INTERNAL

OSCILLATOR

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

POP-AND-CLICK

SUPPRESSION

GND

VBATT

2.5V TO 5.5V

OUT–

OUT+

7551-001

SSM2335

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 4

Thermal Resistance ...................................................................... 4

ESD Caution .................................................................................. 4

Pin Configuration and Function Descriptions ............................. 5

Typical Performance Characteristics ............................................. 6

REVISION HISTORY

10/08—Revision 0: Initial Version

Typical Application Circuits ......................................................... 11

Theory of Operation ...................................................................... 12

Overview ..................................................................................... 12

Gain .............................................................................................. 12

Pop-and-Click Suppression ...................................................... 12

Output Modulation Description .............................................. 12

Layout .......................................................................................... 13

Input Capacitor Selection .......................................................... 13

Power Supply Decoupling ......................................................... 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. 0 | Page 2 of 16

SSM2335

www.BDTIC.com/ADI

SPECIFICATIONS

VDD = 5.0 V, TA = 25°C, RL = 8 Ω +33 μH, unless otherwise noted.

Table 1.

Parameter Symbol Test Conditions/Comments

DEVICE CHARACTERISTICS

Output Power P

O

R

R

R

R

R

R

R

R

R

R

R

f = 1 kHz, 20 kHz BW
RL = 8 Ω, THD = 1%, VDD = 5.0 V 1.48 W

= 8 Ω, THD = 1%, VDD = 3.6 V 0.75 W

L

= 8 Ω, THD = 10%, VDD = 5.0 V 1.84 W

L

= 8 Ω, THD = 10%, VDD = 3.6 V 0.94 W

L

= 4 Ω, THD = 1%, VDD = 5.0 V 2.72 W

L

= 4 Ω, THD = 1%, VDD = 3.6 V 1.38 W

L

= 4 Ω, THD = 10%, VDD = 5.0 V 3.40

L

= 4 Ω, THD = 10%, VDD = 3.6 V 1.72 W

L

= 3 Ω, THD = 1%, VDD = 5.0 V

L

= 3 Ω, THD = 1%, VDD = 3.6 V 1.72 W

L

= 3 Ω, THD = 10%, VDD = 5.0 V

L

= 3 Ω, THD = 10%, VDD = 3.6 V 2.14 W

L

Efficiency η PO = 1.4 W, 8 Ω, VDD = 5.0 V 93 %

Total Harmonic Distortion + Noise THD + N PO = 1 W into 8 Ω, f = 1 kHz, VDD = 5.0 V 0.01 %

P

= 0.5 W into 8 Ω, f = 1 kHz, VDD = 3.6 V 0.01 %

O

Input Common-Mode Voltage Range VCM 1.0 VDD − 1.0 V

Common-Mode Rejection Ratio CMRR

GSM VCM

= 2.5 V ± 100 mV at 217 Hz, output referred 60 dB
Average Switching Frequency fSW 300 kHz
Differential Output Offset Voltage V

OOS

Gain = 18 dB 2.0 mV

POWER SUPPLY

Supply Voltage Range V

DD

Guaranteed from PSRR test 2.5 5.5 V
Power Supply Rejection Ratio PSRRDC VDD = 2.5 V to 5.0 V, dc input floating 60 85 dB
PSRR
Supply Current I

SY

V
V
V
V
V
Shutdown Current ISD

V

GSM

= 100 mV at 217 Hz, inputs ac GND, CIN = 0.1 μF 65 dB

RIPPLE

VIN = 0 V, no load, VDD = 5.0 V 3.2 mA

= 0 V, no load, VDD = 3.6 V 2.8 mA

IN

= 0 V, no load, VDD = 2.5 V 2.4 mA

IN

= 0 V, load = 8 Ω + 33 μH, VDD = 5.0 V 3.3 mA

IN

= 0 V, load = 8 Ω + 33 μH, VDD = 3.6 V 2.9 mA

IN

= 0 V, load = 8 Ω + 33 μH, VDD = 2.5 V 2.4 mA

IN

SD

= GND

GAIN CONTROL

Closed-Loop Gain Gain 18 dB
Differential Input Impedance Z

IN

SD

= VDD

SHUTDOWN CONTROL

Input Voltage High V
Input Voltage Low V
Turn-On Time t
Turn-Off Time t

Output Impedance Z

WU

SD

IH

IL

OUT

ISY ≥ 1 mA 1.2 V

ISY ≤ 300 nA 0.5 V

SD

rising edge from GND to VDD

SD

falling edge from VDD to GND

SD

= GND

NOISE PERFORMANCE

Output Voltage Noise en V

= 3.6 V, f = 20 Hz to 20 kHz, inputs are

DD

ac-grounded, gain = 18 dB, A-weighted
Signal-to-Noise Ratio SNR PO = 1.4 W, RL = 8 Ω 96 dB

1

Although the SSM2335 has good audio quality above 3 W, continuous output power beyond 3 W must be avoided due to device packaging limitations.

2

This value represents measured performance; packaging limitations must not be exceeded.

1

Min Typ Max Unit

2

W

2

3.43

4.28

W

2

W

20 nA

20 kΩ

7 ms
5 μs
>100 kΩ

44 μV rms

Rev. 0 | Page 3 of 16

SSM2335

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings apply at 25°C, unless otherwise noted.

Table 2.

Parameter Rating

Supply Voltage 6 V
Input Voltage V
Common-Mode Input Voltage V
Continuous Output Power 3 W
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +165°C
Lead Temperature (Soldering, 60 sec) 300°C
ESD Susceptibility 2.5 kV

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

DD

DD

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type PCB θJA θJB Unit

9-Ball, 1.5 mm × 1.5 mm WLCSP 1S0P 162 39 °C/W
2S0P 76 21 °C/W

ESD CAUTION

Rev. 0 | Page 4 of 16

SSM2335

www.BDTIC.com/ADI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

BALL A1
CORNER

A

B

C

SSM2335

TOP VIEW

BALL SIDE DOW N

(Not to Scale)

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1A IN+ Noninverting Input.
1B VDD Power Supply.
1C IN− Inverting Input.
2A GND Ground.
2B PVDD Power Supply.
2C

SD

Shutdown Input. Active low digital input.

3A OUT− Inverting Output.
3B GND Ground.
3C OUT+ Noninverting Output.

321

07551-002

Rev. 0 | Page 5 of 16

SSM2335

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

100

10

RL= 8Ω, 33µH
GAIN = 18dB

f

= 1kHz

IN

VDD = 2.5V

VDD = 3.6V

100

RL = 8Ω, 33µH
GAIN = 18dB
V

10

= 5V

DD

1

0.1

THD + N (%)

0.01

0.001

0.0001 0.001 0.01 0.1 1 10

OUTPUT POW ER (W)

VDD = 5V

Figure 3. THD + N vs. Output Power into 8 Ω + 33 μH, Gain = 18 dB

100

RL= 4Ω, 33µH
GAIN = 18dB

f

= 1kHz

IN

10

1

0.1

THD + N (%)

0.01

0.001

0.0001 0.001 0.01 0.1 1 10

OUTPUT POW ER (W)

VDD = 2.5V

VDD = 3.6V

VDD = 5V

Figure 4. THD + N vs. Output Power into 4 Ω + 33 μH, Gain = 18 dB

100

RL= 3Ω, 33µH
GAIN = 18dB

f

= 1kHz

IN

10

VDD = 2.5V

VDD = 3.6V

1

0.1

THD + N (%)

0.01

0.001

07551-003

10 100 1k 10k 100k

FREQUENCY (Hz)

Figure 6. THD + N vs. Frequency, V

= 5 V, RL = 8 Ω + 33 μH, Gain = 18 dB

DD

0.5W

1W

0.25W

07551-006

100

RL = 4Ω, 33µH
GAIN = 18dB
V

= 5V

DD

10

1

0.1

THD + N (%)

0.01

0.001

07551-004

10 100 1k 10k 100k

FREQUENCY (Hz)

2W

0.5W

1W

07551-007

Figure 7. THD + N vs. Frequency, VDD = 5 V, RL = 4 Ω + 33 μH, Gain = 18 dB

100

RL = 3Ω, 33µH
GAIN = 18dB
V

= 5V

DD

10

1

0.1

THD + N (%)

0.01

0.001

0.0001 0.001 0.01 0.1 1 10

OUTPUT POW ER (W)

VDD = 5V

07551-005

Figure 5. THD + N vs. Output Power into 3 Ω + 33 μH, Gain = 18 dB

Rev. 0 | Page 6 of 16

1

0.1

THD + N (%)

0.01

0.001
10 100 1k 10k 100k

Figure 8. THD + N vs. Frequency, V

3W

FREQUENCY (Hz)

1.5W

0.75W

= 5 V, RL = 3 Ω + 33 μH, Gain = 18 dB

DD

1-008
0755

SSM2335

www.BDTIC.com/ADI

100

RL = 8Ω, 33µH
GAIN = 18dB
V

10

DD

= 3.6V

100

10

RL= 8Ω, 33µH
GAIN = 18dB

= 2.5V

V

DD

1

0.1

THD + N (%)

0.01

0.001
10 100 1k 10k 100k

FREQUENCY (Hz)

0.5W

0.125W

0.25W

Figure 9. THD + N vs. Frequency, VDD = 3.6 V, RL = 8 Ω + 33 μH, Gain = 18 dB

100

RL = 4Ω, 33µH
GAIN = 18dB

= 3.6V

V

DD

10

1

0.1

THD + N (%)

0.01

0.001
10 100 1k 10k 100k

FREQUENCY (Hz)

Figure 10. THD + N vs. Frequency, V

= 3.6 V, RL = 4 Ω + 33 μH, Gain = 18 dB

DD

1W

0.5W

0.25W

100

RL= 3Ω, 33µH
GAIN = 18dB

= 3.6V

V

DD

10

1

0.1

THD + N (%)

0.01

009

07551-

0.001
10 100 1k 10k 100k

Figure 12. THD + N vs. Frequency, V

0.25W

0.0625W

0.125W

FREQUENCY (Hz)

= 2.5 V, RL = 8 Ω + 33 μH, Gain = 18 dB

DD

07551-012

100

RL= 4Ω, 33µH
GAIN = 18dB

= 2.5V

V

DD

10

1

0.1

THD + N (%)

0.01

010

07551-

0.001
10 100 1k 10k 100k

0.5W

FREQUENCY (Hz)

0.125W

0.25W

07551-013

Figure 13. THD + N vs. Frequency, VDD = 2.5 V, RL = 4 Ω + 33 μH, Gain = 18 dB

100

RL = 3Ω, 33µH
GAIN = 18dB

= 2.5V

V

DD

10

1

0.1

THD + N (%)

0.01

0.001
10 100 1k 10k 100k

1.5W

0.75W

0.375W

FREQUENCY (Hz)

07551-011

Figure 11. THD + N vs. Frequency, VDD = 3.6 V, RL = 3 Ω + 33 μH, Gain = 18 dB

Rev. 0 | Page 7 of 16

1

0.75W

0.1

THD + N (%)

0.01

0.001
10 100 1k 10k 100k

0.375W

0.188W

FREQUENCY (Hz)

07551-014

Figure 14. THD + N vs. Frequency, VDD = 2.5 V, RL = 3 Ω + 33 μH, Gain = 18 dB

SSM2335

www.BDTIC.com/ADI

3.8

3.6

3.4

3.2

3.0

2.8

SUPPLY CURRENT (mA)

2.6

2.4

2.2

2.5 3.0 3.5 4. 0 4.5 5.0 5.5 6. 0

= 8Ω, 33µH

R

L

SUPPLY VOLTAGE (V)

RL = 4Ω, 33µH

RL = 3Ω, 33µH

NO LOAD

Figure 15. Supply Current vs. Supply Voltage

2.0
RL = 8Ω, 33µH
GAIN = 18dB

1.8
f = 1kHz

1.6

1.4

1.2

1.0

0.8

OUTPUT POWER (W)

0.6

0.4

0.2

0

2.5 3.0 3.5 4.0 4.5 5.0

10%

1%

SUPPLY VOLTAGE (V)

Figure 16. Maximum Output Power vs. Supply Voltage, RL = 8 Ω + 33 μH,

Gain = 18 dB

4.0
RL = 4Ω, 33µH

GAIN = 18dB

3.5

f = 1kHz

3.0

2.5

2.0

1.5

OUTPUT PO WER (W)

1.0

0.5

0

2.5 3.0 3.5 4.0 4. 5 5. 0

10%

1%

SUPPLY VOLTAGE (V)

Figure 17. Maximum Output Power vs. Supply Voltage, RL = 4 Ω + 33 μH,

Gain = 18 dB

4.5
RL = 3Ω, 33µH

GAIN = 18dB

4.0
f = 1kHz

3.5

3.0

2.5

2.0

1.5

OUTPUT POWER (W)

1.0

0.5

015

07551-

0

2.5 3. 0 3. 5 4. 0 4. 5 5. 0

Figure 18. Maximum Output Power vs. Supply Voltage, R

10%

1%

SUPPLY VOLTAGE (V)

= 3 Ω + 33 μH,

L

07551-018

Gain = 18 dB

100

VDD = 2.5V

90

80

70

60

50

40

EFFICIENCY (%)

30

20

10

16

07551-0

0

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

= 3.6V

V

DD

OUTPUT PO WER (W)

VDD = 5V

RL = 8Ω, 33µH

07551-019

Figure 19. Efficiency vs. Output Power into 8 Ω + 33 μH

100

90

80

70

60

50

40

EFFICIENCY (%)

30

20

10

0

0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6

07551-017

V

DD

VDD = 3.6V

= 2.5V

VDD = 5V

OUTPUT PO WER (W)

RL = 4Ω, 33µH

0

07551-02

Figure 20. Efficiency vs. Output Power into 4 Ω + 33 μH

Rev. 0 | Page 8 of 16

SSM2335

www.BDTIC.com/ADI

0.12
RL = 8Ω, 33µH

V

= 5V

DD

0.10

0.08

0.06

0.04

POWER DISSIPATION ( W)

0.02

0

0 0.3 0.6 0.9 1.2 1.5 1.8

OUTPUT PO WER (W)

Figure 21. Power Dissipation vs. Output Power into 8 Ω + 33 μH, V

0.30
RL = 4Ω, 33µH

= 5V

V

DD

0.25

0.20

0.15

0.10

POWER DISSIPATION (W)

0.05

0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

OUTPUT PO WER (W)

Figure 22. Power Dissipation vs. Output Power into 4 Ω + 33 μH, V

0.08

RL = 8Ω, 33µH

= 3.6V

V

DD

0.06

DD

DD

= 5 V

= 5 V

0.18

= 4Ω, 33µH

R

L

= 3.6V

V

DD

0.16

0.14

0.12

0.10

0.08

0.06

POWER DISS IPATIO N (W)

0.04

0.02

0

1-021
0755

Figure 24. Power Dissipation vs. Output Power into 4 Ω + 33 μH, V

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

OUTPUT PO WER (W)

DD

07551-024

= 3.6 V

450

RL = 8Ω, 33µH

400

350

300

250

200

150

SUPPLY CURRENT (mA)

100

50

0

-022

07551

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

VDD = 2.5V

VDD = 3.6V

OUTPUT PO WER (W)

VDD = 5.0V

07551-025

Figure 25. Supply Current vs. Output Power into 8 Ω + 33 μH

800

RL = 4Ω, 33µH

700

600

500

VDD = 3.6V

VDD = 5.0V

0.04

0.02

POWE R DISSI PATION (W)

0

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

OUTPUT PO WER (W)

Figure 23. Power Dissipation vs. Output Power into 8 Ω + 33 μH, V

= 3.6 V

DD

07551-023

Rev. 0 | Page 9 of 16

400

300

SUPPLY CURRENT (mA)

200

100

VDD = 2.5V

0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

OUTPUT PO WER (W)

Figure 26. Supply Current vs. Output Power into 4 Ω + 33 μH

07551-026

SSM2335

www.BDTIC.com/ADI

0

–10

–20

–30

–40

–50

PSRR (dB)

–60

–70

–80

–90

–100

10 100 1k 10k 100k

FREQUENCY (Hz)

27

07551-0

Figure 27. Power Supply Rejection Ratio (PSRR) vs. Frequency

0

–10

–20

–30

–40

–50

–60

CMRR (dB)

–70

–80

–90

–100

10 100 1k 10k 100k

FREQUENCY (Hz)

07551-028

Figure 28. Common-Mode Rejection Ratio (CMRR) vs. Frequency Figure 30. Turn-Off Response

6

5

4

3

2

VOLTAGE (V)

1

0

–1

–2

–2 20 4 6 8 10 12 14 16 18

SD INPUT

OUTPUT

TIME (ms)

Figure 29. Turn-On Response

7

6

OUTPUT

5

4

3

2

VOLTAGE (V)

1

0

–1

–2

–90 –50–70 –30–101030507090

SD INPUT

TIME (µs)

07551-029

07551-030

Rev. 0 | Page 10 of 16

SSM2335

www.BDTIC.com/ADI

TYPICAL APPLICATION CIRCUITS

EXTERNAL GAIN SETT INGS = 160kΩ/(20k Ω + R

EXT

10µF

)

0.1µF
VBATT

2.5V TO 5.5V

FET

DRIVER

POP-AND-CLICK

SUPPRESSION

GND

VDD

OUT–

OUT+

7551-031

47nF*

SSM2335

R

47nF*

EXT

R

EXT

AUDIO IN+

AUDIO IN–

SHUTDOWN

*INPUT CAPACITORS ARE OPTI ONAL IF INPUT DC COMMON-MODE

VOLTAGE IS APPROXIMATELY V

IN+

IN–

SD

20kΩ

20kΩ

DD

/2.

160kΩ

MODULATOR

(Σ-Δ)

160kΩ

BIAS

INTERNAL

OSCILLATOR

Figure 31. Differential Input Configuration, User-Adjustable Gain

EXTERNAL G AIN SETTINGS = 160kΩ/(20kΩ + R

SSM2335

47nF

AUDIO IN+

47nF

R

EXT

R

EXT

IN+

IN–

20kΩ

20kΩ

)

EXT

10µF

160kΩ

MODULATOR

(Σ-Δ)

160kΩ

0.1µF

DRIVER

FET

VDD

VBATT

2.5V TO 5.5V

OUT–

OUT+

SHUTDOWN

SD

BIAS

INTERNAL

OSCILLATOR

POP-AND-CLICK

SUPPRESSION

GND

7551-032

Figure 32. Single-Ended Input Configuration, User-Adjustable Gain

Rev. 0 | Page 11 of 16

SSM2335

www.BDTIC.com/ADI

THEORY OF OPERATION

OVERVIEW

The SSM2335 mono Class-D audio amplifier features a filterless
modulation scheme that greatly reduces the external component
count, conserving board space and, thus, reducing systems cost.
The SSM2335 does not require an output filter but, instead, relies
on the inherent inductance of the speaker coil and the natural
filtering of the speaker and human ear to fully recover the audio
component of the square wave output. Most Class-D amplifiers
use some variation of pulse-width modulation (PWM), but the
SSM2335 uses Σ-Δ modulation to determine the switching
pattern of the output devices, resulting in a number of important
benefits. Σ-Δ modulators do not produce a sharp peak with many
harmonics in the AM frequency band, as pulse-width modulators
often do. Σ-Δ modulation provides the benefits of reducing the
amplitude of spectral components at high frequencies, that is,
reducing EMI emission that might otherwise be radiated by
speakers and long cable traces. The SSM2335 does not require
external EMI filtering for twisted speaker cable lengths shorter
than 10 cm. Due to the inherent spread-spectrum nature of Σ-Δ
modulation, the need for oscillator synchronization is eliminated
for designs incorporating multiple SSM2335 amplifiers.

The SSM2335 also offers protection circuits for overcurrent and
temperature protection.

GAIN

The SSM2335 has a default gain of 18 dB that can be reduced by
using a pair of external resistors with a value calculated as follows:

External Gain Settings = 160 kΩ/(20 kΩ + R

EXT

)

POP-AND-CLICK SUPPRESSION

Voltage transients at the output of audio amplifiers can occur
when shutdown is activated or deactivated. Voltage transients
as low as 10 mV can be heard as an audio pop in the speaker.
Clicks and pops can also be classified as undesirable audible
transients generated by the amplifier system and, therefore, as
not coming from the system input signal. Such transients may
be generated when the amplifier system changes its operating
mode. For example, the following may be sources of audible
transients: system power-up and power-down, mute and unmute,
input source change, and sample rate change. The SSM2335 has
a pop-and-click suppression architecture that reduces these out­put transients, resulting in noiseless activation and deactivation.

OUTPUT MODULATION DESCRIPTION

The SSM2335 uses three-level, Σ-Δ output modulation. Each
output can swing from GND to V
no input signal is present, the output differential voltage is 0 V
because there is no need to generate a pulse. In a real-world
situation, there are always noise sources present.

Due to this constant presence of noise, a differential pulse is
generated, when required, in response to this stimulus. A small
amount of current flows into the inductive load when the differ­ential pulse is generated.

Most of the time, however, output differential voltage is 0 V, due
to the Analog Devices patent pending, three-level, Σ-Δ output
modulation. This feature ensures that the current flowing through
the inductive load is small.

When the user wants to send an input signal, an output pulse is
generated to follow the input voltage. The differential pulse
density is increased by raising the input signal level. Figure 33
depicts three-level, Σ-Δ output modulation with and without
input stimulus.

OUTPUT = 0V

OUT+

OUT–

VOUT

OUTPUT > 0V

OUT+

OUT–

VOUT

OUTPUT < 0V

OUT+

OUT–

VOUT

Figure 33. Three-Level, Σ-Δ Output Modulation With and Without Input Stimulus

and vice versa. Ideally, when

DD

+5V

0V

+5V

0V
+5V

0V

–5V

+5V

0V

+5V

0V

+5V

0V

+5V

0V

+5V

0V

0V

–5V

07551-033

Rev. 0 | Page 12 of 16

SSM2335

www.BDTIC.com/ADI

LAYOUT

As output power continues to increase, care must be taken to
lay out PCB traces and wires properly among the amplifier,
load, and power supply. A good practice is to use short, wide
PCB tracks to decrease voltage drops and minimize inductance.
Ensure that track widths are at least 200 mil for every inch of
track length for lowest DCR, and use 1 oz or 2 oz of copper PCB
traces to further reduce IR drops and inductance. A poor layout
increases voltage drops, consequently affecting efficiency. Use
large traces for the power supply inputs and amplifier outputs to
minimize losses due to parasitic trace resistance.

Proper grounding guidelines help to improve audio performance,
minimize crosstalk between channels, and prevent switching
noise from coupling into the audio signal. To maintain high
output swing and high peak output power, the PCB traces that
connect the output pins to the load, as well as the PCB traces to
the supply pins, should be as wide as possible to maintain the
minimum trace resistances. It is also recommended that a large
ground plane be used for minimum impedances.

In addition, good PCB layout isolates critical analog paths from
sources of high interference. High frequency circuits (analog
and digital) should be separated from low frequency circuits.

Properly designed multilayer PCBs can reduce EMI emission
and increase immunity to the RF field by a factor of 10 or more,
compared with double-sided boards. A multilayer board allows
a complete layer to be used for the ground plane, whereas the
ground plane side of a double-sided board is often disrupted by
signal crossover.

If the system has separate analog and digital ground and power
planes, the analog ground plane should be directly beneath the
analog power plane, and, similarly, the digital ground plane should
be directly beneath the digital power plane. There should be no
overlap between analog and digital ground planes or between
analog and digital power planes.

INPUT CAPACITOR SELECTION

The SSM2335 does not require input coupling capacitors if the
input signal is biased from 1.0 V to V
are required if the input signal is not biased within this recom­mended input dc common-mode voltage range, if high-pass
filtering is needed, or if a single-ended source is used. If high­pass filtering is needed at the input, the input capacitor and the
input resistor of the SSM2335 form a high-pass filter whose
corner frequency is determined by the following equation:

f

= 1/(2π × RIN × CIN)

C

The input capacitor can significantly affect the performance of
the circuit. Not using input capacitors degrades both the output
offset of the amplifier and the dc PSRR performance.

− 1.0 V. Input capacitors

DD

POWER SUPPLY DECOUPLING

To ensure high efficiency, low total harmonic distortion (THD),
and high PSRR, proper power supply decoupling is necessary.
Noise transients on the power supply lines are short-duration
voltage spikes. Although the actual switching frequency can range
from 10 kHz to 100 kHz, these spikes can contain frequency
components that extend into the hundreds of megahertz. The
power supply input needs to be decoupled with a good quality,
low ESL, low ESR capacitor, with a minimum value of 4.7 μF.
This capacitor bypasses low frequency noises to the ground
plane. For high frequency transient noises, use a 0.1 μF capacitor
as close as possible to the VDD pin of the device. Placing the
decoupling capacitor as close as possible to the SSM2335 helps
to maintain efficient performance.

Rev. 0 | Page 13 of 16

SSM2335

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

0.655

0.600

0.545

SEATING
PLANE

0.350

0.320

0.290

123

A

B

A1 BALL

CORNER

1.490

1.460 SQ

1.430

C

C

101507-

TOP VIEW

(BALL SI DE DOWN)

0.385

0.360

0.335

0.50
BALL PI TCH

0.270

0.240

0.210

BOTTOM VIEW

(BALL SIDE UP)

Figure 34. 9-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-9-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

SSM2335CBZ-R2
SSM2335CBZ-REEL
SSM2335CBZ-REEL7
EVAL-SSM2335Z

1

Z = RoHS Compliant Part.

1

1

Evaluation Board

−40°C to +85°C 9-Ball Wafer Level Chip Scale Package [WLCSP] CB-9-2 Y1L

1

−40°C to +85°C 9-Ball Wafer Level Chip Scale Package [WLCSP] CB-9-2 Y1L

1

−40°C to +85°C 9-Ball Wafer Level Chip Scale Package [WLCSP] CB-9-2 Y1L

Rev. 0 | Page 14 of 16

SSM2335

www.BDTIC.com/ADI

NOTES

Rev. 0 | Page 15 of 16

SSM2335

www.BDTIC.com/ADI

NOTES

©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07551-0-10/08(0)

Rev. 0 | Page 16 of 16