Page 1
Filterless, High Efficiency,
www.BDTIC.com/ADI
FEATURES
Filterless Class-D amplifier with Σ-Δ modulation
No sync necessary when using multiple Class-D amplifiers
from Analog Devices, Inc.
3 W into 3 Ω load and 1.4 W into 8 Ω load at 5.0 V supply
with <1% total harmonic distortion (THD + N)
93% efficiency at 5.0 V, 1.4 W into 8 Ω speaker
>103 dB signal-to-noise ratio (SNR)
Single-supply operation from 2.5 V to 5.5 V
20 nA ultralow shutdown current
Short-circuit and thermal protection
Available in 9-ball, 1.5 mm × 1.5 mm WLCSP
Pop-and-click suppression
Built-in resistors reduce board component count
Default fixed 6 dB or user adjustable gain setting
APPLICATIONS
Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys
GENERAL DESCRIPTION
The SSM2315 is a fully integrated, high efficiency, Class-D audio
amplifier. It is designed to maximize performance for mobile
phone applications. The application circuit requires a minimum
of external components and operates from a single 2.5 V to 5.5 V
supply. It is capable of delivering 3 W of continuous output power
with <1% THD + N driving a 3 Ω load from a 5.0 V supply.
FUNCTIONAL BLOCK DIAGRAM
Mono 3 W Class-D Audio Amplifier
SSM2315
The SSM2315 features a high efficiency, low noise modulation
scheme that requires no external LC output filters. The modulation
continues to provide high efficiency even at low output power.
It operates with 93% efficiency at 1.4 W into 8 Ω or 85% efficiency
at 3 W into 3 Ω from a 5.0 V supply and has an SNR of >103 dB.
Spread-spectrum pulse density modulation is used to provide
lower EMI-radiated emissions compared with other Class-D
architectures.
The SSM2315 has a micropower shutdown mode with a typical
shutdown current of 20 nA. Shutdown is enabled by applying
SD
pin.
/2.
DD
VBATT
2.5V TO 5.5V
10µF
a logic low to the
The device also includes pop-and-click suppression circuitry.
This suppression circuitry minimizes voltage glitches at the
output during turn-on and turn-off, reducing audible noise
on activation and deactivation.
The fully differential input of the SSM2315 provides excellent
rejection of common-mode noise on the input. Input coupling
capacitors can be omitted if the dc input common-mode voltage
is approximately V
The default gain of the SSM2315 is 6 dB, but users can reduce the
gain by using a pair of external resistors (see the Gain section).
The SSM2315 is specified over the industrial temperature range of
−40°C to +85°C. It has built-in thermal shutdown and output
short-circuit protection. It is available in a 9-ball, 1.5 mm × 1.5 mm
wafer level chip scale package (WLCSP).
0.1µF
SSM2315
AUDIO IN+
AUDIO IN–
SHUTDOWN
*INPUT CAPS ARE OPTI ONAL IF I NPUT DC COMMO N-MODE
VOLTAGE IS APPROXIMATELY V
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
47nF*
47nF*
IN+
IN–
SD
80kΩ
80kΩ
/2.
DD
MODULATOR
BIAS
FET
DRIVER
GND
VDD
OUT+
OUT–
POP/CLICK
SUPPRESSION
6857-001
160kΩ
(Σ-Δ)
160kΩ
INTERNAL
OSCILLATOR
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
Page 2
SSM2315
www.BDTIC.com/ADI
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Application Circuits ......................................................... 11
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Typical Performance Characteristics ............................................. 6
REVISION HISTORY
8/08—Rev. 0 to Rev. A
Changes to Efficiency and Total Harmonic
Distortion + Noise Parameters ....................................................... 3
Changes to Ordering Guide .......................................................... 14
2/08—Revision 0: Initial Version
Theory of Operation ...................................................................... 12
Overview ..................................................................................... 12
Gain .............................................................................................. 12
Pop-and-Click Suppression ...................................................... 12
Output Modulation Description .............................................. 12
Layout .......................................................................................... 13
Input Capacitor Selection .......................................................... 13
Proper Power Supply Decoupling ............................................ 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
Rev. A | Page 2 of 16
Page 3
SSM2315
www.BDTIC.com/ADI
SPECIFICATIONS
VDD = 5.0 V, TA = 25oC, RL = 8 Ω + 33 μH, unless otherwise noted.
Table 1.
Parameter Symbol Conditions1 Min Typ Max Unit
DEVICE CHARACTERISTICS
Output Power P
O
R
R
R
R
R
R
R
R
R
R
R
Efficiency η PO = 1.4 W, RL = 8 Ω + 33 μH, VDD = 5.0 V 93 %
Total Harmonic Distortion + Noise THD + N PO = 1 W, RL = 8 Ω + 33 μH, f = 1 kHz, VDD = 5.0 V 0.004 %
P
Input Common-Mode Voltage Range VCM 1.0 VDD − 1.0 V
Common-Mode Rejection Ratio CMRR
Average Switching Frequency fSW 280 kHz
Differential Output Offset Voltage V
OOS
POWER SUPPLY
Supply Voltage Range V
DD
Power Supply Rejection Ratio PSRR VDD = 2.5 V to 5.0 V, dc input floating 70 85 dB
PSRR
Supply Current I
SY
V
V
Shutdown Current ISD
GAIN CONTROL
Closed-Loop Gain Gain 6 dB
Differential Input Impedance Z
IN
SHUTDOWN CONTROL
Input Voltage High V
Input Voltage Low V
Turn-On Time t
Turn-Off Time t
Output Impedance Z
WU
SD
IH
IL
OUT
NOISE PERFORMANCE
Output Voltage Noise en V
Signal-to-Noise Ratio SNR PO = 1.4 W, RL = 8 Ω 103 dB
1
Note that although the SSM2315 has good audio quality above 3 W, continuous output power beyond 3 W must be avoided due to device packaging limitations.
2
This value represents measured performance; packaging limitations must not be exceeded.
RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 1.48 W
= 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 0.75 W
L
= 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 1.84 W
L
= 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 0.94 W
L
= 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 2.72 W
L
= 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 1.38 W
L
= 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 3.402 W
L
= 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 1.72 W
L
= 3 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 3.43 W
L
= 3 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 1.72 W
GSM VCM
L
= 3 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V
L
= 3 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 2.14 W
L
= 0.5 W, RL = 8 Ω + 33 μH, f = 1 kHz, VDD = 3.6 V 0.004 %
O
= 2.5 V ± 100 mV at 217 Hz, output referred 55 dB
4.28
2
Gain = 6 dB 2.0 mV
Guaranteed from PSRR test 2.5 5.5 V
GSM VRIPPLE
= 100 mV at 217 Hz, inputs ac GND, CIN = 0.1 μF 60 dB
VIN = 0 V, no load, VDD = 5.0 V 3.2 mA
= 0 V, no load, VDD = 3.6 V 2.8 mA
IN
= 0 V, no load, VDD = 2.5 V 2.4 mA
IN
V
= 0 V, load = 8 Ω+ 33 μH, VDD = 5.0 V
IN
V
= 0 V, load = 8 Ω+ 33 μH, VDD = 3.6 V
IN
V
= 0 V, load = 8 Ω+ 33 μH, VDD = 2.5 V
IN
SD
= GND
SD
= VDD
3.3 mA
2.9 mA
2.4 mA
20 nA
80 kΩ
ISY ≥ 1 mA 1.2 V
ISY ≤ 300 nA 0.5 V
SD
rising edge from GND to VDD
SD
falling edge from VDD to GND
SD
= GND
= 3.6 V, f = 20 Hz to 20 kHz, inputs are ac-grounded,
DD
7 ms
5 μs
>100 kΩ
21 μV rms
gain = 6 dB, A-weighted
W
Rev. A | Page 3 of 16
Page 4
SSM2315
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
Table 2.
Parameter Rating
Supply Voltage 6 V
Input Voltage V
Common-Mode Input Voltage V
Continuous Output Power 3 W
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +165°C
Lead Temperature (Soldering, 60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
DD
DD
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type PCB θJA θJB Unit
9-ball, 1.5 mm × 1.5 mm WLCSP 1S0P 162 39 °C/W
2S0P 76 21 °C/W
ESD CAUTION
Rev. A | Page 4 of 16
Page 5
SSM2315
www.BDTIC.com/ADI
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BALL A1
CORNER
A
B
C
SSM2315
TOP VIEW
BALL SIDE DOW N
(Not to Scale)
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
2C
2A GND Ground.
1A IN+ Noninverting Input.
1C IN− Inverting Input.
3C OUT+ Noninverting Output.
1B VDD Power Supply.
3B GND Ground.
3A OUT− Inverting Output.
2B PVDD Power Supply.
SD
Shutdown Input. Active low digital input.
321
06857-002
Rev. A | Page 5 of 16
Page 6
SSM2315
www.BDTIC.com/ADI
TYPICAL PERFORMANCE CHARACTERISTICS
100
RL = 8Ω + 33µH
GAIN = 6dB
10
V
= 3.6V
DD
V
= 2.5V
DD
100
10
VDD = 5V
GAIN = 6dB
= 8Ω + 33µH
R
L
1
0.1
THD + N (%)
= 5V
V
0.01
0.001
0.0001 0.001 0.01 0.1 1 10
OUTPUT POWER (W)
DD
Figure 3. THD + N vs. Output Power, RL = 8 Ω + 33 μH, Gain = 6 dB
100
RL = 4Ω + 33µH
GAIN = 6dB
V
= 2.5V
10
1
0.1
THD + N (%)
0.01
0.001
0.0001 0.001 0.01 0.1 1 10
OUTPUT POWER (W)
DD
= 3.6V
V
DD
= 5V
V
DD
Figure 4. THD + N vs. Output Power, RL = 4 Ω + 33 μH, Gain = 6 dB
1
0.1
THD + N (%)
0.01
0.001
0.0001
10 100 1k 10k 100k
06857-003
FREQUENCY (Hz)
0.25W
0.5W
1W
06857-006
Figure 6. THD + N vs. Frequency, VDD = 5 V, RL = 8 Ω + 33 μH, Gain = 6 dB
100
VDD = 5V
GAIN = 6dB
= 4Ω + 33µH
R
L
10
1
0.1
THD + N (%)
0.01
0.001
0.0001
10 100 1k 10k 100k
06857-004
FREQUENCY (Hz)
0.5W
1W
2W
06857-007
Figure 7. THD + N vs. Frequency, VDD = 5 V, RL = 4 Ω + 33 μH, Gain = 6 dB
100
RL = 3Ω + 33µH
GAIN = 6dB
V
= 2.5V
10
1
0.1
THD + N (%)
0.01
0.001
0.0001 0.001 0.01 0.1 1 10
OUTPUT POWER (W)
DD
V
DD
V
= 3.6V
= 5V
DD
06857-005
Figure 5. THD + N vs. Output Power, RL = 3 Ω + 33 μH, Gain = 6 dB
Rev. A | Page 6 of 16
100
VDD = 5V
GAIN = 6dB
= 3Ω + 33µH
R
L
10
1
0.1
THD + N (%)
0.01
0.001
0.0001
10 100 1k 10k 100k
FREQUENCY (Hz)
3W
0.5W
0.75W
Figure 8. THD + N vs. Frequency, VDD = 5 V, RL = 3 Ω + 33 μH, Gain = 6 dB
06857-008
Page 7
SSM2315
www.BDTIC.com/ADI
100
10
VDD = 3.6V
GAIN = 6dB
= 8Ω + 33µH
R
L
100
10
VDD = 2.5V
GAIN = 6dB
= 8Ω + 33µH
R
L
1
0.1
THD + N (%)
0.01
0.001
10 100 1k 10k 100k
0.5W
FREQUENCY (Hz)
0.125W
0.25W
06857-009
Figure 9. THD + N vs. Frequency, VDD = 3.6 V, RL = 8 Ω + 33 μH, Gain = 6 dB
100
VDD = 3.6V
GAIN = 6dB
= 4Ω + 33µH
R
L
10
1
0.1
THD + N (%)
0.01
0.001
10 100 1k 10k 100k
0.5W
0.25W
FREQUENCY (Hz)
1W
06857-010
Figure 10. THD + N vs. Frequency, VDD = 3.6 V, RL = 4 Ω + 33 μH, Gain = 6 dB
1
0.1
THD + N (%)
0.01
0.001
10 100 1k 10k 100k
0.25W
FREQUENCY (Hz)
0.125W0.63W
06857-012
Figure 12. THD + N vs. Frequency, VDD = 2.5 V, RL = 8 Ω + 33 μH, Gain = 6 dB
100
VDD = 2.5V
GAIN = 6dB
= 4Ω + 33µH
R
L
10
1
0.5W
0.1
THD + N (%)
0.01
0.001
10 100 1k 10k 100k
0.25W
0.125W
FREQUENCY (Hz)
06857-013
Figure 13. THD + N vs. Frequency, VDD = 2.5 V, RL = 4 Ω + 33 μH, Gain = 6 dB
100
VDD = 3.6V
GAIN = 6dB
= 3Ω + 33µH
R
L
10
1
0.1
THD + N (%)
0.75W
0.01
0.001
10 100 1k 10k 100k
FREQUENCY (Hz)
1.5W
0.38W
06857-011
Figure 11. THD + N vs. Frequency, VDD = 3.6 V, RL = 3 Ω + 33 μH, Gain = 6 dB
Rev. A | Page 7 of 16
100
VDD = 2.5V
GAIN = 6dB
= 3Ω + 33µH
R
L
10
1
0.1
THD + N (%)
0.01
0.001
10 100 1k 10k 100k
FREQUENCY (Hz)
0.75W
0.375W
0.188W
06857-014
Figure 14. THD + N vs. Frequency, VDD = 2.5 V, RL = 3 Ω + 33 μH, Gain = 6 dB
Page 8
SSM2315
www.BDTIC.com/ADI
4.1
3.9
3.7
3.5
3.3
3.1
SUPPLY CURRENT (mA)
2.9
2.7
2.5
2.5 3.0 3. 5 4.0 4.5 5.0 5.5 6.0
RL = 3Ω + 33µH
R
= 4Ω + 33µH
L
SUPPLY VOLTAGE (V)
NO LOAD
Figure 15. Supply Current vs. Supply Voltage
06857-015
4.5
FREQUENCY = 1kHz
GAIN = 6dB
4.0
= 3Ω + 33µH
R
L
3.5
3.0
2.5
2.0
1.5
OUTPUT POWER (W)
1.0
0.5
0
2.5 3.0 3.5 4.0 4.5 5.0
DO NOT EXCE ED 3W
CONTINUO US OUTPUT POWER
SUPPLY VOLTAGE (V)
10%
1%
Figure 18. Maximum Output Power vs. Supply Voltage,
= 3 Ω + 33 μH, Gain = 6 dB
R
L
06857-018
2.0
FREQUENCY = 1kHz
GAIN = 6dB
1.8
= 8Ω + 33µH
R
L
1.6
1.4
1.2
1.0
0.8
OUTPUT POWER (W)
0.6
0.4
0.2
0
2.5 3.0 3.5 4.0 4.5 5.0
10%
1%
SUPPLY VOLTAGE (V)
Figure 16. Maximum Output Power vs. Supply Voltage,
= 8 Ω + 33 μH, Gain = 6 dB
R
L
4.0
FREQUENCY = 1kHz
GAIN = 6dB
3.5
= 4Ω + 33µH
R
L
3.0
2.5
2.0
1.5
OUTPUT POWER (W)
1.0
0.5
0
DO NOT EXC EED 3W CONT INUOUS O UTPUT POWER
10%
1%
2.5 3.0 3.5 4.0 4.5 5.0
SUPPLY VOLTAGE (V)
Figure 17. Maximum Output Power vs. Supply Voltage,
= 4 Ω + 33 μH, Gain = 6 dB
R
L
100
V
= 2.5V
DD
90
80
70
60
50
40
EFFICIE NCY (%)
30
20
10
0
01.81.61.41.21.00.80.60.40.2
06857-016
= 3.6V
V
DD
OUTPUT POWER (W)
= 5V
V
DD
RL = 8Ω + 33µH
06857-019
Figure 19. Efficiency vs. Output Power, RL = 8 Ω + 33 μH
100
90
80
70
60
50
40
EFFICIE NCY (%)
30
20
10
0
03.23.02.82.62.42.22.01.81.61.41.21.00.80.60.40.2
06857-017
V
= 2.5V VDD = 3.6V VDD = 5V
DD
OUTPUT POWER (W)
RL = 4Ω + 33µH
06857-020
Figure 20. Efficiency vs. Output Power, RL = 4 Ω + 33 μH
Rev. A | Page 8 of 16
Page 9
SSM2315
www.BDTIC.com/ADI
0.16
0.14
0.12
VDD = 5V
= 8Ω + 33µH
R
L
0.25
0.20
VDD = 3.6V
= 4Ω + 33µH
R
L
0.10
0.08
0.06
POWER DISSIPATIO N (W)
0.04
0.02
0
01.81.61.41.21.00.80.60.40.2
OUTPUT POWER (W)
Figure 21. Power Dissipation vs. Output Power, R
0.40
VDD = 5V
= 4Ω + 33µH
R
L
0.35
0.30
0.25
0.20
0.15
POWER DISSIPATIO N (W)
0.10
0.05
= 8 Ω + 33 μH at VDD = 5.0 V
L
0.15
0.10
POWER DISSIPATIO N (W)
0.05
0
01.61.41.21.00.80.60.40.2
06857-021
OUTPUT POWER (W)
06857-024
Figure 24. Power Dissipation vs. Output Power, RL = 4 Ω + 33 μH at VDD = 3.6 V
400
350
300
250
200
150
SUPPLY CURRENT (mA)
100
50
RL = 8Ω + 33µH
VDD = 2.5V
V
DD
= 3.6V
= 5V
V
DD
0
03.02.52.01.51.00.5
OUTPUT POWER (W)
Figure 22. Power Dissipation vs. Output Power, R
0.09
VDD = 3.6V
= 8Ω + 33µH
R
L
0.08
0.07
0.06
0.05
0.04
0.03
POWER DISSIPATIO N (W)
0.02
0.01
0
00.90.70.5 0.80.60.40.30.20.1
OUTPUT POWER (W)
Figure 23. Power Dissipation vs. Output Power, R
= 4 Ω + 33 μH at VDD = 5.0 V
L
= 8 Ω + 33 μH at VDD = 3.6 V
L
0
01.81.61.41.21.00.80.60.40.2
06857-022
OUTPUT POWER (W)
06857-025
Figure 25. Supply Current vs. Output Power, RL = 8 Ω + 33 μH
800
RL = 4Ω + 33µH
700
600
500
400
300
SUPPLY CURRENT (mA)
200
100
06857-023
0
03.02.82.62.42.22.01.81.61.41.21.00.80.60.40.2
V
DD
= 2.5V
= 3.6V
V
DD
OUTPUT POWER (W)
= 5V
V
DD
06857-026
Figure 26. Supply Current vs. Output Power, RL = 4 Ω + 33 μH
Rev. A | Page 9 of 16
Page 10
SSM2315
www.BDTIC.com/ADI
0
–10
–20
–30
–40
–50
PSRR (dB)
–60
–70
–80
–90
–100
10 100k10k1k100
FREQUENCY (Hz)
Figure 27. Power Supply Rejection Ratio (PSRR) vs. Frequency
06857-027
8
7
6
–2 20181614121086420
SD INPUT
OUTPUT
TIME (ms)
06857-029
5
4
3
2
VOLTAGE (V)
1
0
–1
–2
Figure 29. Turn-On Response
0
–10
–20
–30
–40
–50
CMRR (dB)
–60
–70
–80
–90
–100
10 100k10k1k100
FREQUENCY (Hz)
Figure 28. Common-Mode Rejection Ratio (CMRR) vs. Frequency
8
7
6
5
4
3
2
VOLTAGE (V)
1
0
–1
–2
–90 9070503010–10–30–50–70
06857-028
TIME (µs)
OUTPUT
SD INPUT
06857-030
Figure 30. Turn-Off Response
Rev. A | Page 10 of 16
Page 11
SSM2315
A
A
www.BDTIC.com/ADI
TYPICAL APPLICATION CIRCUITS
EXTERNAL GAIN SETT INGS = 160kΩ/(80k Ω + R
EXT
10µF
)
0.1µF
VBATT
2.5V TO 5.5V
FET
DRIVER
GND
VDD
OUT+
OUT–
POP/CLICK
SUPPRESSION
6857-031
47nF*
SSM2315
R
47nF*
EXT
R
EXT
UDIO IN+
UDIO IN–
SHUTDOWN
*INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MO DE
VOLTAGE IS APPROXIMATELY V
IN+
IN–
SD
80kΩ
80kΩ
DD
MODULATOR
BIAS
/2.
160kΩ
(Σ-Δ)
160kΩ
INTERNAL
OSCILLATOR
Figure 31. Differential Input Configuration, User-Adjustable Gain
EXTERNAL G AIN SETTINGS = 160kΩ/(80kΩ + R
SSM2315
47nF
AUDIO IN+
47nF
R
EXT
R
EXT
IN+
IN–
80kΩ
80kΩ
)
EXT
10µF
160kΩ
MODULATOR
(Σ-Δ)
160kΩ
0.1µF
DRIVER
FET
VDD
VBATT
2.5V TO 5.5V
OUT+
OUT–
SHUTDOWN
SD
BIAS
INTERNAL
OSCILLATOR
POP/CLICK
SUPPRESSION
GND
6857-032
Figure 32. Single-Ended Input Configuration, User-Adjustable Gain
Rev. A | Page 11 of 16
Page 12
SSM2315
www.BDTIC.com/ADI
THEORY OF OPERATION
OVERVIEW
The SSM2315 mono Class-D audio amplifier features a filterless
modulation scheme that greatly reduces the external component
count, conserving board space and, thus, reducing systems cost.
The SSM2315 does not require an output filter but, instead, relies
on the inherent inductance of the speaker coil and the natural
filtering of the speaker and human ear to fully recover the audio
component of the square wave output. Most Class-D amplifiers
use some variation of pulse-width modulation (PWM), but the
SSM2315 uses a Σ-Δ modulation to determine the switching
pattern of the output devices, resulting in a number of important
benefits. Σ-Δ modulators do not produce a sharp peak with many
harmonics in the AM frequency band, as pulse-width modulators
often do. Σ-Δ modulation provides the benefits of reducing the
amplitude of spectral components at high frequencies, that is,
reducing EMI emission that may otherwise be radiated by
speakers and long cable traces. The SSM2315 does not require
external EMI filtering for twisted speaker cable lengths shorter
than 10 cm. Due to the inherent spread spectrum nature of Σ-Δ
modulation, the need for oscillator synchronization is eliminated
for designs incorporating multiple SSM2315 amplifiers.
OUTPUT MODULATION DESCRIPTION
The SSM2315 uses three-level, Σ-Δ output modulation. Each
output can swing from GND to VDD and vice versa. Ideally,
when no input signal is present, the output differential voltage
is 0 V because there is no need to generate a pulse. In a real world
situation, there are always noise sources present.
Due to this constant presence of noise, a differential pulse is
generated, when required, in response to this stimulus. A small
amount of current flows into the inductive load when the differential pulse is generated.
However, most of the time, output differential voltage is 0 V,
due to the Analog Devices patented, three-level, Σ-Δ output
modulation. This feature ensures that the current flowing through
the inductive load is small.
When the user wants to send an input signal, an output pulse
is generated to follow the input voltage. The differential pulse
density is increased by raising the input signal level. Figure 33
depicts three-level, Σ-Δ output modulation with and without
input stimulus.
The SSM2315 also offers protection circuits for overcurrent and
temperature protection.
GAIN
The SSM2315 has a default gain of 6 dB that can be reduced by
using a pair of external resistors with a value calculated as follows:
External Gain Settings = 160 kΩ/(80 kΩ + R
EXT
)
POP-AND-CLICK SUPPRESSION
Voltage transients at the output of audio amplifiers may occur
when shutdown is activated or deactivated. Voltage transients as
low as 10 mV can be heard as an audio pop in the speaker. Clicks
and pops can also be classified as undesirable audible transients
generated by the amplifier system and, therefore, as not coming
from the system input signal. Such transients may be generated
when the amplifier system changes its operating mode. For example,
the following may be sources of audible transients: system power-up
and power-down, mute and unmute, input source change, and
sample rate change. The SSM2315 has a pop-and-click suppression
architecture that reduces these output transients, resulting in
noiseless activation and deactivation.
OUTPUT = 0V
OUT+
OUT–
VOUT
OUTPUT > 0V
OUT+
OUT–
VOUT
OUTPUT < 0V
OUT+
OUT–
VOUT
Figu re 33. Three-L evel, Σ-Δ Output Modulation With and Without Input Stimulus
+5V
0V
+5V
0V
+5V
0V
–5V
+5V
0V
+5V
0V
+5V
0V
+5V
0V
+5V
0V
0V
–5V
06857-033
Rev. A | Page 12 of 16
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SSM2315
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LAYOUT
As output power continues to increase, care must be taken to lay
out PCB traces and wires properly among the amplifier, load,
and power supply. A good practice is to use short, wide PCB
tracks to decrease voltage drops and to minimize inductance.
Ensure that track widths are at least 200 mil for every inch of track
length for lowest DCR, and use 1 oz or 2 oz of copper PCB traces
to further reduce IR drops and inductance. A poor layout increases
voltage drops, consequently affecting efficiency. Use large traces
for the power supply inputs and amplifier outputs to minimize
losses due to parasitic trace resistance.
Proper grounding guidelines help improve audio performance,
minimize crosstalk between channels, and prevent switching noise
from coupling into the audio signal. To maintain high output swing
and high peak output power, the PCB traces that connect the
output pins to the load and supply pins should be as wide as
possible to maintain the minimum trace resistances. It is also
recommended that a large ground plane be used for minimum
impedances.
In addition, good PCB layouts isolate critical analog paths from
sources of high interference. High frequency circuits (analog
and digital) should be separated from low frequency circuits.
Properly designed multilayer printed circuit boards can reduce
EMI emission and increase immunity to the RF field by a factor
of 10 or more, compared with double-sided boards. A multilayer
board allows a complete layer to be used for the ground plane,
whereas the ground plane side of a double-sided board is often
disrupted with signal crossover.
If the system has separate analog and digital ground and power
planes, the analog ground plane should be underneath the analog
power plane. Similarly, the digital ground plane should be
underneath the digital power plane. There should be no overlap
between analog and digital ground planes or analog and digital
power planes.
INPUT CAPACITOR SELECTION
The SSM2315 does not require input coupling capacitors if the
input signal is biased from 1.0 V to V
required if the input signal is not biased within this recommended
input dc common-mode voltage range, if high-pass filtering is
needed, or if a single-ended source is used. If high-pass filtering
is needed at the input, the input capacitor and the input resistor
of the SSM2315 form a high-pass filter whose corner frequency
is determined by the following equation:
f
= 1/(2π × RIN × CIN)
C
The input capacitor can significantly affect the performance of
the circuit. Not using input capacitors degrades both the output
offset of the amplifier and the dc PSRR performance.
− 1.0 V. Input capacitors are
DD
PROPER POWER SUPPLY DECOUPLING
To ensure high efficiency, low total harmonic distortion (THD),
and high PSRR, proper power supply decoupling is necessary.
Noise transients on the power supply lines are short-duration
voltage spikes. Although the actual switching frequency can range
from 10 kHz to 100 kHz, these spikes can contain frequency
components that extend into the hundreds of megahertz. The
power supply input needs to be decoupled with a good quality,
low ESL, low ESR capacitor, usually of around 4.7 μF. This capacitor
bypasses low frequency noises to the ground plane. For high
frequency transients noises, use a 0.1 μF capacitor as close as
possible to the VDD pin of the device. Placing the decoupling
capacitor as close as possible to the SSM2315 helps maintain
efficient performance.
Rev. A | Page 13 of 16
Page 14
SSM2315
www.BDTIC.com/ADI
OUTLINE DIMENSIONS
0.655
0.600
0.545
SEATING
PLANE
0.350
0.320
0.290
123
A
B
A1 BALL
CORNER
1.490
1.460 SQ
1.430
C
101507-C
TOP VIEW
(BALL SI DE DOWN)
0.385
0.360
0.335
0.50
BALL PI TCH
0.270
0.240
0.210
BOTTOM VIEW
(BALL SIDE UP)
Figure 34. 9-Ball Wafer Level Chip Scale Package [WLCSP]
(CP-9-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
SSM2315CBZ-R21 −40°C to +85°C 9-Ball Wafer Level Chip Scale Package [WLCSP] CB-9-2 Y0P
SSM2315CBZ-REEL1 −40°C to +85°C 9-Ball Wafer Level Chip Scale Package [WLCSP] CB-9-2 Y0P
SSM2315CBZ-REEL71 −40°C to +85°C 9-Ball Wafer Level Chip Scale Package [WLCSP] CB-9-2 Y0P
SSM2315-EVALZ1 Evaluation Board
1
Z = RoHS Compliant Part.
Rev. A | Page 14 of 16
Page 15
SSM2315
www.BDTIC.com/ADI
NOTES
Rev. A | Page 15 of 16
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SSM2315
www.BDTIC.com/ADI
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06857-0-8/08(A)
Rev. A | Page 16 of 16
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