Datasheet ssm2305 Datasheet (ANALOG DEVICES)

Filterless High Efficiency

*

V

Mono 2.8 W Class-D Audio Amplifier

FEATURES

Filterless Class-D amplifier with Σ-Δ modulation
No sync necessary when using multiple Class-D amplifiers

from Analog Devices, Inc.

2.8 W into 4 Ω load and 1.6 W into 8 Ω load at 5.0 V supply
with <10% total harmonic distortion (THD)

89% efficiency at 5.0 V, 1.3 W into 8 Ω speaker
>98 dB signal-to-noise ratio (SNR)
Single-supply operation from 2.5 V to 5.5 V
20 nA ultralow shutdown current
Short-circuit and thermal protection
Available in 8-lead, 3 mm × 3 mm LFCSP and MSOP
Pop-and-click suppression
Built-in resistors reduce board component count
Fixed and user-adjustable gain configurations

APPLICATIONS

Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys

GENERAL DESCRIPTION

The SSM2305 is a fully integrated, high efficiency, Class-D
audio amplifier designed to maximize performance for mobile
phone applications. The application circuit requires a minimum
of external components and operates from a single 2.5 V to 5.5 V
supply. It is capable of delivering 2.2 W of continuous output
power with less than 1% THD + N driving a 4 Ω load from a

5.0 V supply. It has built-in thermal shutdown and output short-

circuit protection.

SSM2305

The SSM2305 features a high efficiency, low noise modulation
scheme that does not require external LC output filters. The modu­lation provides high efficiency even at low output power. The
SSM2305 operates with 90% efficiency at 1.3 W into 8 Ω or 83%
efficiency at 2.2 W into 4 Ω from a 5.0 V supply and has an SNR of
>98 dB. Spread-spectrum pulse density modulation is used to
provide lower EMI-radiated emissions compared with other
Class-D architectures.

The SSM2305 has a micropower shutdown mode with a maximum
shutdown current of 30 nA. Shutdown is enabled by applying
a Logic 0 to the
suppression circuitry. This minimizes voltage glitches at the
output during turn-on and turn-off, thus reducing audible noise
on activation and deactivation.

The fully differential input of the SSM2305 provides excellent
rejection of common-mode noise on the input. Input coupling
capacitors can be omitted if the dc input common-mode voltage
is approximately V

The SSM2305 has excellent rejection of power supply noise,
including noise caused by GSM transmission bursts and RF
rectification. PSRR is typically 60 dB at 217 Hz.

The default gain of the SSM2305 is 18 dB, but users can reduce the
gain by using a pair of external resistors.

The SSM2305 is specified over the commercial temperature range
(−40°C to +85°C). It is available in both an 8-lead, 3 mm ×
3 mm lead frame chip scale package (LFCSP) and an 8-lead
mini small outline package (MSOP).

SD

pin. The device also includes pop-and-click

/2.

DD

FUNCTIONAL BLOCK DIAGRAM

10µF

SSM2305

AUDIO IN+

AUDIO IN–

SHUTDOWN

INPUT CAPACIT ORS ARE OPTI ONAL IF INPUT DC COMM ON-MODE VOLTAGE IS
APPROXIMATELY

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

47nF*

47nF*

37kΩ

IN+

37kΩ

IN–

SD

/2.

DD

296kΩ

MODULATOR

(Σ-Δ)

296kΩ

BIAS

Figure 1.

0.1µF

VDD

FET

DRIVER

INTERNAL

OSCILLAT OR

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

POP/CLICK

SUPPRESSION

GND

VBATT

2.5V TO 5. 5V

OUT+

OUT–

07243-001

SSM2305

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications Information .............................................................. 11

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 4

Thermal Resistance ...................................................................... 4

ESD Caution .................................................................................. 4

Pin Configurations and Function Descriptions ........................... 5

Typical Performance Characteristics ............................................. 6

REVISION HISTORY

7/08—Rev. 0 to Rev. A

Changes to Figure 1 .......................................................................... 1

Change to Shutdown Current Parameter, Table 1 ........................ 3

Change to Differential Input Impedance Parameter, Table 1 ..... 3

Added Exposed Pad Notation to Figure 2 ..................................... 5

Change to Figure 24 ......................................................................... 9

Changes to Figure 32 and Figure 33 ............................................. 11

Changes to Gain Section ................................................................ 12

Updated Outline Dimensions ....................................................... 14

3/08—Revision 0: Initial Version

Overview ..................................................................................... 11

Gain .............................................................................................. 12

Pop-and-Click Suppression ...................................................... 12

Output Modulation Description .............................................. 12

Layout .......................................................................................... 12

Input Capacitor Selection .......................................................... 12

Proper Power Supply Decoupling ............................................ 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. A | Page 2 of 16

SSM2305

SPECIFICATIONS

VDD = 5.0 V, TA = 25oC, RL = 8 Ω + 33 μH, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

DEVICE CHARACTERISTICS

Output Power P

O

R
R
R
R
R
R
R
Efficiency η PO = 1.3 W, 8 Ω 89 %
Total Harmonic Distortion + Noise THD + N PO = 1 W into 8 Ω, f = 1 kHz 0.02 %
P
Input Common-Mode Voltage Range VCM 1.0 VDD − 1 V
Common-Mode Rejection Ratio CMRR
Average Switching Frequency fSW 280 kHz
Differential Output Offset Voltage V

OOS

POWER SUPPLY

Supply Voltage Range V

DD

Power Supply Rejection Ratio PSRR VDD = 2.5 V to 5.0 V, dc input floating 70 85 dB
PSRR
Supply Current I

SY

V
V
V
V
V
Shutdown Current ISD

GAIN CONTROL

Closed-Loop Gain Av 18 dB
Differential Input Impedance Z

IN

SHUTDOWN CONTROL

Input Voltage High V
Input Voltage Low V
Wake-Up Time t
Shutdown Time t

Output Impedance Z

IH

IL

WU

SD

OUT

NOISE PERFORMANCE

Output Voltage Noise en

Signal-to-Noise Ratio SNR PO = 1.4 W, RL = 8 Ω 98 dB

RL = 8 Ω, THD = 1%, f = 1 kHz, BW = 20 kHz 1.34 W

= 8 Ω, THD = 1%, f = 1 kHz, BW = 20 kHz, VDD = 3.6 V 0.68 W

L

= 8 Ω, THD = 10%, f = 1 kHz, BW = 20 kHz 1.67 W

L

= 8 Ω, THD = 10%, f = 1 kHz, BW = 20 kHz, VDD = 3.6 V 0.85 W

L

= 4 Ω, THD = 1%, f = 1 kHz, BW = 20 kHz 2.22 W

L

= 4 Ω, THD = 1%, f = 1 kHz, BW = 20 kHz, VDD = 3.6 V 1.1 W

L

= 4 Ω, THD = 10%, f = 1 kHz, BW = 20 kHz 2.8 W

L

= 4 Ω, THD = 10%, f = 1 kHz, BW = 20 kHz, VDD = 3.6 V 1.3 W

L

= 0.5 W into 8 Ω, f = 1 kHz, VDD = 3.6 V 0.02 %

O

GSM VCM

= 2.5 V ± 100 mV at 217 Hz, output referred 55 dB

G = 18 dB 2.0 mV

Guaranteed from PSRR test 2.5 5.5 V

GSM VRIPPLE

= 100 mV at 217 Hz, inputs ac GND, CIN = 0.1 μF 60 dB

VIN = 0 V, no load 3.2 mA

= 0 V, 3.3 mA

IN

= 0 V, no load, VDD = 3.6 V 2.8 mA

IN

= 0 V, VDD = 3.6 V 2.9 mA

IN

= 0 V, no load, VDD = 2.5 V 2.4 mA

IN

= 0 V, VDD = 2.5 V 2.4 mA

IN

= GND

SD

SD = VDD

20 30 nA

37 kΩ

ISY ≥ 1 mA 1.2 V
ISY ≤ 300 nA 0.5 V
SD rising edge from GND to VDD
SD falling edge from VDD to GND

= GND

SD

= 3.6 V, f = 20 Hz to 20 kHz, inputs are ac grounded,

V

DD

= 18 dB, A-weighted

A

V

30 ms
5 μs
>100 kΩ

40 μV

Rev. A | Page 3 of 16

SSM2305

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings apply at TA = 25°C, unless other­wise noted.

Table 2.

Parameter Rating

Supply Voltage 6 V
Input Voltage V
Common-Mode Input Voltage V
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +165°C
Lead Temperature (Soldering, 60 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

DD

DD

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 3.

Package Type θJA θJC Unit

8-Lead, 3 mm × 3 mm LFCSP 62 20.8 °C/W
8-Lead MSOP 210 45 °C/W

ESD CAUTION

Rev. A | Page 4 of 16

SSM2305

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

2NC

3IN+

(Not to Scale)

4IN–

PIN 1
INDICAT OR

SSM2305

TOP VIEW

8OUT–

7GND

6VDD

5OUT+

SD

1

2

NC

3

IN+

(Not to S cale)

IN–

4

07243-002

NC = NO CONNECT

Figure 3. MSOP Pin Configuration

SD 1

NOTES:

1. NC = NO CONNECT .

2. EXPOSED P AD IS NOT CO NNECTED INTERNALLY.
FOR INCREASED REL IABILI TY OF T HE SOLDER
JOINTS AND MAXIMUM THERMAL CAPABILIT Y IT
IS RECOMMENDED THAT THE PAD BE SOLDERED

TO THE GRO UND PLANE.

Figure 2. LFSCP Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1

SD

Shutdown Input. Active low digital input.
2 NC No Connect. This pin has no function; tie it to GND.
3 IN+
4 IN−
5 OUT+
6 VDD
7 GND

Noninverting Input.

Inverting Input.

Noninverting Output.

Power Supply.

Ground.
8 OUT− Inverting Output.

SSM2305

TOP VIEW

OUT–

8

7

GND

6

VDD

OUT+

5

07243-103

Rev. A | Page 5 of 16

SSM2305

TYPICAL PERFORMANCE CHARACTERISTICS

100

10

RL = 4Ω + 33µH
GAIN = 18dB

VDD = 2.5V

100

10

RL = 8Ω + 33µH
GAIN = 6dB

VDD = 2.5V

VDD = 3.6V

0.01 0.1

VDD = 5V

1

THD + N (%)

0.01

1

0.1

0.0001
OUTPUT PO WER (W)

Figure 4. THD + N vs. Output Power into 4 Ω + 33 μH, AV = 18 dB

100

RL = 4Ω + 33µH
GAIN = 6dB

10

1

0.1

THD + N (%)

0.01

0.001

0.0001
OUTPUT PO WER (W)

Figure 5. THD + N vs. Output Power into 4 Ω + 33 μH, A

VDD = 2.5V

VDD = 3.6V

0.01 0.1

VDD = 5V

1

= 6 dB

V

1

0.1

THD + N (%)

0.01

100.001

07243-004

0.001

0.0001
OUTPUT PO WER (W)

VDD = 3.6V

0.01 0.1

VDD = 5V

1

100.001

07243-007

Figure 7. THD + N vs. Output Power into 8 Ω + 33 μH, AV = 6 dB

100

VDD = 5V
GAIN = 18dB
R

= 4Ω + 33µH

L

10

1

0.1

THD + N (%)

0.01

100.001

07243-005

0.001
10

100

2W

1W

0.5W

1000 10000010000

FREQUENCY (Hz)

07243-008

Figure 8. THD + N vs. Frequency, VDD = 5 V, RL = 4 Ω + 33 μH, AV = 18 dB

100

RL = 8Ω + 33µH

0.1

THD + N (%)

0.01

0.001

10

1

0.0001

GAIN = 18dB

OUTPUT PO WER (W)

VDD = 2.5V

VDD = 3.6V

0.01 0.1

1

Figure 6. THD + N vs. Output Power into 8 Ω + 33 μH, A

VDD = 5V

= 18 dB

V

100.001

07243-006

Rev. A | Page 6 of 16

100

100

VDD= 5V
GAIN = 18dB
R

= 8Ω + 33µH

L

10

10

1

1

0.1

0.1

THD + N (%)

0.01

0.01

0.001

0.001
10

0.5W

0.25W

100

1W

1000 10000010000

FREQUENCY (Hz)

Figure 9. THD + N vs. Frequency, VDD = 5 V, RL = 8 Ω + 33 μH, AV = 18 dB

07243-009

SSM2305

100

VDD = 3.6V
GAIN = 18dB
R

= 4Ω + 33µH

L

10

THD + N (%)

0.01

0.001

1

0.1

10

1W

100

0.5W

0.25W

1000 10000010000

FREQUENCY (Hz)

Figure 10. THD + N vs. Frequency, VDD = 3.6 V, RL = 4 Ω + 33 μH, AV = 18 dB

100

VDD = 3.6V
GAIN = 18dB
R

= 8Ω + 33µH

L

10

1

0.1

THD + N (%)

0.01

0.001

0.5W

10

100

0.25W

0.25W

1000 10000010000

FREQUENCY (Hz)

Figure 11. THD + N vs. Frequency, VDD = 3.6 V, RL = 8 Ω + 33 μH, AV = 18 dB

100

VDD = 2.5V
GAIN = 18dB
R

= 8Ω + 33µH

L

10

1

0.1

THD + N (%)

0.01

0.075W

0.001
10

07243-010

Figure 13. THD + N vs. Frequency, V

3.8

3.6

3.4

3.2

3.0

2.8

2.6

SUPPLY CURRENT (mA)

2.4

2.2

2.0

2.53.03.54.04.55.05.56.

07243-011

0.25W

0.125W

100

FREQUENCY (Hz)

RL = 8Ω + 33µH

SUPPLY VOLTAGE (V)

1000 10000010000

= 2.5 V, RL = 8 Ω + 33 μH, AV = 18 dB

DD

RL = 4Ω + 33µH

NO LOA D

07243-013

07243-014

0

Figure 14. Supply Current vs. Supply Voltage

100

VDD = 2.5V
GAIN = 18dB
R

= 4Ω + 33µH

L

10

0.5W

1

0.1

THD + N (%)

0.01

0.001
10

100

0.25W

0.125W

1000 10000010000

FREQUENCY (Hz)

07243-012

Figure 12. THD + N vs. Frequency, VDD = 2.5 V, RL = 4 Ω + 33 μH, AV = 18 dB

Rev. A | Page 7 of 16

12

10

8

VDD = 5V

6

4

SHUTDOWN CURRENT (µ A)

2

0

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

SHUTDOWN VOLTAGE (V )

VDD = 3.6V

VDD = 2.5V

Figure 15. Shutdown Current vs. Shutdown Voltage

07243-015

SSM2305

3.0

f = 1kHz
GAIN = 18dB

2.5
R

= 4Ω + 33µH

L

2.0

1.5

1.0

OUTPUT POWER (W)

0.5

0

2.5 3.0

10%

1%

3.54.04.55

SUPPLY VOLTAGE (V)

Figure 16. Maximum Output Power vs. Supply Voltage,

= 4 Ω + 33 μH, AV = 18 dB

R

L

07243-016

.0

1.8

f = 1kHz

1.6
GAIN = 6dB
R

= 8Ω + 33µH

1.4

1.2

1.0

0.8

0.6

OUTPUT POWER (W)

0.4

0.2

L

0

2.5 3.0 3. 5

SUPPLY VOLTAGE (V)

10%

1%

4.0 4.5 5.0

Figure 19. Maximum Output Power vs. Supply Voltage,

= 8 Ω + 33 μH, AV = 6 dB

R

L

07243-019

3.0

f = 1kHz
GAIN = 6dB

2.5
R

= 4Ω + 33µH

L

2.0

1.5

1.0

OUTPUT POWER (W)

0.5

0

2.5 3.0 3. 5

10%

1%

4.0 4.5 5.0

SUPPLY VOLTAGE (V)

Figure 17. Maximum Output Power vs. Supply Voltage,

= 4 Ω + 33 μH, AV = 6 dB

R

L

1.8

f = 1kHz

1.6
GAIN = 18dB
R

= 8Ω + 33µH

1.4

1.2

1.0

0.8

0.6

OUTPUT POWER (W)

0.4

0.2

L

0

2.5 3.0 3. 5

SUPPLY VOLTAGE (V)

10%

1%

4.0 4.5 5.0

Figure 18. Maximum Output Power vs. Supply Voltage,

= 8 Ω + 33 μH, AV = 18 dB

R

L

100

RL = 4Ω + 33µH

90

GAIN = 18dB

80

70

60

50

40

EFFICIE NCY (%)

30

20

10

07243-017

0

0 0.20.40.60.81.01.21.41.61.82.0

VDD = 2.5V

VDD = 5V

VDD = 3.6V

07243-020

OUTPUT PO WER (W)

Figure 20. Efficiency vs. Output Power into 4 Ω + 33 μH

100

RL = 8Ω + 33µH

90

GAIN = 18dB

80

VDD = 2.5V

70

60

50

40

EFFICIE NCY (%)

30

20

10

07243-018

0

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

VDD = 3.6V

OUTPUT PO WER (W)

VDD = 5V

07243-021

Figure 21. Efficiency vs. Output Power into 8 Ω + 33 μH

Rev. A | Page 8 of 16

SSM2305

0.6

VDD = 5.0V

0.5

R

= 4Ω + 33µH

L

0.4

0.3

0.2

POWER DISSIPATIO N (W)

0.1

0.14

VDD = 3.6V
R

= 8Ω + 33µH

0.12

0.10

0.08

0.06

0.04

POWER DISSIPATION (W)

0.02

L

0

0 0.5 1.0 1.5 2.0 2.5 3.0

OUTPUT PO WER (W)

Figure 22. Power Dissipation vs. Output Power into 4 Ω + 33 μH

= 5.0 V

at V

DD

0.20

0.18
VDD = 5.0V

R

= 8Ω + 33µH

0.16

0.14

0.12

0.10

0.08

0.06

POWER DISSIPATIO N (W)

0.04

0.02

L

0

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

OUTPUT PO WER (W)

Figure 23. Power Dissipation vs. Output Power into 8 Ω + 33 μH

= 5.0 V

at V

DD

07243-022

0

00.20.1 0.40.3 0. 5 0.6 0.7 0.8 0.9 1.0

OUTPUT POWER (W)

07243-025

Figure 25. Power Dissipation vs. Output Power into 8 Ω + 33 μH

= 3.6 V

at V

DD

800

RL = 4Ω + 33µH

700

600

500

400

VDD = 2.5V

300

SUPPLY CURRENT (mA)

200

100

07243-023

0

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

VDD = 3.6V

OUTPUT PO WER (W)

VDD = 5V

07243-026

Figure 26. Supply Current vs. Output Power into 4 Ω + 33 μH

0.40

VDD = 3.6V
R

0.35

0.30

0.25

0.20

0.15

POWER DISSIPATIO N (W)

0.10

0.05

= 4Ω + 33µH

L

0

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

OUTPUT PO WER (W)

Figure 24. Power Dissipation vs. Output Power into 4 Ω + 33 μH

= 3.6 V

at V

DD

07243-024

Rev. A | Page 9 of 16

450

RL = 8Ω + 33µH

400

SUPPLY CURRENT (mA)

350

300

250

200

150

100

50

0

00.2

VDD = 2.5V

0.4

VDD = 3.6V

0.6 0.8 1. 0 1.2 1.4 1.6 1.8

OUTPUT PO WER (W)

Figure 27. Supply Current vs. Output Power into 8 Ω + 33 μH

VDD = 5V

07243-027

SSM2305

0

–10

–20

–30

–40

–50

PSSR (dB)

–60

–70

–80

–90

–100

10

100

1000 10000010000

FREQUENCY (Hz)

Figure 28. Power Supply Rejection Ratio vs. Frequency

07243-028

8

7

6

5

4

3

2

VOLTAGE (V)

1

0

–1

–2

–10 0 10 20

SD INPUT

30 40 50 60 70 80 90

TIME (ms)

Figure 30. Turn-On Response

OUTPUT

07243-030

0

–10

–20

–30

–40

–50

CMRR (dB)

–60

–70

–80

–90

–100

10

100

1000 10000010000

FREQUENCY (Hz)

Figure 29. Common-Mode Rejection Ratio vs. Frequency

07243-029

8

7

6

5

4

3

2

VOLTAGE (V)

1

0

–1

–2

–500 –400 –300 –200 –100 0 100 200 300 400 500

OUTPUT

SD INPUT

TIME (µs)

Figure 31. Turn-Off Response

07243-031

Rev. A | Page 10 of 16

SSM2305

APPLICATIONS INFORMATION

OVERVIEW

The SSM2305 mono Class-D audio amplifier features a filterless
modulation scheme that greatly reduces the external components
count that, in turn, conserves board space, thereby reducing
systems cost. The SSM2305 does not require an output filter,
relying instead on the inherent inductance of the speaker coil
and the natural filtering of the speaker and human ear to fully
recover the audio component of the square wave output. Most
Class-D amplifiers use some variation of pulse-width modulation
(PWM), but the SSM2305 uses Σ-Δ modulation to determine the
switching pattern of the output devices, resulting in a number of

EXTERNAL GAIN SETT INGS = 296kΩ/(37kΩ + R

important benefits. Σ-Δ modulators do not produce a sharp peak
with many harmonics in the AM frequency band, as pulse-width
modulators often do. Σ-Δ modulation provides the benefits of
reducing the amplitude of spectral components at high frequencies,
that is, reducing EMI emission that might otherwise be radiated
by speakers and long cable traces. Due to the inherent spread­spectrum nature of Σ-Δ modulation, the need for oscillator
synchronization is eliminated for designs incorporating multiple
SSM2305 amplifiers.

The SSM2305 also offers protection circuits for overcurrent and
temperature protection.

)

EXT

10µF

0.1µF
VBATT

2.5V TO 5.5V

FET

DRIVER

GND

VDD

POP/CLICK

SUPPRESSION

OUT+

OUT–

07243-032

SSM2305

47nF*

R

47nF*

EXT

R

EXT

AUDIO IN+

AUDIO IN–

SHUTDOWN

*INPUT CAPACIT ORS ARE OPT IONAL IF INPUT DC COMM ON-MODE

VOLTAGE IS APPROXIMATELY V

IN+

IN–

SD

37kΩ

37kΩ

DD

MODULATOR

BIAS

/2.

296kΩ

(Σ-Δ)

296kΩ

INTERNAL

OSCILLATOR

Figure 32. Differential Input Configuration, User-Adjustable Gain

EXTERNAL GAIN SETT INGS = 296kΩ/(37kΩ + R

SSM2305

47nF

AUDIO IN+

47nF

R

EXT

R

EXT

IN+

IN–

37kΩ

37kΩ

)

EXT

10µF

296kΩ

MODULATOR

(Σ-Δ)

296kΩ

0.1µF

DRIVER

FET

VDD

VBAT

T

2.5V TO 5. 5V

OUT+

OUT–

SHUTDOWN

SD

BIAS

INTERNAL

OSCILLATOR

GND

Figure 33. Single-Ended Input Configuration, User-Adjustable Gain

Rev. A | Page 11 of 16

POP/CLICK

SUPPRESSION

07243-033

SSM2305

GAIN

The SSM2305 has a default gain of 18 dB that can be reduced by
using a pair of external resistors with a value calculated as follows:

External Gain Settings = 296 kΩ/(37 kΩ + R

EXT

)

POP-AND-CLICK SUPPRESSION

Voltage transients at the output of audio amplifiers can occur when
shutdown activates or deactivates. Voltage transients as low as
10 mV can be heard as audio pops in the speaker. Clicks and
pops can also be classified as undesirable audible transients gener­ated by the amplifier system and, therefore, as not coming from
the system input signal. Such transients can be generated when
the amplifier system changes its operating mode. For example, the
following can be sources of audible transients: system power-up/
power-down, mute/unmute, input source change, and sample rate
change. The SSM2305 has a pop-and-click suppression architecture
that reduces these output transients, resulting in noiseless activation
and deactivation.

OUTPUT MODULATION DESCRIPTION

The SSM2305 uses three-level, Σ-Δ output modulation. Each
output is able to swing from GND to VDD, and vice versa. Ideally,
when no input signal is present, the output differential voltage is
0 V because there is no need to generate a pulse. In a real-world
situation, there are always noise sources present. Due to this
constant presence of noise, a differential pulse generates when it
is required in response to this stimulus. A small amount of current
flows into the inductive load when the differential pulse is
generated. However, most of the time output differential voltage is
0 V due to the Analog Devices patented three-level, Σ-Δ output
modulation. This feature ensures that the current flowing through
the inductive load is small.

When the user wants to send an input signal, an output pulse is
generated to follow the input voltage. The differential pulse density
is increased by raising the input signal level. Figure 34 depicts
three-level, Σ-Δ output modulation with and without input stimuli.

OUTPUT = 0V

OUT+

OUT–

VOUT

OUTPUT > 0V

OUT+

OUT–

VOUT

OUTPUT < 0V

OUT+

OUT–

VOUT

Figure 34. 3-Level, Σ-Δ Output Modulation with and Without Input Stimuli

+5V

0V

+5V

0V
+5V

0V

–5V

+5V

0V

+5V

0V

+5V

0V

+5V

0V

+5V

0V

0V

–5V

07243-003

Rev. A | Page 12 of 16

LAYOUT

As output power continues to increase, care needs to be taken
to lay out PCB traces and wires properly between the amplifier,
load, and power supply. A good practice is to use short, wide
PCB tracks to decrease voltage drops and minimize inductance.
Ensure that track widths are at least 200 mil for every inch of
track length for lowest dc resistance (DCR), and use 1 oz or 2 oz
of copper PCB traces to further reduce IR drops and inductance.
A poor layout increases voltage drops, consequently affecting
efficiency. Use large traces for the power supply inputs and
amplifier outputs to minimize losses due to parasitic trace
resistance.

Proper grounding guidelines help improve audio performance,
minimize crosstalk between channels, and prevent switching noise
from coupling into the audio signal. To maintain high output swing
and high peak output power, the PCB traces that connect the
output pins to the load and supply pins should be as wide as
possible to maintain the minimum trace resistances. It is also
recommended that a large ground plane be used for minimum
impedances.

In addition, good PCB layouts isolate critical analog paths from
sources of high interference. Separate high frequency circuits
(analog and digital) from low frequency circuits.

Properly designed multilayer PCBs can reduce EMI emission
and increase immunity to the RF field by a factor of 10 or more
compared with double-sided boards. A multilayer board allows
a complete layer to be used for the ground plane, whereas the
ground plane side of a double-sided board is often disrupted with
signal crossover.

If the system has separate analog and digital ground and power
planes, place the analog ground plane underneath the analog
power plane, and, similarly, place the digital ground plane
underneath the digital power plane. There should be no overlap
between analog and digital ground planes or analog and digital
power planes.

INPUT CAPACITOR SELECTION

The SSM2305 does not require input coupling capacitors if the
input signal is biased from 1.0 V to V
are required if the input signal is not biased within this recom­mended input dc common-mode voltage range, if high-pass
filtering is needed, or if using a single-ended source. If high-pass
filtering is needed at the input, the input capacitor, together with
the input resistor of the SSM2305, forms a high-pass filter
whose corner frequency is determined by the following
equation:

f

= 1/(2π × RIN × CIN)

C

The input capacitor can significantly affect the performance of
the circuit. Not using input capacitors degrades both the output
offset of the amplifier and the dc PSRR performance.

− 1.0 V. Input capacitors

DD

SSM2305

PROPER POWER SUPPLY DECOUPLING

To ensure high efficiency, low total harmonic distortion (THD),
and high PSRR, proper power supply decoupling is necessary.
Noise transients on the power supply lines are short duration
voltage spikes. Although the actual switching frequency can range
from 10 kHz to 100 kHz, these spikes can contain frequency
components that extend into the hundreds of megahertz. The
power supply input needs to be decoupled with a good quality
low ESL, low ESR capacitor, usually of around 4.7 μF. This

capacitor bypasses low frequency noises to the ground plane.
For high frequency transient noise, use a 0.1 μF capacitor as
close as possible to the VDD pin of the device. Placing the
decoupling capacitor as close as possible to the SSM2305 helps
maintain efficient performance.

Rev. A | Page 13 of 16

SSM2305

OUTLINE DIMENSIONS

3.25

3.00 SQ

2.75

2.95

INDICATOR

0.90 MAX

0.85 NOM

SEATING

PLANE

PIN 1

12° MAX

TOP

VIEW

0.70 MAX

0.65 TYP

0.30

0.23

0.18

2.75 SQ

2.55

0.05 MAX

0.01 NOM

0.20 REF

Figure 35. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]

3 mm × 3 mm Body, Very Thin, Dual Lead

Dimensions shown in millimeters

3.20

3.00

2.80

0.60 MAX

0.50

0.40

0.30

(CP-8-2)

0.60 MAX

5

EXPOSED

(BOTTOM VIEW)

4

EXPOSED PAD IS NOT CONNECTED I NTERNAL LY.
FOR INCREASED RELIABILIT Y OF THE SOLDER
JOINTSAND MAXIMUM THERMA L CAPABILITY IT
IS RECOM MENDED THAT THE PAD BE SOLDERED
TO THE G ROUND PLANE.

PA D

0.50
BSC

8

1

1.89

1.74

1.59

PIN 1
INDICATOR

1.60

1.45

1.30

061507-B

8

5

4

SEATING
PLANE

5.15

4.90

4.65

1.10 MAX

0.23

0.08

8°
0°

0.80

0.60

0.40

3.20

3.00

1

2.80

PIN 1

0.65 BSC

0.95

0.85

0.75

0.15

0.38

0.00

0.22

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 36. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

SSM2305CPZ-R2
SSM2305CPZ-REEL
SSM2305CPZ-REEL7
SSM2305RMZ-R2
SSM2305RMZ-REEL
SSM2305RMZ-REEL7
SSM2305-EVALZ

1

Z = RoHS Compliant Part.

1

1

1

Evaluation Board with LFCSP Model

−40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-2 Y10

1

−40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-2 Y10

1

−40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-2 Y10

−40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 Y10

1

−40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 Y10

1

−40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 Y10

Rev. A | Page 14 of 16

SSM2305

NOTES

Rev. A | Page 15 of 16

SSM2305

NOTES

©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07243-0-7/08(A)

Rev. A | Page 16 of 16