Datasheet SSM2164S, SSM2164P Datasheet (Analog Devices)

Low Cost Quad

a

FEATURES
Four High Performance VCAs in a Single Package

0.02% THD
No External Trimming
120 dB Gain Range

0.07 dB Gain Matching (Unity Gain)
Class A or AB Operation

APPLICATIONS
Remote, Automatic, or Computer Volume Controls
Automotive Volume/Balance/Faders
Audio Mixers
Compressor/Limiters/Compandors
Noise Reduction Systems
Automatic Gain Controls
Voltage Controlled Filters
Spatial Sound Processors
Effects Processors

GENERAL DESCRIPTION

The SSM2164 contains four independent voltage controlled
amplifiers (VCAs) in a single package. High performance
(100 dB dynamic range, 0.02% THD) is provided at a very low
cost-per-VCA, resulting in excellent value for cost sensitive gain
control applications. Each VCA offers current input and output
for maximum design flexibility, and a ground referenced
–33 mV/dB control port.

All channels are closely matched to within 0.07 dB at unity gain,
and 0.24 dB at 40 dB of attenuation. A 120 dB gain range is
possible.

A single resistor tailors operation between full Class A and AB
modes. The pinout allows upgrading of SSM2024 designs with
minimal additional circuitry.

The SSM2164 will operate over a wide supply voltage range of
±4 V to ±18 V. Available in 16-pin P-DIP and SOIC packages,
the device is guaranteed for operation over the extended
industrial temperature range of –40°C to +85°C.

Voltage Controlled Amplifier

SSM2164

FUNCTIONAL BLOCK DIAGRAM

V

C

I

IN

V

C

I

IN

V

C

I

IN

V

C

I

IN

AND BIASING CIRCUITRY

V+ GND V– MODE

VCA1

VCA2

VCA3

VCA4

POWER SUPPLY

I

IOUT

I

IOUT

I

IOUT

I

IOUT

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

SSM2164–SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

(VS = ±15 V, AV = 0 dB, 0 dBu = 0.775 V rms, VIN = 0 dBu, RIN = R

= 30 kΩ, f = 1 kHz,

OUT

–40°C < TA < +85°C using Typical Application Circuit (Class AB), unless otherwise noted. Typical specifications apply at TA = +25°C.)

SSM2164

Parameter Conditions Min Typ Max Units

AUDIO SIGNAL PATH

Noise V

= GND, 20 kHz Bandwidth –94 dBu

IN

Headroom Clip Point = 1% THD+N 22 dBu
Total Harmonic Distortion 2nd and 3rd Harmonics Only

A

= 0 dB, Class A 0.02 .1 %

V

A

= ±20 dB, Class A

V

A

= 0 dB, Class AB 0.16 %

V

A

= ±20 dB, Class AB

V

1

1

0.15 %

0.3 %
Channel Separation –110 dB
Unity Gain Bandwidth C
Slew Rate C

= 10 pF 500 kHz

F

= 10 pF 0.7 mA/µs

F

Input Bias Current ±10 nA
Output Offset Current V

= 0 ±50 nA

IN

Output Compliance ±0.1 V

CONTROL PORT

Input Impedance 5kΩ
Gain Constant (Note 2) –33 mV/dB
Gain Constant Temperature Coefficient –3300 ppm/°C
Control Feedthrough 0 dB to –40 dB Gain Range
Gain Matching, Channel-to-Channel A

= 0 dB 0.07 dB

V

A

= –40 dB 0.24 dB

V

3

1.5 8.5 mV

Maximum Attenuation –100 dB
Maximum Gain +20 dB

POWER SUPPLIES

Supply Voltage Range ±4 ±18 V
Supply Current Class AB 6 8 mA
Power Supply Rejection Ratio 60 Hz 90 dB

NOTES

1

–10 dBu input @ 20 dB gain; +10 dBu input @ –20 dB gain.

2

After 60 seconds operation.

3

+25°C to +85°C.

Specifications subject to change without notice.

TYPICAL APPLICATION AND TEST CIRCUIT

V

C

V

C4

V

IN4

30kΩ

500Ω

560pF

14

15

I

IN

POWER SUPPLY

AND BIASING CIRCUITRY

98

V– GND V+ MODE

0.1µF 0.1µF

VCA4

16 1

+15V–15V

13

R

B

100pF

IOUT

30kΩ

1/2

OP275

I

(7.5kΩ CLASS A)
(OPEN CLASS AB)

V

OUT4

Figure 1. RIN = R

= 30 kΩ, CF = 100 pF. Optional RB = 7.5 kΩ, Biases Gain Core to Class A Opera-

OUT

tion. For Class AB, Omit R

.

B

–2–

REV. 0

SSM2164

MODE

I

IN1

V+
I

IN4

I

OUT2

V

C2

I

IN2

I

OUT3

V

C3

I

IN3

V

C1

I

OUT1

V

C4

I

OUT4

GND V–

1
2

16
15

5
6
7

12
11
10

3
4

14
13

89

TOP VIEW

(Not to Scale)

SSM2164

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

ORDERING GUIDE

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V

Input, Output, Control Voltages . . . . . . . . . . . . . . . . V– to V+

Output Short Circuit Duration to GND . . . . . . . . . Indefinite

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Operating Temperature Range . . . . . . . . . . . . .–40°C to +85°C

Junction Temperature Range . . . . . . . . . . . . –65°C to +150°C

Model Range Description Options

SSM2164P –40°C to +85°C Plastic DIP N-16
SSM2164S –40°C to +85°C Narrow SOIC R-16A

Temperature Package Package

Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C

Package Type θJA* θ

JC

16-Pin Plastic DIP (P Suffix) 76 33 °C/W

Units

PIN CONFIGURATION

16-Lead Epoxy DIP and SOIC

16-Pin SOIC (S Suffix) 92 27 °C/W

*θ

is specified for the worst case conditions; i.e., θJA is specified for device in socket

JA

for P-DIP packages, θJA is specified for device soldered in circuit board for SOIC
package.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SSM2164 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0

–3–

SSM2164

210

200
190
180
170

160
150
140
130

120
110
100

90
80
70
60
50
40
30
20
10

0

UNITS

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45
THD – %

V

S

= ±15V

T

A

= +25°C

1200 CHANNELS

Typical Performance Characteristics

1.0
CLASS A

= ±15V

V

S

LPF = 80kHz

AV = + 20dB

0.1

THD + N – %

0.01
20 100

FREQUENCY – Hz

AV = – 20dB

AV = 0dB

1k 10k

Figure 2. THD+N vs. Frequency, Class A

1.0
CLASS AB

= ±15V

V

S

LPF = 80kHz

0.1

THD + N – %

AV = +20dB

AV = –20dB

AV = 0dB

20k

Figure 5. THD Distribution, Class AB

1.0
VS ±15V

A

= 0dB

V

LPF = 22kHz

0.1

THD + N – %

CLASS AB

CLASS A

0.01
20 100

FREQUENCY – Hz

Figure 3. THD+N vs. Frequency Class, AB

300
280
260
240
220
200
180
160
140

UNITS

120
100

80
60
40
20

0

0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0.045 0.050
THD – %

Figure 4. THD Distribution, Class A

1k 10k

VS = ±15V

= +25°C

T

A

1200 CHANNELS

20k

–4–

0.01
20 100

AMPLITUDE – V

1k 10k

RMS

Figure 6. THD+N vs. Amplitude

0.10

LPF = 80kHz

0.08

0.06

0.04

THD + N – %

0.02

0

0

±4

SUPPLY – Volts

±16±12±8

Figure 7. THD+N vs. Supply Voltage, Class A

20k

±20

REV. 0

SSM2164

1000

100

10

1k 10k 1M100k

R

BIAS

– Ω

VOLTAGE NOISE DENSITY – nV/ Hz

VS = ±15V
T

A

= +25°C

1k 10k 1M100k

R

BIAS

– Ω

10

–5

–20

–10

–15

0

5

CONTROL FEEDTHROUGH – mV

VS = ±15V
T

A

= +25°C

0.030

0.025

0.020

% THD

0.015

0.010

VS = ±15V

= 0dBu

V

IN

A

= 0dB

V

–40 –20 0 20 40 60 80

TEMPERATURE – °C

Figure 8. THD vs. Temperature, Class A

0.30

0.25

0.20

% THD

0.15

VS = ±15V

= 0dBu

V

IN

A

= 0dB

V

Figure 11. Voltage Noise Density vs. R

1.0

0.1

THD – %

VS = ±15V
T

= +25°C

A

BIAS

0.10

–40 –20 0 20 40 60 80

TEMPERATURE – °C

Figure 9. THD vs. Temperature, Class AB

500

VS = ±15V
R

= RF = 30kΩ

IN

= +25°C

T

A

400

300

200

NOISE – nV/ Hz

100

0

1 10 100k10k1k100

FREQUENCY – Hz

Figure 10. Voltage Noise Density vs. Frequency, Class AB

0.01
1k 10k 1M100k

Figure 12. THD vs. R

R

– Ω

BIAS

BIAS

Figure 13. Control Feedthrough vs. R

BIAS

REV. 0

–5–

SSM2164

30

15

0

110

100

5

10

20

25

SLEW RATE – V/µs

I TO V FEEDBACK CAPACITOR – pF

±SLEW RATE
V

S

= ±15V

TA = +25°C

OP275 OUTPUT

AMPLIFIER

20

–20

–80

1k 1M100k10k100

–40

–60

0

FREQUENCY – Hz

VS = ±15V
T

A

= +25°C

V

IN

= 0V

R

F

= RIN = 30kΩ

CONTROL FEEDTHROUGH – dB

10M

1M

10k

1 10 1000100

100k

–3dB BANDWIDTH – Hz

I TO V FEEDBACK CAPACITOR – pF

VS = ±15V
T

A

= +25°C

Typical Performance Characteristics

15

10

VS = ±15V
TA = +25°C

5

AV = 0dB
CF = 10pF

0

GAIN – dB

–5

PHASE

GAIN

180

90

0

–90

PHASE – Degrees

–10

–15

10k 10M1M100k1k

FREQUENCY – Hz

Figure 14. Gain/Phase vs. Frequency

0.1

0

–0.1

GAIN – dB

–0.2

–0.3

–0.4

VS = ±15V
T

= +25°C

A

A

= 0dB

V

100 100k10k1k10

CF = 100pF

FREQUENCY – Hz

Figure 15. Gain Flatness vs. Frequency

C

= 10pF

F

–180

Figure 17. –3 dB Bandwidth vs. I-to-V Feedback Capacitor

Figure 18. Slew Rate vs. I-to-V Feedback Capacitor

40

20

0

GAIN – dB

–20

–40

–60

100 1k 10M1M100k10k

AV = +20dB

AV = 0dB

AV = –20dB

FREQUENCY – Hz

Figure 16. Bandwidth vs. Gain

VS = ±15V
TA = +25°C

= 10pF

C

F

–6–

Figure 19. Control Feedthrough vs. Frequency

REV. 0

SSM2164

Q6Q5 Q8Q7

Q2Q1 Q4Q3

I

IN

I

OUT

V

C

4.5kΩ

500Ω

450Ω

MODE

V–

V+

0

–20

–40

PSRR – dB

–60

–80

–100

VS = ±15V

= +25°C

T

A

10 100 1M100K10k1k

Figure 20. PSRR vs. Frequency

25

20

15

+ISY

+PSRR

–PSRR

FREQUENCY – Hz

VS = ±15V

= +25°C

T

A

APPLICATIONS INFORMATION
Circuit Description

The SSM2164 is a quad Voltage Controlled Amplifier (VCA)
with 120 dB of gain control range. Each VCA is a current-in,
current-out device with a separate –33 mV/dB voltage input
control port. The class of operation (either Class A or Class
AB) is set by a single external resistor allowing optimization of
the distortion versus noise tradeoff for a particular application.
The four independent VCAs in a single 16-pin package make
the SSM2164 ideal for applications where multiple volume
control elements are needed.

–ISY

10

SUPPLY CURRENT – mA

5

0

1k 10k 1M100k

R

– Ω

BIAS

Figure 23. Simplified Schematic (One Channel)

Figure 21. Supply Current vs. R

BIAS

The simplified schematic in Figure 23 shows the basic structure
of one of the four VCAs in the device. The gain core is com-

–45

–40

–35

VS = ±15V

CLASS A AND
CLASS AB

prised of the matched differential pairs Q1-Q4 and the current
mirrors of Q5, Q6 and Q7, Q8. The current input pin, I

, is

IN

connected to the collectors of Q1 and Q7, and the difference in
current between these two transistors is equivalent to I

. For

IN

example, if 100 µA is flowing into the input, Q1’s collector
current will be 100 µA higher than Q7’s collector current.

Varying the control voltage V

, steers the signal current from

C

one side of each differential pair to the other, resulting in either

–30

GAIN CONSTANT – mV/dB

–25

gain or attenuation. For example, a positive voltage on V

C

steers more current through Q1 and Q4 and decreases the
current in Q2 and Q3. The current output pin, I

, is con-

OUT

nected to the collector of Q3 and the current mirror (Q6) from
Q2. With less current flowing through these two transistors, less

–20

Figure 22. Gain Constant vs. Temperature

–50

–25

TEMPERATURE – °C

7550250

100

current is available at the output. Thus, a positive V
the input and a negative V

amplifies the input. The VCA has

C

unity gain for a control voltage of 0.0 V where the signal current
is divided equally between the gain core differential pairs.

The MODE pin allows the setting of the quiescent current in

attenuates

C

the gain core of the VCA to trade off the SSM2164’s THD and
noise performance to an optimal level for a particular applica­tion. Higher current through the core results in lower distortion

REV. 0

–7–

SSM2164

1µF

1µF

1µF

1µF

+5V

100k

30k

V

IN4

500

560pF

POWER SUPPLY

AND BIASING CIRCUITRY

VCA4

+5V

100k

30k

V

IN3

500

560pF

VCA3

+5V

100k

30k

V

IN2

500

560pF

VCA2

+5V

100k

30k

V

IN1

500

560pF

VCA1

98

16 1

V– GND V+ MODE

0.1µF 0.1µF
RB(7.5kΩ CLASS A)

(OPEN CLASSAB)

+15V–15V

1/4

OP482

1/4

OP482

1/4

OP482

1/4

OP482

30k

30k

30k

30k

100pF

100pF

100pF

100pF

V

OUT1

V

OUT2

V

OUT3

V

OUT4

I

IOUT

I

IOUT

I

IOUT

I

IOUT

3

2

6

7

4

5

13

12

11

10

14

15

V

C

I

IN

I

IN

V

C

I

IN

V

C

I

IN

V

C

but higher noise, and the opposite is true for less current. The
increased noise is due to higher current noise in the gain core
transistors as their operating current is increased. THD has the

a low cutoff frequency. The main exception to this is in
dynamic processing applications, where faster attack or decay
times may be needed.

opposite relationship to collector current. The lower distortion
is due to the decrease in the gain core transistors’ emitter
impedance as their operating current increases.

This classical tradeoff between THD and noise in VCAs is
usually expressed as the choice of using a VCA in either Class A
or Class AB mode. Class AB operation refers to running a VCA
with less current in the gain core, resulting in lower noise but
higher distortion. More current in the core corresponds to
Class A performance with its lower THD but higher noise.
Figures 11 and 12 show the THD and noise performance of the
SSM2164 as the bias current is adjusted. Notice the two
characteristics have an inverse characteristic.

The quiescent current in the core is set by adding a single
resistor from the positive supply to the MODE pin. As the
simplified schematic shows, the potential at the MODE pin is
one diode drop above the ground pin. Thus, the formula for the
MODE current is:

I

MODE

With ±15 V supplies, an R

(V +)−0.6V

=

R

B

of 7.5k gives Class A biasing with a

B

current of 1.9 mA. Leaving the MODE pin open sets the
SSM2164 in Class AB with 30 µA of current in the gain core.

Basic VCA Configuration

Figure 24 shows the basic application circuit for the SSM2164.
Each of the four channels is configured identically. A 30 kΩ
resistor converts the input voltage to an input current for the
VCA. Additionally, a 500 Ω resistor in series with a 560 pF
capacitor must be added from each input to ground to ensure
stable operation. The output current pin should be maintained
at a virtual ground using an external amplifier. In this case the
OP482 quad JFET input amplifier is used. Its high slew rate,
wide bandwidth, and low power make it an excellent choice for
the current-to-voltage converter stage. A 30 kΩ feedback
resistor is chosen to match the input resistor, giving unity gain
for a 0.0 V control voltage. The 100 pF capacitors ensure
stability and reduce high frequency noise. They can be
increased to reduce the low pass cutoff frequency for further
noise reduction.

For this example, the control voltage is developed using a
100 kΩ potentiometer connected between +5 V and ground.
This configuration results in attenuation only. To produce both
gain and attenuation, the potentiometer should be connected
between a positive and negative voltage. The control input has
an impedance of 5 kΩ. Because of this, any resistance in series
with V
the gain and attenuation is required, a buffered control voltage
should be used.

Notice that a capacitor is connected from the control input to
ground. Because the control port is connected directly to the
gain core transistors, any noise on the V
output noise of the VCA. Filtering the control voltage ensures
that a minimal amount of noise is introduced into the VCA,
allowing its full performance to be realized. In general, the
largest possible capacitor value should be used to set the filter at

will attenuate the control signal. If precise control of

C

pin will increase the

C

Figure 24. Basic Quad VCA Configuration

Low Cost, Four-Channel Mixer

The four VCAs in a single package can be configured to create a
simple four-channel mixer as shown in Figure 25. The inputs
and control ports are configured the same as for the basic VCA,
but the outputs are summed into a single output amplifier. The
OP176 is an excellent amplifier for audio applications because
of its low noise and distortion and high output current drive.
The amount of signal from each input to the common output
can be independently controlled using up to 20 dB of gain or as
much as 100 dB of attenuation. Additional SSM2164s could be
added to increase the number of mixer channels by simply
summing their outputs into the same output amplifier. Another
possible configuration is to use a dual amplifier such as the
OP275 to create a stereo, two channel mixer with a single
SSM2164.

–8–

REV. 0

30k

560pF

30k

560pF

30k

560pF

30k

560pF

500

500

500

500

V

C

I

IN

V

C

I

IN

V

C

I

IN

V

C

I

IN

AND BIASING CIRCUITRY

V+ GND V– MODE

VCA1

VCA2

VCA3

VCA4

POWER SUPPLY

I

IOUT

100pF

I

IOUT

I

IOUT

I

IOUT

FROM ADDITIONAL SSM2164s
FOR > 4 CHANNELS

30kΩ

OP176

SSM2164

If additional SSM2164s are added, the 100 pF capacitor may
need to be increased to ensure stability of the output amplifier.
Most op amps are sensitive to capacitance on their inverting
inputs. The capacitance forms a pole with the feedback resistor,
which reduces the high frequency phase margin. As more
SSM2164’s are added to the mixer circuit, their output capaci­tance and the parasitic trace capacitance add, increasing the
overall input capacitance. Increasing the feedback capacitor will
maintain the stability of the output amplifier.

V

Digital Control of the SSM2164

OUT

One option for controlling the gain and attenuation of the
SSM2164 is to use a voltage output digital-to-analog converter
such as the DAC8426 (Figure 26), whose 0 V to +10 V output
controls the SSM2164’s attenuation from 0 dB to –100 dB. Its
simple 8-bit parallel interface can easily be connected to a
microcontroller or microprocessor in any digitally controlled
system. The voltage output configuration of the DAC8426
provides a low impedance drive to the SSM2164 so the attenua­tion can be controlled accurately. The 8-bit resolution of the
DAC and its full-scale voltage of +10 V gives an output of

3.9 mV/bit. Since the SSM2164 has a –33 mV/dB gain con­stant, the overall control law is 0.12 dB/bit or approximately
8 bits/dB. The input and output configuration for the
SSM2164 is the same as for the basic VCA circuit shown
earlier. The 4-to-1 mixer configuration could also be used.

Figure 25. Four-Channel Mixer (4 to 1)

V

REF

REFERENCE

LOGIC

CONTROL

10V

LATCH A

LATCH B

LATCH C

LATCH D

MSB

LSB

WR

DAC8426

7

DATA BUS

14

15
16

A1

17

A0

OUT +10V

4

3

V

SS

+15V

V

DD

18

DAC A

DAC B

DAC C

DAC D

5

AGND DGND

V

C

I

IN

V

C

2

V

OUTA

1

V

OUTB

20

V

OUTC

19

V

OUTD

6

I

IN

V

C

I

IN

V

C

I

IN

AND BIASING CIRCUITRY

VCA1

VCA2

VCA3

VCA4

POWER SUPPLY

I

IOUT

I

IOUT

I

IOUT

I

IOUT

REV. 0

Figure 26. Digital Control of VCA Gain

–9–

V+

GND

+15V –15V

V– MODE

SSM2164

Single Supply Operation

The SSM2164 can easily be operated from a single power
supply as low as +8 V or as high as +36 V. The key to using a
single supply is to reference all ground connections to a voltage
midway between the supply and ground as shown in Figure 27.
The OP176 is used to create a pseudo-ground reference for the
SSM2164. Both the OP482 and OP176 are single supply
amplifiers and can easily operate over the same voltage range as
the SSM2164 with little or no change in performance.

V+ = +8V

(1.8kΩ FOR
CLASS A)

R

B

(OPEN FOR

10µF

V

IN

30kΩ

560pF

(0dB GAIN AT VC = )

500Ω

V

CLASS B)

16

1

V+

MODE

GND

V–

8

9

C

V+

2

TO ADDITIONAL

OP482 AMPLIFIERS

V+/2

30kΩ

V+

1/4

OP482

V+

OP176

100pF

10kΩ

V

OUT

V+

10kΩ

10µF

Figure 27. Single Supply Operation of the SSM2164
(One Channel Shown)

The reference voltage is set by the resistor divider from the
positive supply. Two 10 kΩ resistors create a voltage equal to
the positive supply divided by 2. The 10 µF capacitor filters the
supply voltage, providing a low noise reference to the circuit.
This reference voltage is then connected to the GND pin of the
SSM2164 and the noninverting inputs of all the output amplifi­ers. It is important to buffer the resistor divider with the OP176
to ensure a low impedance pseudo-ground connection for the
SSM2164.

The input can either be referenced to this same mid-supply
voltage or ac coupled as is done in this case. If the entire system
is single supply, then the input voltage will most likely already
be referenced to the midpoint; if this is the case, the 10 µF
input capacitor can be eliminated. Unity gain is set when V

C

equals the voltage on the GND pin. Thus, the control voltage
should also be referenced to the same midsupply voltage.

The value of the MODE setting resistor may also change
depending on the total supply voltage. Because the GND pin is
at a pseudo-ground potential, the equation to set the MODE
current now becomes:

I

MODE

(V +)−V

=

GND

R

B

−0.6V

The value of 1.8 kΩ results in Class A biasing for the case of
using a +8 V supply.

Upgrading SSM2024 Sockets

The SSM2164 is intended to replace the SSM2024, an earlier
generation quad VCA. The improvements in the SSM2164
have resulted in a part that is not a drop-in replacement to the
SSM2024, but upgrading applications with the SSM2024 is a
simple task. The changes are shown in Figure 28. Both parts
have identical pinouts with one small exception. The MODE
input (Pin 1) does not exist on the SSM2024. It has fixed
internal biasing, whereas flexibility was designed into the
SSM2164. A MODE set resistor should be added for Class A
operation, but if the SSM2164 is going to be operated in Class
AB, no external resistor is needed.

10kΩ

V

C1

3

10kΩ

200Ω

V

C1

30kΩ

500Ω

560pF

2

3

2

V

IN1

V

IN1

V+

16

SSM2024

9

V–

V+

16

SSM2164

9

V–

NC

8

8

1

1

10kΩ

4

V

OUT1

R

B

30kΩ

4

V

OUT1

Figure 28. Upgrading SSM2024 Sockets with SSM2164

Since both parts are current output devices, the output configu­ration is nearly identical, except that the 10 kΩ resistors should
be increased to 30 kΩ to operate the SSM2164 in its optimum
range. The 10 kΩ input resistor for the SSM2024 should also
be increased to 30 kΩ to match the output resistor. Addition­ally, the 200 Ω resistor should be replaced by a 500 Ω resistor in
series with 560 pF for the SSM2164 circuit.

One last change is the control port configuration. The
SSM2024’s control input is actually a current input. Thus, a
resistor was needed to change the control voltage to a current.
This resistor should be removed for the SSM2164 to provide a
direct voltage input. In addition, the SSM2024 has a log/log
control relationship in contrast to the SSM2164’s linear/log gain
constant. The linear input is actually much easier to control,
but the difference may necessitate adjusting a SSM2024 based
circuit’s control voltage gain curve. By making these relatively
simple changes, the superior performance of the SSM2164 can
easily be realized.

–10–

REV. 0

OUTLINE DIMENSIONS

0.210

(5.33)

MAX

0.160 (4.06)

0.115 (2.93)

0.022 (0.558)

0.014 (0.356)

0.100

(2.54)

BSC

PIN 1

0.280 (7.11)

0.240 (6.10)

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)

0.115 (2.93)

SEATING
PLANE

0.060 (1.52)

0.015 (0.38)

0.130
(3.30)
MIN

0.070 (1.77)

0.045 (1.15)

0.840 (21.33)

0.745 (18.93)

9

16

18

Dimensions shown in inches and (mm).

16-Pin Plastic DIP (N-16)

16-Pin Narrow SOIC (R-16A)

SSM2164

16 9

PIN 1

1

0.3937 (10.00)

0.0098 (0.25)

0.0040 (0.10)

0.0500
(1.27)

BSC

0.3859 (9.80)

0.0192 (0.49)

0.0138 (0.35)

0.1574 (4.00)

0.1497 (3.80)

8

0.0688 (1.75)

0.0532 (1.35)

0.2440 (6.20)

0.2284 (5.80)

0.0099 (0.25)

0.0075 (0.19)

8°
0°

0.0196 (0.50)

0.0099 (0.25)

0.0500 (1.27)

0.0160 (0.41)

x 45°

REV. 0

–11–

C1969–10–10/94

–12–

PRINTED IN U.S.A.