Datasheet SSM2122, SSM2120 Datasheet (Analog Devices)

SIGNAL

OUT

CURRENT
MIRRORS

–V

C

+V

C

V+

V+

V+

SIGNAL

INPUT

36kΩ

36kΩ

V+

V–

I

REF

Dynamic Range

13

16
15
14

22
21
20
19
18
17

12

TOP VIEW

(Not to Scale)

11

10

9

8

1
2
3
4

7

6

5

SSM2120

THRESH 1

+V

C2

SIG

OUT 2

V+

GND

LOG AV 1
CON

OUT 1

SIG

OUT 1

SIG

IN 2

–V

C2

CFT 2

+V

C1

CFT 1

–V

C1

SIG

IN 1

REC

IN 1

I

REF

LOG AV 2

CON

OUT 2

REC

IN 2

V– THRESH 2

14
13
12
11

16
15

10

9

8

1
2
3
4

7

6

5

TOP VIEW

(Not to Scale)

SSM2122

GND

+V

C2

SIG

OUT 2

V+

GND

SIG

OUT 1

+V

C1

CFT 1

SIG

IN 2

–V

C2

CFT 2

–V

C1

SIG

IN 1

I

REF

V–

GND

a

FEATURES

0.01% THD at +10 dBV In/Out
100 dB VCA Dynamic Range
Low VCA Control Feedthrough
100 dB Level Detection Range
Log/Antilog Control Paths
Low External Component Count

APPLICATIONS
Compressors
Expanders
Limiters
AGC Circuits
Voltage-Controlled Filters
Noise Reduction Systems
Stereo Noise Gates

GENERAL DESCRIPTION

The SSM2120 is a monolithic integrated circuit designed for the
purpose of processing dynamic signals in various analog systems
including audio. This “dynamic range processor” consists of two
VCAs and two level detectors (the SSM2122 consists of two
VCAs only). These circuit blocks allow the user to logarithmically
control the gain or attenuation of the signals presented to the
level detectors depending on their magnitudes. This allows the
compression, expansion or limiting of ac signals, some of the
primary applications for the SSM2120.

Processors/Dual VCA

SSM2120/SSM2122

FUNCTIONAL BLOCK DIAGRAM

PIN CONNECTIONS

22-Pin Plastic DIP

(P Suffix)

16-Pin Plastic DIP

(P Suffix)

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

© Analog Devices, Inc., 1995

SSM2120/SSM2122–SPECIFICATIONS

(@VS = 615 V, TA = +258C, I

ELECTRICAL CHARACTERISTICS

unless otherwise noted)

Parameter Conditions Min Typ Max Units

POWER SUPPLY

Supply Voltage Range ±5 ±18 V
Positive Supply Current 810mA
Negative Supply Current –6 –8 mA

VCAs

Max I

(In/Out) ±300 ±325 ±350 µA

SIGNAL

Output Offset ±1 ±8 µA
Control Feedthrough (Trimmed) R

IN

= R

= 36 kΩ, –30 dB ≤ AV ≤ 0 dB ±750 µV

OUT

Gain Control Range Unity-Gain –85 +40 dB
Control Sensitivity 6 mV/dB
Gain Scale Factor Drift –3300 ppm/°C
Frequency Response Unity Gain or Less 250 kHz
Off Isolation At 1 kHz 100 dB
Current Gain +V

= –VC = 0 V –0.5 +0.5 dB

C

THD (Unity-Gain) +10 dBV IN/OUT 0.005 0.04 %
Noise (20 kHz Bandwidth) RE: 0 dBV –80 dB

LEVEL DETECTORS (SSM2120 ONLY)

Detection Range 90 95 dB
Input Current Range 0.085 2800 µA p-p
Rectifier Input Bias Current 4nA
Output Sensitivity (At LOG AV Pin) 3 mV/dB
Output Offset Voltage ±0.5 ±3.4 mV
Frequency Response

I

= 1 mA p-p 1000

IN

I

= 10 µA p-p 50 kHz

IN

I

= 1 µA p-p 7.5

IN

CONTROL AMPLIFIERS (SSM2120 ONLY)

Input Bias Current ±85 ±175 nA
Output Drive (Max Sink Current) 5.0 7.5 mA
Input Offset Voltage ±0.5 ±4.2 mV

Specifications are subject to change without notice.

= 200 mA, +VC = –VC = GND (AV = 0 dB). 0 dB = 1 V rms

REF

SSM2120/SSM2122

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V

Operating Temperature Range . . . . . . . . . . . . –10°C to +55°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Maximum Current into Any Pin . . . . . . . . . . . . . . . . . . 10 mA

Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C

Package Type θ

1

JA

θ

JC

Units

Model Range Description Option

SSM2120 –10°C to +50°C 22-Pin Plastic DIP (N-22)
SSM2122 –10°C to +50°C 16-Pin Plastic DIP (N-16)

ORDERING GUIDE

Temperature Package Package

16-Pin Plastic DIP (P) 86 10 °C/W
22-Pin Plastic DIP (P) 70 7 °C/W

NOTE

1

θJA is specified for worst case mounting conditions, i.e., θJA is specified for

device in socket for P-DIP.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SSM2120/SSM2122 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–2–

WARNING!

ESD SENSITIVE DEVICE

REV. C

+V

GAIN – dB

0.03

THD – %

0.01

–20 20–10 0 10

0.003

C1

INPUT 1 OUTPUT 1

–V

C1

+V

C2

INPUT 2 OUTPUT 2

–V

C2

SSM2122

CFT 1

CFT 2

Figure 1. SSM2120 Block Diagram

REC

REC

IN 1

IN 2

SSM2120/SSM2122

V+ THRESH 1

|IIN|

FULL

WAVE

RECTIFIER

2V

LOG AV 1

V+ THRESH 2

|IIN|

FULL

WAVE

RECTIFIER

2V

LOG AV 2

CON

CON

OUT 1

V–

OUT 2

V–

VOLTAGE-CONTROLLED AMPLIFIERS

The two voltage-controlled amplifiers are full Class A current
in/current out devices with complementary dB/V gain control
ports. The control sensitivities are +6 mV/dB and –6 mV/dB. A
resistor divider (attenuator) is used to adapt the sensitivity of an
external control voltage to the range of the control port. It is
best to use 200 Ω or less for the attenuator resistor to ground.

VCA INPUTS

The signal inputs behave as virtual grounds. The input current
compliance range is determined by the current into the reference
current pin.

REFERENCE PIN

The reference current determines the input and output current
compliance range of the VCAs. The current into the reference
pin is set by connecting a resistor to V+. The voltage at the
reference pin is about two volts above V– and the current will be

[(V +)–((V–)+2V )]

=

I

REF

R

REF

The current consumption of the VCAs will be directly pro­portional to I

which is nominally 200 µA. The device will

REF

operate at lower current levels which will reduce the effective
dynamic range of the VCAs. With a 200 µA reference current,
the input and output clip points will be ± 400 µA. In general:

I

= ±2 I

CLIP

REF

VCA OUTPUTS

The VCA outputs are designed to interface directly with the virtual
ground inputs of external operational amplifiers configured as
current-to-voltage converters. The outputs must operate at virtual
ground because of the output stage’s finite output impedance.
The power supplies and selected compliance range determines
the values of input and output resistors needed. As an example,
with ±15 V supplies and ±400 µA maximum input and output
current, choose R

IN

= R

= 36 kΩ for an output compliance

OUT

range of ±14.4 V. Note that the signal path through the VCA
including the output current-to-voltage converter is noninverting.

VCA PERFORMANCE

Figures 2a and 2b show the typical THD and noise performance
of the VCAs over ±20 dB gain/attenuation. Full Class A operation
provides very low THD.

a. VCA THD Performance vs. Gain
(+10 dBV In/Out @ 1 kHz)

–70

–80

NOISE – dBV

–90

–20 20–10 0 10

GAIN – dB

b. VCA Noise vs. Gain (20 kHz Bandwidth)

Figure 2. Typical THD and Noise Performance

REV. C

–3–

SSM2120/SSM2122

TRIMMING THE VCAs

The control feedthrough (CFT) pins are optional control feed­through null points. CFT nulling is usually required in applications
such as noise gating and downward expansion. If trimming is
not used, leave the CFT pins open.

Trim Procedure

1. Apply a 100 Hz sine wave to the control point attenuator.
The signal peaks should correspond to the control voltages
which induce the VCAs maximum intended gain and at least
30 dB of attenuation.

2. Adjust the 50 kΩ potentiometer for the minimum
feedthrough.

(Trimmed control feedthrough is typically well under 1 mV rms
when the maximum gain is unity using 36 kΩ input and output
resistors.)

Applications such as compressor/limiters typically do not require
control feedthrough trimming because the VCA operates at
unity-gain unless the signal is large enough to initiate gain
reduction. In this case the signal masks control feedthrough.

This trim is ineffective for voltage-controlled filter applications.

LEVEL DETECTION CIRCUITS

The SSM2120 contains two independent level detection
circuits. Each circuit contains a wide dynamic range full-wave
rectifier, logging circuit and a unipolar drive amplifier. These
circuits will accurately detect the input signal level over a
100 dB range from 30 nA to 3 mA peak-to-peak.

LEVEL DETECTOR THEORY OF OPERATION

Referring to the level detector block diagram of Figure 3, the
REC

input is an AC virtual ground. The next block imple-

IN

ments the full-wave rectification of the input current. This
current is then fed into a logging transistor (Q
transistor (Q

) has a fixed collector current of I

2

) whose pair

1

. The LOG

REF

AV output is then:





AV =

kT

q

V

LOG

ln

|

|I

IN





I





REF

With the use of the LOG AV capacitor the output is then the log
of the average of the absolute value of I

.

IN

(The unfiltered LOG AV output has broad flat plateaus with
sharp negative spikes at the zero crossing. This reduces the
“work” that the averaging capacitor must do, particularly at low
frequencies.)

Note: It is natural to assume that with the addition of the
averaging capacitor, the LOG AV output would become the

average of the log of the absolute value of I

. However, since the

IN

capacitor forces an ac ground at the emitter of the output
transistor, the capacitor charging currents are proportional to
the antilog of the voltage at the base of the output transistor.
Since the base voltage of the output transistor is the log of the
absolute value of I

, the log and antilog terms cancel, so the

IN

capacitor becomes a linear integrator with a charging current
directly proportional to the absolute value of the input current.
This effectively inverts the order of the averaging and logging
functions. The signal at the output therefore is the log of the

average of the absolute value of I

.

IN

USING DETECTOR PINS RECIN, LOGAV, THRESH AND
CON

OUT

When applying signals to RECIN (rectifier input) an input series
resistor should be followed by a low leakage blocking capacitor
since REC
ground. Choose R

has a dc voltage of approximately 2.1 V above

IN

for a ±1.5 mA peak signal. For ± 15 V

IN

operation this corresponds to a value of 10 kΩ.
A 1.5 MΩ value of R

a 10 µA reference current in the logging transistor (Q

from log average to –15 V will establish

REF

). This

1

will bias the transistor in the middle of the detector’s dynamic
current range in dB to optimize dynamic range and accuracy.
The LOG AV outputs are buffered and amplified by unipolar
drive op amps. The 39 kΩ, 1 kΩ resistor network at the
THRESH pin provides a gain of 40.

An attenuator from the CON

(control output) to the

OUT

appropriate VCA control port establishes the control sensitivity.
Use 200 Ω for the attenuator resistor to ground and choose
R

for the desired sensitivity. Care should be taken to minimize

CON

capacitive loads on the control outputs CON

. If long lines

OUT

or capacitive loads are present, it is best to connect the series
resistor R

as closely to the CON

CON

pin as possible.

OUT

DYNAMIC LEVEL DETECTOR CHARACTERISTICS

Figures 4 and 5 show the dynamic performance of the level
detector to a change in signal level. The input to the detector (not
shown) is a series of 500 ms tone bursts at 1 kHz in successive
10 dBV steps. The tone bursts start at a level of –60 dBV (with
R

= 10 k) and return to –60 dBV after each successive 10 dB

IN

step. Tone bursts range from –60 dBV to +10 dBV. Figure 4
shows the logarithmic level detector output. The output of the
detector is 3 mV/dB at LOG AV and the amplifier gain is 40
which yields 120 mV/dB. Thus, the output at CON

OUT

is seen

to increase by 1.2 V for each 10 dBV increase in input level.

1kΩ

39kΩ

INPUT

I

REF

LOG AV

R

REF

THRESH

CON

OUT

V–

R

CON

200Ω

TO V

C

V+

R

REC

IN

IN

RECTIFIER

2V

FULL

WAVE

|IIN|

Q2

Q1

C

AV

V–

Figure 3. Level Detector

–4–

REV. C

SSM2120/SSM2122

2V

100

90

10

0%

1s

Figure 4. Detector Output

2V

100

90

10

0%

50ms

Figure 5. Overlayed Detector Output

DYNAMIC ATTACK AND DECAY RATES

Figure 5 shows the output levels overlayed using a storage
scope. The attack rate is determined by the step size and the
value of C

. The attack time to final value is a function of the

AV

step size increase. Table I shows the values of total settling
times to within 5 dB, 3 dB, 2 dB and 1 dB of final value with
C

= 10 µF. When step sizes exceed 40 dB, the increase in

AV

settling time for larger steps is negligible. To calculate the attack
time to final value for any value of C
value in the chart by C

/10 µF.

AV

, simply multiply the

AV

The decay rates are linear ramps that are dependent on the
current out of the LOG AV pin (set by R
C

. The integration or decay time of the circuit is derived from

AV

) and the value of

REF

the formula:

I

×333

Decrementation Rate (in dB/s) =

REF

C

AV

Table I. Settling Time (tS) for CAV = 10 mF. tS = tS (CAV = 10 mF)

5 dB 3 dB 2 dB 1 dB

10 dB Step 11.28 ms 21.46 30.19 46.09
20 dB Step 16.65 26.83 35.56 51.46
30 dB Step 18.15 28.33 37.06 52.96
40 dB Step 18.61 27.79 37.52 53.42
50 dB Step (+144 µs)
60 dB Step (+46 µs)

APPLICATIONS

The following applications for the SSM2120 use both the VCAs
and level detectors in conjunction to assimilate a variety of
functions.

The first section describes the arrangement of the threshold
control in each control circuit configuration. These control
circuits form the foundation for the applications to follow which
include the downward expander, compressor/limiter and
compandor.

THRESHOLD CONTROL

Figure 6a shows the control circuit for a typical downward
expander while Figure 6b shows a typical control curve. Here,
the threshold potentiometer adjusts V

to provide a negative

T

unipolar control output. This is typically used in noise gate,
downward expander, and dynamic filter applications. This
potentiometer is used in all applications to control the signal
level versus control voltage characteristics.

CON

V

+

–

THRESHOLD

*

*LOWER LIMIT CAN BE FIXED
BY CONNECTING A RESISTOR

FROM RECIN TO GROUND

R

LL

VIN – dB

R

IN

L

R

MONO

OR R

IN

MONO – RIN = 10kΩ
STEREO – R

= 20kΩ

IN

REC

THRESHOLD

CONTROL

V

T

V–

R

T

39kΩ

CON

R

CON

OUT

V–

200Ω

TO +V

C

LOG AV

AV

V+

1kΩ

1.5MΩ

V–

IN

R

LL

|IIN|

2V

C

a. Control Circuit b. Typical Downward Expander
Control Curve

Figure 6. Noise Gate/Downward Expander Control Circuit and Typical Response

REV. C

–5–

SSM2120/SSM2122

In the noise gate, downward expander and compressor/limiter
applications, this potentiometer will establish the onset of the
control action. The sensitivity of the control action depends on
the value of R

.

T

For a positive unipolar control output add two diodes as shown
in Figure 7a. This is useful in compressor/limiter applications.
Figure 7b shows a typical response.

Bipolar control outputs can be realized by adding a resistor from
the op amp output to V+. This is useful in compandor circuits

THRESHOLD

CONTROL

R

IN

L

R

MONO

OR R

IN

MONO – RIN = 10kΩ
STEREO – R

= 20kΩ

IN

REC IN

V+

|IIN|

2V

C

AV

LOG AV

1.5MΩ

V–

1kΩ

THRESH

V

T

R

T

39kΩ

as shown in Figure 8a, with its response in Figure 8b. The value
of the resistor R

will determine the maximum output from the

PV

control amplifier.

STEREO COMPRESSOR/LIMITER

The two control circuits of Figures 6 and 7 can be used in
conjunction to produce composite control voltages. Figures 9a
and 9b show this type of circuit and transfer function for a
stereo compressor/limiter which also acts as a downward
expander for noise gating. The output noise in the absence of a

V+

R

PV

R

CON

CON
OUT

V–

200Ω

TO –V

C

+

CON

V

–

*UPPER LIMIT CAN BE FIXED BY
VALUE OF PULL UP RESISTOR (R
CONNECTED TO POSITIVE SUPPLY

THRESHOLD

*

PV

VIN – dB

)

a. Control Circuit b. Typical Compressor/Limiter Control
Curve

Figure 7. Compressor/Limiter Control Circuit and Typical Response

R

IN

L

R

MONO

OR R

IN

MONO – RIN = 10kΩ
STEREO – R

= 20kΩ

IN

REC

GAIN

V+

IN

R

LL

2V

|IIN|

C

LOG AV

AV

V–

1kΩ

THRESH

1.5MΩ

V–

V+

V

T

R

T

39kΩ

R

CON

PV

TO +V

C

OR –V

OUT

200Ω

C

+

VT < 0V

CON

V

–

V–

*

VT = 0

LOWER LIMITS CAN
BE ESTABLISHED BY
VALUES OF R

*

, RESPECTIVELY

R

LL

VIN – dB

>

0

T

*UPPER AND

AND

PV

a. Control Circuit b. Typical Compandor Control Curves

Figure 8. Compandor Control Circuit and Typical Curves

MONO

OR R

EXPANSION

– dB

OUT

V

THRESHOLD

THRESHOLD EXP.

L

FIGURE 6

THRESHOLD COM.

FIGURE 7

200Ω

200Ω

+V

C

–V

C

*

COMPRESSION

THRESHOLD

VIN – dB

a. Control Circuit b. Input/Output Curve

Figure 9. Control Circuit for Stereo Compressor/Limiter with Noise Gating and Input/Output Curve

–6–

REV. C

SSM2120/SSM2122

1kΩ

10pF

36Ω

TRANSMISSION

OR

STORAGE

MEDIUM

V+

R

C

39kΩ

10kΩ

V–

SIGNAL

INPUT

36kΩ

1µF

10kΩ

47Ω

REC

2200pF

IN

200Ω

200Ω

|IIN|

1µF

+V

–V

C

C

V+

LOG AV

4.7MΩ

V–

Figure 10. Companding Noise Rejection System

signal will be dependent on the noise of the current-to-voltage
converter amplifier if the expansion ratio is high enough.

As discussed in the Threshold Control section, the use of the
control circuit of Figure 6, including the R

to V+ and two

PV

diodes, yields positive unipolar control outputs.

COMPANDING NOISE REDUCTION SYSTEM

A complete companding noise reduction system is shown in
Figure 10. Normally, to obtain an overall gain of unity, the
value of R

is equal to RE. The values of R

C

will determine the

C/E

compression/expansion ratio.
Table II shows compression/expansion ratios ranging from 1.5:1

to full limiting with the corresponding values of R

C/E

.

An example of a 2:1 compression/expansion ratio is plotted in
Figure 11. Note that signal compression increases gain for low
level signals and reduces gain for high levels while expansion
does the reverse. The net result for the system is the same as the
original input signal except that it has been compressed before
being sent to a given medium and expanded after recovery. The
compression/expansion ratio needed depends on the medium

1kΩ

10pF

36kΩ

SIGNAL
OUTPUT

V+

R

E

39kΩ

10kΩ

V–

36kΩ

1µF

10kΩ

47Ω

REC

2200pF

IN

200Ω

200Ω

|IIN|

1µF

–V

+V

C

C

V+

LOG AV

4.7MΩ

V–

being used. As an extreme example, a household tape player
would require a higher compression/expansion ratio than a
professional stereo system.

20

I

≈ 3µA

REF

= 4.7MΩ

R

REF

0

–20

–40

OUTPUT SIGNAL LEVEL – dB

–60

–80

–80 20–60

INPUT SIGNAL LEVEL – dB

OVERALL

RESPONSE

2:1

EXPANSION

2:1
COMPRESSION

–40 –20 0

25dB

Figure 11. Companding Noise Reduction with 2:1
Compression/Expansion Ratio

Table II.

Gain Compressor Expander

(Reduction Only Only
Input Signal or Increase) Output Signal Output Signal Compression/ DV
Increase (dB) (dB) Increase (dB) Increase (dB) Expansion Ratio R

V (mV/dB)

C/E

20 6.67 13.33 22.67 1.5:1 11,800 2.0
20 10.00 10.00 30.00 2:1 7,800 3.0
20 13.33 6.67 33.33 3:1 5,800 4.0
20 15.00 5.00 35.00 4:1 5,133 4.5
20 16.00 4.00 36.00 5:1 4,800 4.8
20 17.33 2.67 37.33 7.5:1 4,415 5.2
20 18.00 2.00 38.00 10:1 4,244 5.4
20 20.00 0 40.00 AGC*/Limiter 3,800 6.0

*AGC for Compression Only.

REV. C

–7–

CONTROL

–

SSM2120/SSM2122

DYNAMIC FILTER

Figure 12 shows a control circuit for a dynamic filter capable of
single ended (nonencode/decode) noise reduction. Such circuits
usually suffer from a loss of high frequency content at low signal
levels because their control circuits detect the absolute amount
of highs present in the signal. This circuit, however, measures
wideband level as well as high frequency band level to produce
a composite control signal combined in a 1:2 ratio respectively.
The upper detector senses wideband signals with a cutoff of
20 Hz while the lower detector has a 5 kHz cutoff to sense only
high frequency band signals. This approach allows very good
noise masking with a minimum loss of “highs” when the signal
level goes below the threshold.

V+

THRESHOLD

AUDIO

INPUT

10kΩ

F

(WIDEBAND)

2.2µF

≤ 20Hz

C

REC

CONTROL

IN

|IIN|

9

LOG AV

3.3µF

2

1.5MΩ

160kΩ

V–

THRESH

1kΩ

39kΩ

CON

1

12kΩ

OUT

3

V–

3300pF

10kΩ

(HIGH FREQUENCY)

F

C

REC

= 5kHz

V–

V+

IN

|IIN|

15

LOG AV

3.3µF

V–

13

1.5MΩ

160kΩ

THRESH

1kΩ

39kΩ

12

36kΩ

CON

V–

OUT

14

2200pF

5.6kΩ

47Ω

200Ω

SIG
8

+V

5

C

IN

7

–V

C

200Ω

SIG

36kΩ

OUT

5

36kΩ

36kΩ

100pF

AUDIO
OUTPUT

Figure 12. Dynamic Noise Filter Circuit

–8–

REV. C

Figures 13a–c show the filter’s 3 dB frequency response with the

WIDEBAND SIGNAL LEVEL – dB

–50 –40 –30 –20 –10 0 10 20

20

HIGH-FREQUENCY SIGNAL LEVEL – dB

–20

–30

–40

–50

0

–10

10

1.5 2.2 3.1 4.2 4.2 4.2 4.2 4.2

4.9 7.1 10 10 10 10 10

15.1 22 22 22 22 22

48 49.2 49.2 49.2 49.2

50.6 50.6 50.6 50.6

50.6 50.6 50.6

50.6 50.6

50.6

WIDEBAND SIGNAL LEVEL – dB

–50 –40 –30 –20 –10 0 10 20

20

HIGH-FREQUENCY SIGNAL LEVEL – dB

–20

–30

–40

–50

0

–10

10

12.3 17.3 17.8 17.8 17.8 17.8 17.8 17.8

40 41 41 41 41 41 41

50.6 50.6 50.6 50.6 50.6 50.6

50.6 50.6 50.6 50.6 50.6

50.6 50.6 50.6 50.6

50.6 50.6 50.6

50.6 50.6

50.6

threshold potentiometer at V+, centered, and V–. Data was
taken by applying a 300 Hz signal to the wideband detector and
a 20 kHz signal to the high-frequency band detector simultane­ously. These figures correspond to filter characteristics for
50 dB, 70 dB and 90 dB dynamic range program source
material, respectively. The system could thus treat signals from
anything ranging from 1/4" magnetic tape to high performance
compact disc players.

Note that in Figure 13a the control circuit is designed so that
the minimum cutoff frequency is about 1 kHz. This occurs as
the control circuit detects the noise floor of the source material.

Dynamic filtering limits the signal bandwidth to less than 1 kHz
unless enough highs are detected in the signal to cover the noise
floor in the mid- and high frequency range. In this case the filter
opens to pass more of the audio band as more highs are detected.
The filter’s bandwidth can extend to 50 kHz with a nominal
signal level at the input. At other signal levels with varying high
frequency content, the filter will close to the required band­width. Here, noise outside the band is removed while the
perceived noise is masked by other signals within the band.
Even in this system, however, a certain amount of mid- and high
frequency components will be lost, especially during transients
at very low signal levels. This circuit does not address low
frequency noise such as “hum” and “rumble.”

SSM2120/SSM2122

20

10

0

–10

–20

–30

–40

HIGH-FREQUENCY SIGNAL LEVEL – dB

–50

1.0 1.0 1.2 1.7 2.4 2.4 2.4

1.0 1.0 1.0 1.0 1.0 1.1 1.1 1.1

–50 –40 –30 –20 –10 0 10 20

6 8.3 11.7 11.7 11.7

1.9 2.75 3.9 5.5 5.5 5.5

WIDEBAND SIGNAL LEVEL – dB

a. V

THRESH

at V+

50.6

50.6 50.6

50.6 50.6 50.6

17.8 26 26 26

b. V

c. V

THRESH

THRESH

Centered

at V–

Figure 13. 3 dB Filter Response

REV. C

–9–

SSM2120/SSM2122

+20

–30

–40

–50

–60

+20

–30

–45

–60

–75

INPUT – dB

OUTPUT – dB

V+

THRESHOLD

SIGNAL

INPUT

R

IN1

FC ≤ 20Hz

R

IN2

F

= 5Hz

C

REC

REC

IN

IN

IN |IIN|

C

AV1

IN |IIN|

C

AV2

V+

LOG AV

1.5MΩ

V–

V+

LOG AV

1.5MΩ

V–

160kΩ

1kΩ

160kΩ

1kΩ

36kΩ

Figure 14. Dynamic Filter with Downward Expander

DYNAMIC FILTER WITH DOWNWARD EXPANDER

A composite single-ended noise reduction system can be
realized by a combination of dynamic filtering and a downward
expander. As shown in Figure 14, the output from the wideband
detector can also be connected to the +V

control port of the

C

second VCA which is connected in series with the sliding filter.
This will act as a downward expander with a threshold that
tracks that of the filter. Although both of these techniques are
used for noise reduction, each alone will pass appreciable
amounts of noise under some conditions. When used together,
both contribute distinct advantages while compensating for each
other’s deficiencies.

Downward expansion uses a VCA controlled by the level
detector. This section maintains dynamic range integrity for all
levels above the user adjustable threshold level. As the input
level decreases below the threshold, gain reduction occurs at an
increasing rate (see Figure 15). This technique reduces audible
noise in fade outs or low level signal passages by keeping the
standing noise floor well below the program material.

This technique by itself is less effective for signals with
predominantly low frequency content such as a bass solo where
wideband frequency noise would be heard at full level. Also,
since the level detector has a time constant for signal averaging,
percussive material can modulate the noise floor causing a
“pumping” or “breathing” effect.

39kΩ

V–

39kΩ

200Ω

+V

C

–V

C

200Ω

DOWNWARD EXPANDER

36kΩ

36kΩ

100pF

36kΩ

36kΩ

SIGNAL
OUTPUT

CON

V–

V–

2200pF

OUT

CON

47Ω

OUT

12kΩ

5.6kΩ

200Ω

+V

–V

200Ω

2200pF

C

C

12kΩ

47Ω

36kΩ

The dynamic filter and downward expander techniques used
together can be employed more subtly to achieve a given level of
noise reduction than would be required if used individually. Up
to 30 dB of noise reduction can be realized while preserving the
crisp highs with a minimum of transient side effects.

Figure 15. Typical Downward Expander I/O Characteristics
at –30 dB Threshold Level (1:1.5 Ratio)

–10–

REV. C

SSM2120/SSM2122

FADER AUTOMATION

The SSM2120 can be used in fader automation systems to serve
two channels. The inverting control port is connected through
an attenuator to the VCA control voltage source. The noninverting
control port is connected to a control circuit (such as Figure 6)
which senses the input signal level to the VCA. Above the
threshold voltage, which can be set quite low (for example
–60 dBV), the VCA operates at its programmed gain. Below
this threshold the VCA will downward expand at a rate deter­mined by the +V

control port attenuator. By keeping the release

C

time constant in the 10 ms to 25 ms range, the modulation of
the VCA standing noise floor (–80 dB at unity-gain), can be
kept inaudibly low.

10pF

SIG

SIG

OUT 1

–V

IN 1

36kΩ

1/2

TL082

V+

50kΩ

*

V–

C1

36kΩ

2000pF

47Ω

220kΩ

V+

200Ω

200Ω

0.1µF

150kΩ

–15V

1

2

3

4

SSM2122

5

6

7

8

*

OPTIONAL CONTROL FEEDTHROUGH TRIM

The SSM2300 8-channel multiplexed sample-and-hold IC
makes an excellent controller for VCAs in automation systems.

Figure 16 shows the basic connection for the SSM2122 operating
as a unity-gain VCA with its noninverting control ports grounded
and access to the inverting control ports. This is typical for fader
automation applications. Since this device is a pinout option of
the SSM2120, the VCAs will behave exactly as described
earlier in the VCA section.

The SSM2122 can also be used with two or more op amps to
implement complex voltage-controlled filter functions. Biquad
and state-variable two-pole filters offering low pass, bandpass
and high pass outputs can be realized. Higher order filters can
also be formed by connecting two or more such stages in series.

+15V

0.1µF

16

15

14

200Ω

13

220kΩ

12

200Ω

11

10

9

10pF

36kΩ

1/2

TL082

2000pF

47Ω

36kΩ

SIG

50kΩ

OUT 2

*

–V

C2

SIG

IN 2

V+

V–

Figure 16. SSM2122 Basic Connection (Control Ports at 0 V)

REV. C

–11–

SSM2120/SSM2122

0.210 (5.33)

0.160 (4.06)

0.115 (2.93)

0.210

(5.33)

MAX

0.160 (4.06)

0.115 (2.93)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

16-Pin Plastic DIP

(N-16)

0.840 (21.33)

0.745 (18.93)

16

18

PIN 1

MAX

0.022 (0.558)

0.014 (0.356)

0.100
(2.54)

BSC

9

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.130
(3.30)
MIN

0.070 (1.77)

0.045 (1.15)

SEATING
PLANE

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

22-Pin Plastic DIP

(N-22)

1.080 (27.43)

1.020 (25.91)

22

111

PIN 1

0.022 (0.558)

0.014 (0.356)

0.100
(2.54)

BSC

12

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.070 (1.77)

0.045 (1.15)

SEATING
PLANE

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

C2088–2–11/95

0.195 (4.95)

0.115 (2.93)

0.195 (4.95)

0.115 (2.93)

–12–

PRINTED IN U.S.A.

REV. C