Datasheet ssg6680 Datasheet

Page 1
SSG6680
Elektronische Bauelemente
N-Channel Enhancement Mode Power Mos.FET
RoHS Compliant Product
Description
The SSG6680 provide the designer with the best combination of fast switching,
The SOP-8 is universally preferred for all commercial industrial surface mount application and suited for low voltage applications such as DC/DC converters.
Features
* Surface Mount Package * High Vgs Max. Rating Voltage
* Low On-Resistance
Date Code
11.5A, 30V,RDS(ON) 11m
SOP-8
0.40
0.90
6.20
5.80
0.25
1.27Typ.
0.35
0.49
D D D D
8
6
7
6680SC
Dimensions in millimeters
5
0.100.25
4.80
5.00
o
0
o
8
G
Ω
0.19
0.25
o
45
0.375 REF
3.80
4.00
1.35
1.75
D
Absolute Maximum Ratings
Parameter Symbol Ratings Unit
Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current
Pulsed Drain Current Total Power Dissipation Linear Derating Factor Operating Junction and Storage Temperature Range
3
3
1
Thermal Data
Parameter
Thermal Resistance Junction-ambient Max.
3
2
1
3
4
S S S G
VDS
VGS ID@TA=25 ID@TA=7
IDM
PD@TA=25
o
C
o
0
C
o
C
30
±25
11.5
9.5
50
2.5
0.02
Tj, Tstg
-55~+150
Symbol Ratings Unit
Rthj-a
50
V V
A A
A
W / C
o
S
W
o
o
C
/W C
http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual
01-Jun-2002 Rev. A
Page 1 of 5
Page 2
SSG6680
11.5A, 30V,RDS(ON) 11m
Elektronische Bauelemente
Electrical Characteristics( Tj=25 C Unless otherwise specified)
Parameter Symbol Max.
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Gate Threshold Voltage
Gate-Source Leakage Current Drain-Source Leakage Current (Tj=25 ) Drain-Source Leakage Current (Tj=70
Static Drain-Source On-Resistance
Total Gate Charge
2
Gate-Source Charge
Gate-Drain ("Miller") Charge Turn-on Delay Time
2
Rise Time
Turn-off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
o
C
o
C
2
)
o
BVDSS
BVDS/ Tj
VGS(th)
IGSS
IDSS
RDS(ON)
Qg Qgs
Qgd
Td(ON)
Tr
(Off)
Td
T
f
Ciss
Coss
Crss
N-Channel Enhancement Mode Power Mos.FET
Min. Unit
30
_
1.0
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
Typ.
_
0.02
_
_
_
_
_
_
16.8
4.2 8
8.9
7.3
25.6
18.6
1450
285
180
_
_
3.0
±
100
1
25 11 18
_
_
_
_
_
_
_
_
_
_
V
o
V/
C
V
nA
uA
uA
Ω
m
nC
nS
pF
Ω
Test Condition
VGS=0V, ID=250uA
±
Ω
Ω
o
C
Reference to 25 , ID=1mA
VDS=VGS, ID=250uA
VGS= 25A
VDS=30V,VGS=0
VDS=24V,VGS=0
VGS=10V, ID=11.5A
VGS=4.5V, ID=9.5A
ID=11.5A VDS=15V VGS=5V
VDD=15V
ID=1A VGS=10V RG=5.5
RD=10
VGS=0V VDS=25V
f=1.0MHz
Forward Transconductance
Gfs
_
30
_
S
VDS=15V, ID=11.5A
Source-Drain Diode
Parameter Symbol Max.
≦
2
Is A
_ _
≦
Forward On Voltage VDS
Continuous Source Current (Body Diode)
Notes: 1.Pulse width limited by Max. junction temperature
2.Pulse width 300us, dutycycle 2%.
3.Surface mounted on 1 inch2 copper pad of FR4 board; 125 when mounted on min. copper pad.
http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual
01-Jun-2002 Rev. A
Typ. Test ConditionMin. Unit
°
C/W
__
1.3
1.92
V
IS=3 5. A,VGS=0V,Tj=25 C
VD=VG=0V, VS=1.3V
o
Page 2 of 5
Page 3
SSG6680
Elektronische Bauelemente
Characteristics Curve
Fig 1. Typical Output Characteristics
11.5A, 30V,RDS(ON) 11m
Ω
N-Channel Enhancement Mode Power Mos.FET
Fig 2. Typical Output Characteristics
Fig 3. On-Resistance v.s. Gate Voltage
Fig 4. Normalized On-Resistance
v.s. Junction Temperature
http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual
01-Jun-2002 Rev. A
Fig 5. Maximum Drain Current
v.s. Case Temperature
Fig 6. Type Power Dissipation
Page
3 of 5
Page 4
SSG6680
Ω
Elektronische Bauelemente
11.5A, 30V,RDS(ON) 11m
N-Channel Enhancement Mode Power Mos.FET
Fig 7. Maximum Safe Operating Area Fig 8. Effective Transient Thermal Impedance
Fig 9. Gate Charge Characteristics
Fig 11. Forward Characteristics of Reverse Diode
http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual
01-Jun-2002 Rev. A
Fig 10. Typical Capacitance Characteristics
Fig 12. Gate Threshold Voltage v.s.
Junction Temperature
Page 4 of 5
Page 5
SSG6680
11.5A, 30V,RDS(ON) 11m
Elektronische Bauelemente
N-Channel Enhancement Mode Power Mos.FET
Fig 13. Switching Time Circuit Fig 14. Switching Time Waveform
Ω
Fig 15. Gate Charge Circuit Fig 16. Gate Charge Waveform
http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual
01-Jun-2002 Rev. A
Page 5 of 5
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