Page 1
SSG4224
Elektronische Bauelemente
RoHS Compliant Product
Description
The SSG
ruggedized device design, low on-resistance and cost-effectiveness.
4224
provide the designer with the best combination of fast switching,
Features
* Dual N MOSFET Package
* Simple Drive Requirement
* Low On-Resistance
D1 D1 D2 D2
8
7
10A,30V,RDS(ON) 14m
Ω
N-Channel Enhancement Mode Power Mos.FET
SOP-8
0.19
0.25
0.40
0.90
6.20
5.80
0.25
1.27Typ.
0.35
0.49
Dimensions in millimeters
5
6
D1
0.100.25
4.80
5.00
o
45
0.375 REF
3.80
4.00
1.35
o
1.75
0
o
8
D2
Date Code
Absolute Maximum Ratings
Parameter Symbol Ratings Unit
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Continuous Drain Current
Pulsed Drain Current
Total Power Dissipation
Linear Derating Factor
Operating Junction and Storage Temperature Range
3
3
1
4
224
SS
2
1
S1 G1 S2 G2
3
DS
V
VGS
ID@TA=25
ID@TA=70
DM
I
PD@TA=25
Tj, Tstg
G1
4
S1
30
±20
o
C
o
C
10
8
30
o
C
2
0.016
-55~+150
G2
S2
V
V
A
A
A
W / C
W
o
o
C
Thermal Data
Parameter
Thermal Resistance Junction-ambient Max.
http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual
01-Jun-2002 Rev. A
3
Symbol Ratings Unit
o
Rthj-a
62.5
/W C
Page 1 of 4
Page 2
SSG4224
10A,30V,RDS(ON) 14m
Elektronische Bauelemente
Electrical Characteristics( Tj=25 C Unless otherwise specified)
Parameter Symbol Max.
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Gate Threshold Voltage
Gate-Source Leakage Current
o
Drain-Source Leakage Current (Tj=25 )
Drain-Source Leakage Current (Tj=70
Static Drain-Source On-Resistance
Total Gate Charge
2
Gate-Source Charge
Gate-Drain ("Miller") Charge
Turn-on Delay Time
2
Rise Time
Turn-off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
C
o
C
)
2
o
BVDSS
BVDS/ Tj
VGS(th)
IGSS
IDSS
RDS(ON)
Qg
Qgs
Qgd
Td(ON)
Tr
(Off)
Td
T
f
Ciss
Coss
Crss
N-Channel Enhancement Mode Power Mos.FET
Min. Unit
30
_
1.0
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
Typ.
_
0.0
3
_
_
_
_
_
_
23
6
14
12
8
34
16
1910
400
280
_
_
3.0
±
100
1
25
14
20
15
_
_
_
_
_
3070
_
_
_
Ω
Test Condition
V
V/
V
nA
uA
uA
m
nC
nS
pF
VGS=0V, ID=250uA
o
Reference to 25 , ID=1mA
C
VDS=VGS, ID=250uA
±0
VGS= 2 V
VDS=30V,VGS=0
VDS=24V,VGS=0
VGS=10V, ID=10A
Ω
VGS=4.5V, ID=7A
ID=10A
VDS=24V
VGS=4.5V
VDD=15V
ID=1A
VGS=10V
Ω
RG=3.3
Ω
RD=15
VGS=0V
VDS=25V
f=1.0MHz
o
C
_
__
1.2
_
_
nC
S
Ω
V
nS
VDS=10V, ID=10A
f=1.0MHz
IS =1.7A, VGS=0V.Tj=25 C
=10A, VGS=0V.
IS
o
dl/dt=100A/us
Page 2 of 4
_
_
30
_
16
0.9
Typ. Test ConditionMin. Unit
__
24
Forward Transconductance
Gate Resistance
Source-Drain Diode
Parameter
Forward On Voltage VDS
Reverse Recovery Time
2
2
Reverse Recovery Charge
Symbol Max.
Gfs
Rg
Trr
Qrr
Notes: 1.Pulse width limited by safe operating area.
2.Pulse width 300us, dutycycle 2%.
3.Surface mounted on 1 inch2 copper pad of FR4 board
http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual
01-Jun-2002 Rev. A
≦
≦
O
C/W when mounted on min. copper pad.
; 135
Page 3
SSG4224
Elektronische Bauelemente
Characteristics Curve
Fig 1. Typical Output Characteristics
10A,30V,RDS(ON) 14m
Ω
N-Channel Enhancement Mode Power Mos.FET
Fig 2. Typical Output Characteristics
Fig 3. On-Resistance v.s. Gate Voltage
Fig 4. Normalized On-Resistance
v.s. Junction Temperature
http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual
01-Jun-2002 Rev. A
Fig 5. Forward Characteristics of
Reverse Diode
Fig 6. Gate Threshold Voltage v.s.
Junction Temperature
Page 3 of 4
Page 4
SSG4224
Ω
Elektronische Bauelemente
10A,30V,RDS(ON) 14m
N-Channel Enhancement Mode Power Mos.FET
Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics
Fig 9. Maximum Safe Operating Area
Fig 11. Switching Time Waveform
http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual
01-Jun-2002 Rev. A
Fig 10. Effective Transient Thermal Impedance
Fig 12. Gate Charge Waveform
Page 4 of 4
Loading...