Page 1
r
Elektronische Bauelemente
RoHS Compliant Product
A suffix of “-C” specifies halogen free
N-Ch Enhancement Mode Power MOSFET
DESCRIPTION
These miniature surface mount MOSFETs utilize a high cell density trench
process to provide low R
and to ensure minimal power loss and heat dissipation.
DS(on)
Typical applications are DC-DC converters and power management in portable
And battery-powered products such as computers, printers, PCMCIA cards,
cellular and cordless telephones.
FEATURES
Low R
Low thermal impedance copper leadframe DPAK saves board space.
Fast switching speed.
High performance trench technology.
provides higher efficiency and extends battery life.
DS(on)
PRODUCT SUMMARY
PRODUCT SUMMARY
I
V
(V) R
DS
40
(on) m(
DS
12@V
= 10V 53
GS
14@VGS= 4.5V 49
D
(A)
Gate
SSD60N04-12D
53A, 40V, R
Drain
Source
12mΩ
DS(ON)
TO-252(D-Pack)
A
B
G E
FHK
M
J
Millimeter
REF.
Min. Max. Min. Max.
A 6.4 6.8 J 2.30 REF.
B 5.20 5.50 K 0.70 0.90
C 2.20 2.40 M 0.50 1.1
D 0.45 0.58 N 0.9 1.6
E 6.8 7.3 O 0 0.15
F 2.40 3.0 P 0.43 0.58
G 5.40 6.2
H 0.8 1.20
REF.
Millimete
C
D
N
O
P
ABSOLUTE MAXIMUM RATINGS (T
= 25°C unless otherwise specified)
A
PARAMETER SYMBOL RATINGS UNIT
Drain-Source Voltage VDS 40 V
Gate-Source Voltage VGS ±20 V
Continuous Drain Current
Pulsed Drain Current
Continuous Source Current (Diode Conduction) a I
Total Power Dissipation a P
Operating Junction and Storage Temperature Range TJ, T
a
I
b
IDM 40 A
@T
=25℃ 53 A
D
A
30 A
S
=25℃ 50 W
D @TA
-55 ~ 175 °C
STG
THERMAL RESISTANCE RATINGS
Maximum Thermal Resistance Junction-Ambient a R
Maximum Thermal Resistance Junction-Case R
50 °C / W
θJA
3.0 °C / W
θJC
Notes：
a. Surface Mounted on 1” x 1” FR4 Board.
b. Pulse width limited by maximum junction temperature.
http://www.SeCoSGmbH.com/ Any changes of specification will not be informed individually.
10-Jun-2010 Rev.A Page 1 of 2
Page 2
Elektronische Bauelemente
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise specified)
A
N-Ch Enhancement Mode Power MOSFET
SSD60N04-12D
53A, 40V, R
DS(ON)
12mΩ
PARAMETER
SYMBO
MIN. TYP. MAX. UNIT TEST CONDITIONS
Static
Gate-Threshold Voltage V
Gate-Body Leakage I
Zero Gate Voltage Drain Current I
On-State Drain Current a I
Drain-Source On-Resistance a R
Forward Transconductance a g
Diode Forward Voltage V
GS(th)
GSS
DSS
D(on)
DS(ON)
fs
SD
Total Gate Charge Qg - 4.0 -
Gate-Source Charge Qgs - 1.1 -
Gate-Drain Charge Qgd - 1.4 -
1.0 - - V VDS= V
- - ±100 nA VDS = 0V, VGS= 20V
- - 1
- - 25 VDS= 32V, VGS= 0V, TJ=55°C
34 - - A VDS = 5V, VGS= 10V
- - 12
mΩ
- - 14 VGS= 4.5V, ID= 49 A
- 22 - S VDS= 15V, ID= 53 A
- 1.1 - V IS= 34 A, VGS= 0 V
Dynamic
b
VDS= 32V, VGS= 0V
μA
= 10V, ID= 53 A
V
GS
V
= 15 V
nC
DS
VGS = 4.5 V
I
= 53 A
D
GS, ID
= 250 μA
Turn-on Delay Time T
- 16 -
d(on)
Rise Time Tr - 5 -
Turn-off Delay Time T
- 23 -
d(off)
Fall Time Tf - 3 -
Notes
a. Pulse test：Pulse width ≦ 300 μs, duty cycle ≦ 2％.
b. Guaranteed by design, not subject to production testing.
nS
V
= 25 V
DD
I
= 34 A
D
V
GEN
= 25
R
L
= 10 V
http://www.SeCoSGmbH.com/ Any changes of specification will not be informed individually.
10-Jun-2010 Rev.A Page 2 of 2
Loading...