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Elektronische Bauelemente
RoHS Compliant Product
A suffix of “-C” specifies halogen free
DESCRIPTION
These miniature surface mount MOSFETs utilize high
cell density process. Low R
assures minimal power
DS(on)
loss and conserves energy, making this device ideal for
use in power management circuitry. Typical applications
are PWMDC-DC converters, power management in
portable and battery-powered products such as computers,
printers, battery charger, telecommunication power system,
and telephones power system.
FEATURES
Low R
battery life.
Miniature TO-252 surface mount package saves board
space.
High power and current handling capability.
Extended V
provides higher efficiency and extends
DS(on)
range (±25) for battery pack applications.
GS
PACKAGE INFORMATION
Package MPQ LeaderSize
TO-252 2.5K 13’ inch
SSD50P03-09D
61A, -30V, R
P-Ch Enhancement Mode Power MOSFET
M
REF.
A 6.4 6.8 J 2.30 REF.
B 5.20 5.50 K 0.70 0.90
C 2.20 2.40 M 0.50 1.1
D 0.45 0.58 N 0.9 1.6
E 6.8 7.3 O 0 0.15
F 2.40 3.0 P 0.43 0.58
G 5.40 6.2
H 0.8 1.20
9mΩ
DS(ON)
TO-252(D-Pack)
A
B
G E
FHK
J
Millimeter
Min. Max. Min. Max.
REF.
C
D
N
O
P
Millimete
Gate
Drain
ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise specified)
Source
PARAMETER SYMBOL RATINGS UNIT
Drain-Source Voltage VDS -30 V
Gate-Source Voltage VGS ±25 V
Continuous Drain Current
Pulsed Drain Current
Continuous Source Current (Diode Conduction) 1 I
Total Power Dissipation 1 P
Operating Junction and Storage Temperature Range TJ, T
1
I
2
IDM ±40 A
@T
=25℃ 61 A
D
A
-30 A
S
=25℃ 50 W
D @TA
-55 ~ 175 °C
STG
THERMAL RESISTANCE RATINGS
Maximum Thermal Resistance Junction-Ambient 1 R
Maximum Thermal Resistance Junction-Case R
Notes：
1 Surface Mounted on 1” x 1” FR4 Board.
2 Pulse width limited by maximum junction temperature.
http://www.SeCoSGmbH.com/ Any changes of specification will not be informed individually.
50 °C / W
θJA
3.0 °C / W
θJC
02-Dec-2010 Rev.A Page 1 of 2
Page 2
Elektronische Bauelemente
ELECTRICAL CHARACTERISTICS (T
P-Ch Enhancement Mode Power MOSFET
= 25°C unless otherwise specified)
A
SSD50P03-09D
61A, -30V, R
DS(ON)
9mΩ
PARAMETER
SYMBO
MIN. TYP. MAX. UNIT TEST CONDITIONS
Static
Gate-Threshold Voltage V
Gate-Body Leakage I
Zero Gate Voltage Drain Current I
On-State Drain Current 1 I
Drain-Source On-Resistance 1 R
Forward Transconductance 1 g
Diode Forward Voltage V
GS(th)
- - ±100 nA VDS = 0V, VGS= ±25V
GSS
DSS
D(on)
DS(ON)
fs
SD
Total Gate Charge Qg - 37 -
Gate-Source Charge Qgs - 10 -
Gate-Drain Charge Qgd - 14.5 -
-1 - - VDS= V
- - -1
- - -5 VDS= -24V, VGS=0V, TJ=55°C
-41 - - A VDS = -5V, VGS= -10V
- - 9
mΩ
- - 13 VGS= -4.5V, ID= -51A
- 31 - S VDS= -15V, ID= -61A
- -0.7 - V IS= -41 A, VGS= 0 V
Dynamic
2
VDS= -24V, VGS= 0V
μA
= -10V, ID= -61A
V
GS
V
= -15 V
nC
DS
VGS = -4.5 V
I
= -61 A
D
GS, ID
= -250 μA
Switching
Turn-on Delay Time T
Rise Time Tr - 12 -
Turn-off Delay Time T
Fall Time Tf - 46 -
Notes
1 Pulse test：Pulse width ≦ 300 μs, duty cycle ≦ 2％.
2 Guaranteed by design, not subject to production testing.
- 15 -
d(on)
- 62 -
d(off)
nS
V
= -15 V
DD
= -41 A
I
D
V
= -10 V
GEN
R
= 15
L
RG= 6
http://www.SeCoSGmbH.com/ Any changes of specification will not be informed individually.
02-Dec-2010 Rev.A Page 2 of 2
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