Datasheet SSD1851Z, SSD1851U, SSD1851TR1, SSD1850Z Datasheet (Solomon Systech)

Table of Content

LCD SEGMENT / COMMON DRIVER WITH CONTROLLER ..................................................................................1

FEATURES ................................................................................................................................................................1

ORDERING INFORMATION ......................................................................................................................................2

BLOCK DIAGRAM.....................................................................................................................................................3

TAB PAD ARRAGEMENT (SSD1851T PIN ASSIGNMENT) ..................................................................................4

COF PAD ARRAGEMENT (SSD1851U PIN ASSIGNMENT) ...................................................................................5

DIE PAD ARRAGEMENT (SSD1850Z DIE PIN ASSIGNMENT) ..............................................................................6

DIE PAD ARRANGEMENT (SSD1851Z DIE PIN ASSIGNMENT) ...........................................................................7

PIN DESCRIPTIONS................................................................................................................................................11

RES ....................................................................................................................................................................11

PS0, PS1 .............................................................................................................................................................11

CS .......................................................................................................................................................................11

D/ C .....................................................................................................................................................................11

R/W( WR ) ..........................................................................................................................................................11

D0-D7 ..................................................................................................................................................................11

INTRS..................................................................................................................................................................11

REF .....................................................................................................................................................................11

VDD .....................................................................................................................................................................11

VSS .....................................................................................................................................................................12

VCI.......................................................................................................................................................................12

VCC .....................................................................................................................................................................12

C1P, C2P, C3P, C4P, C5P, C1N and C2N ........................................................................................................12

VL6 ......................................................................................................................................................................12

This document contains information on a new product. Specification and information herein are subject to change without notice.

Copyright  2003 SOLOMON Systech Limited

Rev 1.2 01/2003

VR........................................................................................................................................................................12

VEXT ...................................................................................................................................................................12

VL5, VL4, VL3 and VL2......................................................................................................................................12

COM0 - COM79...................................................................................................................................................12

ICONS .................................................................................................................................................................12

SEG0 - SEG127 ..................................................................................................................................................13

S5150 ..................................................................................................................................................................13

CL........................................................................................................................................................................13

N/C ......................................................................................................................................................................13

FUNCTIONAL BLOCK DESCRIPTIONS ................................................................................................................14

Command Decoder and Command Interface .................................................................................................14

MPU Parallel 6800-series Interface ..................................................................................................................14

MPU Parallel 8080-series interface ..................................................................................................................14

MPU Serial 4-wire Interface ..............................................................................................................................15

MPU Serial 3-wire Interface ..............................................................................................................................15

Modes of operation ...........................................................................................................................................15

Graphic Display Data RAM (GDDRAM) ...........................................................................................................15

Oscillator Circuit................................................................................................................................................18

LCD Driving Voltage Generator and Regulator ..............................................................................................18

193 / 209 Bit Latch .............................................................................................................................................19

Level Selector ....................................................................................................................................................19

HV Buffer Cell (Level Shifter) ...........................................................................................................................19

Reset Circuit ......................................................................................................................................................20

LCD Panel Driving Waveform...........................................................................................................................21

COMMAND TABLE ............................................................................................................................................22

Extended Command Table ...............................................................................................................................25

Frame Frequency Default Setting ....................................................................................................................26

This document contains information on a new product. Specification and information herein are subject to change without notice.

Copyright  2003 SOLOMON Systech Limited

Rev 1.2 01/2003

Read Status Byte...............................................................................................................................................27

Data Read / Write ...............................................................................................................................................27

Address Increment Table (Automatic) ............................................................................................................27

Commands Required for R/W( WR ) Actions on RAM ..................................................................................27

COMMAND DESCRIPTIONS ..................................................................................................................................28

Set Display On/Off .............................................................................................................................................28

Set Display Start Line .......................................................................................................................................28

Set Page Address ..............................................................................................................................................28

Set Lower Column Address .............................................................................................................................28

Set Segment Re-map ........................................................................................................................................28

Set Normal/Inverse Display ..............................................................................................................................28

Set Entire Display On/Off..................................................................................................................................28

Set LCD Bias ......................................................................................................................................................28

Software Reset...................................................................................................................................................28

Set COM Output Scan Direction ......................................................................................................................28

Set Power Control Register ..............................................................................................................................29

Set Internal Regulator Resistors Ratio ...........................................................................................................29

Set Contrast Control Register..........................................................................................................................29

Set Display Offset..............................................................................................................................................29

Set Multiplex Ratio ............................................................................................................................................30

Set Power Save Mode .......................................................................................................................................30

Exit Power Save Mode ......................................................................................................................................30

Set N-line Inversion ...........................................................................................................................................30

Exit N-line Inversion ..........................................................................................................................................30

Set DC-DC Converter Factor ............................................................................................................................30

Set Icon Enable..................................................................................................................................................30

Start Internal Oscillator.....................................................................................................................................30

This document contains information on a new product. Specification and information herein are subject to change without notice.

Copyright  2003 SOLOMON Systech Limited

Rev 1.2 01/2003

Set Display Data Length ...................................................................................................................................30

Set Gray Scale Mode (White/Light Gray/Dark Gray/Black) ...........................................................................30

Set PWM and FRC .............................................................................................................................................31

Set Test Mode ....................................................................................................................................................31

Status Register Read ........................................................................................................................................31

EXTENDED COMMANDS ..................................................................................................................................31

Set VL6 noise reduction ...................................................................................................................................31

Set Temperature Coefficient (TC) Value..........................................................................................................31

Select Oscillator Source ...................................................................................................................................31

Oscillator adjustment........................................................................................................................................31

Lock/Unlock Interface .......................................................................................................................................31

MAXIMUM RATINGS ...............................................................................................................................................32

ELECTRICAL CHARACTERISTICS .......................................................................................................................32

AC ELECTRICAL CHARACTERISTICS .................................................................................................................34

APPLICATION CIRCUIT..........................................................................................................................................41

Application Circuit: DC-DC Converter Circuit Configuration .......................................................................42

Application Circuit: Regulator Circuit and Bias Divider Circuit ...................................................................43

Internal Regulator and Bias Divider ................................................................................................................43

External Regulator and Internal Bias Divider .................................................................................................43

External Regulator Bias Divider.......................................................................................................................43

OTP Programming Circuit and Sequence.......................................................................................................44

Flow Chart of OTP Program .............................................................................................................................45

OTP Example program......................................................................................................................................46

SSD1851T TAB PACKAGE DIMENSION .........................................................................................................47

SSD1851U COF PACKAGE DIMENSION ........................................................................................................50

This document contains information on a new product. Specification and information herein are subject to change without notice.

Copyright  2003 SOLOMON Systech Limited

Rev 1.2 01/2003

SOLOMON SYSTECH LIMITED

SOLOMON SYSTECH LIMITEDSOLOMON SYSTECH LIMITED

SEMICONDUCTOR TECHNICAL DATA

SSD1850/51

Advance Information

CMOS

LCD Segment / Common Driver with Controller

SSD1850/51 is a single-chip CMOS LCD driver with controller for liquid crystal dot-matrix graphic display system. SSD1850 consists of 194 high voltage driving output pins for driving 128 Segments and 64 Commons and 1 icon line. SSD1851 consists of 210 high voltage driving output pins for driving 128 Segments and 80 Commons and 1 icon line.

SSD1850/51 display data directly from their internal 128x65x2 / 128x81x2 bits Graphic Display Data RAM (GDDRAM). Data/Commands are sent from general MCU through hardware selectable 6800/8080-series compatible Parallel Interface or 3/4 wires Serial Peripheral Interface.

SSD1850/51 embeds a DC-DC Converter, a LCD Voltage Regulator, an On-Chip Bias Divider and an On-Chip Oscillator which reduce the number of external components. With the special design on minimizing power consumption and die/package layout, SSD1850/51 is suitable for any portable batterydriven applications requiring long operation period and compact size.

FEATURES

128x64/80 + 1 icon line, 4 gray-levels Graphic Display Programmable Multiplex ratio [16Mux - 65Mux/81Mux] Single Supply Operation, 1.8 V - 3.3V Low Current Sleep Mode(<1.0 uA) On-Chip Voltage Generator / External Power Supply Software selectable 2X / 3X / 4X / 5X / 6X On-Chip DC-DC Converter On-Chip Oscillator On-Chip Bias Dividers Programmable 1/4, 1/5, 1/6, 1/7, 1/8, 1/9 and 1/10 bias ratio Maximum +15.0V LCD Driving Output Voltage Hardware pin selectable for 8-bit 6800-series Parallel Interface, 8-bit 8080-series Parallel Interface, 3-wire Serial Peripheral Interface or 4-wire Serial Peripheral Interface On-Chip 128x65x2 / 128x81x2 Graphic Display Data RAM Re-mapping of Row and Column Drivers Vertical Scrolling Display Offset Control 64 Level Internal Contrast Control External Contrast Control Maximum 15MHz SPI or 10MHz PPI (8 bit) operation Selectable LCD Driving Voltage Temperature Coefficients (2 settings) Available in Gold Bump Die, Standard TAB (Tape Automated Bonding) Package and COF (Chip On Foil)

This document contains information on a new product. Specification and information herein are subject to change without notice.

Copyright  2002 SOLOMON Systech Limited

Rev 1.2 01/2003

ORDERING INFORMATION

Ordering Part

Number

SSD1850Z 128 64 + 1 1/9 Gold Bump Die SSD1851Z 128 80 + 1 1/10 Gold Bump Die

SSD1851TR1 128 80 + 1 1/10 TAB

SSD1851U 128 80 + 1 1/10 COF

SEG COM Default Bias Package Form Reference

2

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

BLOCK DIAGRAM

ICONS

ROW0 to ROW63 (SSD1850) ROW0 to ROW79 (SSD1851)

SEG0 ~SEG127

HV Buffer Cell Level Shifter

Level

Selector

VL6 VL5 VL4 VL3 VL2

V

R

V

CC

C1P C2P C3P C4P C5P C1N C2N

REF INTRS

V

CI

V

EXT

CL

V

SS

Display Timing

Generator

Oscillator

193 Bit Latch (SSD1850)

209 Bits Latch (SSD1851)

GDDRAM

128 x 65 x 2 Bits (SSD1850)

128 x 81 x 2 Bits (SSSD1851)

LCD Driving Voltage Generator 2X/3X/4X/5X/ 6X DC/DC Converter, Voltage Regulator,

Bias Divider,

Contrast Control,

Temperature

Compensation

Command Decoder

V

DD

SSD1850/51 Series

Command Interface

RES# PS0 PS1 CS# R/W E D/C

(WR#)(RD#)

Rev 1.2 01/2003

Parallel / Serial

Interface

D7 D6 D5 D4 D3 D2 D1 D0

(SDA)(SCK)

SOLOMON

3

TAB PAD ARRAGEMENT (SSD1851T PIN ASSIGNMENT) (Copper View)

N/C 1 CL 2 VR 3 VL6 4 VL5 5 VL4 6 VL3 7 VL2 8 INTRS 9 C4P 10 C2N 11 C2P 12 C1P 13 C1N 14 C3P 15 C5P 16 VCC 17 VSS 18 VCI 19 VDD 20 D7 21 D6 22 D5 23 D4 24 D3 25 D2 26 D1 27 D0 28 E(RD#) 29 R/W(WR#)30 D/C 31 RES# 32 CS# 33 PS1 34 PS0 35 N/C 36

247 NC 246 NC 245 COM39 244 COM38 243 COM37

209 COM1 208 COM0 207 ICONS 206 SEG0 205 SEG1

81 SEG125 80 SEG126 79 SEG127 78 COM40 77 COM41

42 COM76 41 COM77 40 COM78 39 COM79 38 ICONS 37 N/C

4

SSD1850/51 Series

Rev 1.2 01/2003

Remarks: REF is connected to VDD

VEXT is not connected

SOLOMON

COF PAD ARRAGEMENT (SSD1851U PIN ASSIGNMENT)(Copper View)

N/C

ICONS

COM79 COM41

COM40

SEG127

SEG126 SEG99

SE98

SEG97

SEG96 SEG55

SEG54

SEG53

SEG52 SEG2

SEG1

SEG0

ICONS

COM0

COM1 COM38

COM39

N/C

VSS

VDD

N/C

PS0

VDD

PS1

VSS

D7D6D5D4D3D2D1

GND

VDD

D0

E

D/C

CS#

GND

RES#

R/W(WR#)

Remarks:

REF is connected to VDD VEXT is not connected INTRS is connected to VDD VR is not connected Default Setting: PS0 and PS1 are connected to VDD (6800 Parallel Interface Mode)

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

5

N

X

N

DIE PAD ARRAGEMENT (SSD1850Z DIE PIN ASSIGNMENT)

/C N/C N/C N/C N/C N/C N/C N/C N/C N/C

COM29

COM30

COM31

Center: 5328.75, 84.3

132 131

Center: 5243.7, -522.3

COM17 COM16 COM15 COM14 COM13 COM12 COM11

COM5 COM4 COM3 COM2 COM1 COM0 ICONS

SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8

SEG9 SEG10 SEG11 SEG12 SEG13

157

N/C

COM18

COM19

COM20

COM21

156

Center: 5508.0, 765.0

X

Y

(0,0)

SEG112 SEG113 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 COM40 COM41 COM42 COM43 COM45 COM46 COM47 COM48 COM49 COM50

Center: -5508.0, 765.0

323 324

1

NC

COM51

COM52

COM53

COM54

COM55

COM62

COM63

Center: -5309.85, 522.3

347

N/C

ICONS

/C

NC NC NC CL VSS VR VR VL6 VL6 VL6 VL5 VL5 VL5 VL4 VL4 VL4 VL3 VL3 VL3 VL2 VL2 VL2 VSS C4P C4P C4P C2N C2N C2N C2N C2P C2P C2P C1P C1P C1P C1N C1N C1N C1N C3P C3P C3P N/C N/C N/C VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCI VCI VCI VCI VDD VDD VDD D7 D7 D6 D6 D5 D4 D3 D2 D1 D0 VDD E(RD#) E(RD#) R/W(/WR#) R/W(/WR#) VSS D/C D/C D/C RES# VDD CS# CS# VSS PS1 VDD VSS PS0 VDD S5150 VSS N/C N/C N/C N/C N/C

N/C

Center (-5243.7, -522.3) Size: 78.5 x 78.5

(-5508.0, 765.0)

ote:

5. The gold bumps face up in this diagram.

6. Coordinates reference to center of the chip.

7. All dimensions and coordinates in um.

8. All alignment keys do not contain gold bump.

Die Size: 12300um x 1960um

Die Thickness: 534um +/- 25 um Bump Height: Nominal 18 um Tolerance < 3 um within die

Center (5328.75, 84.3) Size: 78.5 x 78.5

SSD1850Z Die Pin Assignment DRAWING NOT SCALE

PIN #1

75 µm

Center (-5309.85, -522.3) Size: 78.5 x 78.5

75 µm

(5508.0, 765.0)

6

SSD1850/51 Series

Rev 1.2

SOLOMON

01/2003

N

X

N

DIE PAD ARRANGEMENT (SSD1851Z DIE PIN ASSIGNMENT)

/C

NC NC NC CL VSS VR VR VL6 VL6 VL6 VL5 VL5 VL5 VL4 VL4 VL4 VL3 VL3 VL3 VL2 VL2 VL2 VSS C4P C4P C4P C2N C2N C2N C2N C2P C2P C2P C1P C1P C1P C1N C1N C1N C1N C3P C3P C3P C5P C5P C5P VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCI VCI VCI VCI VDD VDD VDD D7 D7 D6 D6 D5 D4 D3 D2 D1 D0 VDD E(RD#) E(RD#) R/W(/WR#) R/W(/WR#) VSS D/C D/C D/C RES# VDD CS# CS# VSS PS1 VDD VSS PS0 VDD S5150 VSS N/C N/C N/C N/C N/C

N/C

Center (-5243.7, -522.3) Size: 78.5 x 78.5

75 µm

(-5508.0, 765.0)

ote:

1. The gold bumps face up in this diagram.

2. Coordinates reference to center of the chip.

3. All dimensions and coordinates in um.

4. All alignment keys do not contain gold bump.

Die Size: 12300um x 1960um

Die Thickness: 534um +/- 25 um Bump Height: Nominal 18 um Tolerance < 3 um within die

Center (5328.75, 84.3) Size: 78.5 x 78.5

SSD1851Z Die Pin Assignment DRAWING NOT SCALE

PIN #1

157 COM17 COM16 COM15 COM14 COM13 COM12 COM11

COM5 COM4 COM3 COM2 COM1 COM0 ICONS

SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8

SEG9 SEG10 SEG11 SEG12 SEG13

SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 COM32 COM33 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM56 COM57 COM58

SSD1850/51 Series

N/C

COM18

COM19

COM20

COM21 COM38

156

COM39

/C N/C

132 131

Center: 5508.0, 765.0

Center: 5328.75, 84.3

Center: 5243.7, -522.3

X

Y

(0,0)

Center: -5309.85, 522.3

Center: -5508.0, 765.0

323 324

1

NC

COM59

COM60

COM61

COM62

COM63

ICONS

COM78

COM79

Rev 1.2 01/2003

347

Center (-5309.85, -522.3) Size: 78.5 x 78.5

75 µm

(5508.0, 765.0)

SOLOMON

7

Table 1 - SSD1850/51 Die Pad Coordinates

Pad #

SSD 1851

1 N/C N/C -5698.05 -830.85 51 VSS VSS -1687.2 -863.55 101 C4P C4P 3016.05 -804.15 2 N/C N/C -5620.65 -830.85 52 VSS VSS -1611 -863.55 102 C4P C4P 3097.35 -804.15 3 N/C N/C -5543.25 -830.85 53 VSS VSS -1534.8 -863.55 103 VSS VSS 3173.55 -804.15 4 N/C N/C -5465.85 -830.85 54 VSS VSS -1458.6 -863.55 104 REF REF 3249.75 -804.15 5 N/C N/C -5355.68 -830.85 55 VSS VSS -1382.4 -863.55 105 VEXT VEXT 3366.45 -804.15 6 VSS VSS -5279.48 -830.85 56 VSS VSS -1306.2 -863.55 106 VDD VDD 3442.65 -804.15 7 S5150 S5150 -5203.28 -830.85 57 VSS VSS -1230 -863.55 107 INTRS INTRS 3518.85 -804.15 8 VDD VDD -5127.08 -830.85 58 VSS VSS -1153.8 -863.55 108 VSS VSS 3595.05 -804.15

9 PS0 PS0 -5050.88 -830.85 59 VSS VSS -1077.6 -863.55 109 VL2 VL2 3671.25 -804.15 10 VSS VSS -4974.68 -830.85 60 VSS VSS -1001.4 -863.55 110 VL2 VL2 3752.55 -804.15 11 VDD VDD -4898.48 -830.85 61 VSS VSS -925.2 -863.55 111 VL2 VL2 3833.85 -804.15 12 PS1 PS1 -4822.28 -830.85 62 VSS VSS -849 -863.55 112 VL3 VL3 3915.15 -804.15 13 VSS VSS -4746.08 -830.85 63 VSS VSS -772.8 -863.55 113 VL3 VL3 3996.45 -804.15 14 CS# CS# -4669.88 -830.85 64 VSS VSS -696.6 -863.55 114 VL3 VL3 4077.75 -804.15 15 CS# CS# -4593.68 -830.85 65 VSS VSS -620.4 -863.55 115 VL4 VL4 4159.05 -804.15 16 VDD VDD -4517.48 -830.85 66 VSS VSS -544.2 -863.55 116 VL4 VL4 4240.35 -804.15 17 RES# RES# -4441.28 -830.85 67 VSS VSS -468 -863.55 117 VL4 VL4 4321.65 -804.15 18 D/C D/C -4365.08 -830.85 68 VSS VSS -391.8 -863.55 118 VL5 VL5 4402.95 -804.15 19 D/C D/C -4288.88 -830.85 69 VSS VSS -315.6 -863.55 119 VL5 VL5 4484.25 -804.15 20 D/C D/C -4212.68 -830.85 70 VSS VSS -239.4 -863.55 120 VL5 VL5 4565.55 -804.15 21 VSS VSS -4136.48 -830.85 71 VSS VSS -163.2 -863.55 121 VL6 VL6 4646.85 -804.15

R/W

22

(WR#)

R/W

23

(WR#) 24 E(RD#) E(RD#) -3907.88 -830.85 74 VSS VSS 65.4 -863.55 124 VR VR 4926.15 -804.15 25 E(RD#) E(RD#) -3831.68 -830.85 75 VSS VSS 141.6 -863.55 125 VR VR 5002.35 -804.15 26 VDD VDD -3755.48 -830.85 76 VCC VCC 872.55 -804.15 126 VSS VSS 5078.55 -804.15 27 D0 D0 -3679.28 -830.85 77 VCC VCC 953.85 -804.15 127 CL CL 5154.75 -804.15 28 D1 D1 -3603.08 -830.85 78 VCC VCC 1035.15 -804.15 128 N/C N/C 5267.55 -830.85 29 D2 D2 -3526.88 -830.85 79 VCC VCC 1116.45 -804.15 129 N/C N/C 5344.95 -830.85 30 D3 D3 -3450.68 -830.85 80 C5P N/C 1197.75 -804.15 130 N/C N/C 5422.35 -830.85 31 D4 D4 -3374.48 -830.85 81 C5P N/C 1279.05 -804.15 131 N/C N/C 5974.20 -898.05 32 D5 D5 -3298.28 -830.85 82 C5P N/C 1360.35 -804.15 132 N/C N/C 5974.20 -665.25 33 D6 D6 -3222.08 -830.85 83 C3P C3P 1441.65 -804.15 133 N/C N/C 5974.20 -600.45 34 D6 D6 -3145.88 -830.85 84 C3P C3P 1522.95 -804.15 134 COM39 N/C 5974.20 -535.65 35 D7 D7 -3069.68 -830.85 85 C3P C3P 1604.25 -804.15 135 COM38 N/C 5974.20 -470.85 36 D7 D7 -2993.48 -830.85 86 C1N C1N 1685.55 -804.15 136 COM37 N/C 5974.20 -406.05 37 VDD VDD -2917.28 -830.85 87 C1N C1N 1766.85 -804.15 137 COM36 N/C 5974.20 -341.25 38 VDD VDD -2841.08 -830.85 88 C1N C1N 1848.15 -804.15 138 COM35 N/C 5974.20 -276.45 39 VDD VDD -2764.88 -830.85 89 C1N C1N 1929.45 -804.15 139 COM34 N/C 5974.20 -211.65 40 VCI VCI -2620.05 -804.15 90 C1P C1P 2066.25 -804.15 140 COM33 N/C 5974.20 -146.85 41 VCI VCI -2538.75 -804.15 91 C1P C1P 2147.55 -804.15 141 COM32 N/C 5974.20 -82.05 42 VCI VCI -2457.45 -804.15 92 C1P C1P 2228.85 -804.15 142 COM31 COM31 5974.20 -17.25 43 VCI VCI -2376.15 -804.15 93 C2P C2P 2310.15 -804.15 143 COM30 COM30 5974.20 47.55 44 VSS VSS -2266.35 -804.15 94 C2P C2P 2391.45 -804.15 144 COM29 COM29 5974.20 112.35 45 VSS VSS -2190.15 -804.15 95 C2P C2P 2472.75 -804.15 145 COM28 COM28 5974.20 177.15 46 VSS VSS -2113.95 -804.15 96 C2N C2N 2554.05 -804.15 146 COM27 COM27 5974.20 241.95 47 VSS VSS -2037.75 -804.15 97 C2N C2N 2635.35 -804.15 147 COM26 COM26 5974.20 306.75 48 VSS VSS -1961.55 -804.15 98 C2N C2N 2716.65 -804.15 148 COM25 COM25 5974.20 371.55 49 VSS VSS -1885.35 -804.15 99 C2N C2N 2797.95 -804.15 149 COM24 COM24 5974.20 436.35 50 VSS VSS -1763.4 -863.55 100 C4P C4P 2934.75 -804.15 150 COM23 COM23 5974.20 501.15

SSD

X-pos Y-pos Pad #

1850

R/W

-4060.28 -830.85 72 VSS VSS -87 -863.55 122 VL6 VL6 4728.15 -804.15

(WR#)

R/W

-3984.08 -830.85 73 VSS VSS -10.8 -863.55 123 VL6 VL6 4809.45 -804.15

(WR#)

SSD 1851

SSD

X-pos Y-pos Pad #

1850

SSD 1851

SSD 1850

X-pos Y-pos

8

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

Pad #

SSD 1851

151 COM22 COM22 5974.20 565.95 201 SEG25 SEG25 2494.80 788.55 251 SEG75 SEG75 -745.20 788.55 152 COM21 COM21 5974.20 630.75 202 SEG26 SEG26 2430.00 788.55 252 SEG76 SEG76 -810.00 788.55 153 COM20 COM20 5974.20 695.55 203 SEG27 SEG27 2365.20 788.55 253 SEG77 SEG77 -847.80 788.55 154 COM19 COM19 5974.20 760.35 204 SEG28 SEG28 2300.40 788.55 254 SEG78 SEG78 -939.60 788.55 155 COM18 COM18 5974.20 825.15 205 SEG29 SEG29 2235.60 788.55 255 SEG79 SEG79 -1004.40 788.55 156 N/C N/C 5974.20 889.95 206 SEG30 SEG30 2170.80 788.55 256 SEG80 SEG80 -1069.20 788.55 157 COM17 COM17 5346.00 788.55 207 SEG31 SEG31 2106.00 788.55 257 SEG81 SEG81 -1134.00 788.55 158 COM16 COM16 5281.20 788.55 208 SEG32 SEG32 2041.20 788.55 258 SEG82 SEG82 -1198.80 788.55 159 COM15 COM15 5216.40 788.55 209 SEG33 SEG33 1976.40 788.55 259 SEG83 SEG83 -1263.60 788.55 160 COM14 COM14 5151.60 788.55 210 SEG34 SEG34 1911.60 788.55 260 SEG84 SEG84 -1328.40 788.55 161 COM13 COM13 5086.80 788.55 211 SEG35 SEG35 1846.80 788.55 261 SEG85 SEG85 -1393.20 788.55 162 COM12 COM12 5022.00 788.55 212 SEG36 SEG36 1782.00 788.55 262 SEG86 SEG86 -1458.00 788.55 163 COM11 COM11 4957.20 788.55 213 SEG37 SEG37 1717.20 788.55 263 SEG87 SEG87 -1522.80 788.55 164 COM10 COM10 4892.40 788.55 214 SEG38 SEG38 1652.40 788.55 264 SEG88 SEG88 -1587.60 788.55 165 COM9 COM9 4827.60 788.55 215 SEG39 SEG39 1587.60 788.55 265 SEG89 SEG89 -1652.40 788.55 166 COM8 COM8 4762.80 788.55 216 SEG40 SEG40 1522.80 788.55 266 SEG90 SEG90 -1717.20 788.55 167 COM7 COM7 4698.00 788.55 217 SEG41 SEG41 1458.00 788.55 267 SEG91 SEG91 -1782.00 788.55 168 COM6 COM6 4633.20 788.55 218 SEG42 SEG42 1393.20 788.55 268 SEG92 SEG92 -1846.80 788.55 169 COM5 COM5 4568.40 788.55 219 SEG43 SEG43 1328.40 788.55 269 SEG93 SEG93 -1911.60 788.55 170 COM4 COM4 4503.60 788.55 220 SEG44 SEG44 1263.60 788.55 270 SEG94 SEG94 -1976.40 788.55 171 COM3 COM3 4438.80 788.55 221 SEG45 SEG45 1198.80 788.55 271 SEG95 SEG95 -2041.20 788.55 172 COM2 COM2 4374.00 788.55 222 SEG46 SEG46 1134.00 788.55 272 SEG96 SEG96 -2106.00 788.55 173 COM1 COM1 4309.20 788.55 223 SEG47 SEG47 1096.20 788.55 273 SEG97 SEG97 -2170.80 788.55 174 COM0 COM0 4244.40 788.55 224 SEG48 SEG48 1004.40 788.55 274 SEG98 SEG98 -2235.60 788.55 175 ICONS ICONS 4179.60 788.55 225 SEG49 SEG49 939.60 788.55 275 SEG99 SEG99 -2300.40 788.55 176 SEG0 SEG0 4114.80 788.55 226 SEG50 SEG50 874.80 788.55 276 SEG100 SEG100 -2365.20 788.55 177 SEG1 SEG1 4050.00 788.55 227 SEG51 SEG51 810.00 788.55 277 SEG101 SEG101 -2430.00 788.55 178 SEG2 SEG2 3985.20 788.55 228 SEG52 SEG52 745.20 788.55 278 SEG102 SEG102 -2494.80 788.55 179 SEG3 SEG3 3920.40 788.55 229 SEG53 SEG53 680.40 788.55 279 SEG103 SEG103 -2559.60 788.55 180 SEG4 SEG4 3855.60 788.55 230 SEG54 SEG54 615.60 788.55 280 SEG104 SEG104 -2624.40 788.55 181 SEG5 SEG5 3790.80 788.55 231 SEG55 SEG55 550.80 788.55 281 SEG105 SEG105 -2689.20 788.55 182 SEG6 SEG6 3726.00 788.55 232 SEG56 SEG56 486.00 788.55 282 SEG106 SEG106 -2754.00 788.55 183 SEG7 SEG7 3661.20 788.55 233 SEG57 SEG57 421.20 788.55 283 SEG107 SEG107 -2818.80 788.55 184 SEG8 SEG8 3596.40 788.55 234 SEG58 SEG58 356.40 788.55 284 SEG108 SEG108 -2883.60 788.55 185 SEG9 SEG9 3531.60 788.55 235 SEG59 SEG59 291.60 788.55 285 SEG109 SEG109 -2948.40 788.55 186 SEG10 SEG10 3466.80 788.55 236 SEG60 SEG60 226.80 788.55 286 SEG110 SEG110 -3013.20 788.55 187 SEG11 SEG11 3402.00 788.55 237 SEG61 SEG61 162.00 788.55 287 SEG111 SEG111 -3078.00 788.55 188 SEG12 SEG12 3337.20 788.55 238 SEG62 SEG62 97.20 788.55 288 SEG112 SEG112 -3142.80 788.55 189 SEG13 SEG13 3272.40 788.55 239 SEG63 SEG63 32.40 788.55 289 SEG113 SEG113 -3207.60 788.55 190 SEG14 SEG14 3207.60 788.55 240 SEG64 SEG64 -32.40 788.55 290 SEG114 SEG114 -3272.40 788.55 191 SEG15 SEG15 3142.80 788.55 241 SEG65 SEG65 -97.20 788.55 291 SEG115 SEG115 -3337.20 788.55 192 SEG16 SEG16 3078.00 788.55 242 SEG66 SEG66 -162.00 788.55 292 SEG116 SEG116 -3402.00 788.55 193 SEG17 SEG17 3013.20 788.55 243 SEG67 SEG67 -226.80 788.55 293 SEG117 SEG117 3466.80 788.55 194 SEG18 SEG18 2948.40 788.55 244 SEG68 SEG68 -291.60 788.55 294 SEG118 SEG118 -3531.60 788.55 195 SEG19 SEG19 2883.60 788.55 245 SEG69 SEG69 -356.40 788.55 295 SEG119 SEG119 -3596.40 788.55 196 SEG20 SEG20 2818.80 788.55 246 SEG70 SEG70 -421.20 788.55 296 SEG120 SEG120 -3661.20 788.55 197 SEG21 SEG21 2754.00 788.55 247 SEG71 SEG71 -486.00 788.55 297 SEG121 SEG121 -3726.00 788.55 198 SEG22 SEG22 2689.20 788.55 248 SEG72 SEG72 -550.80 788.55 298 SEG122 SEG122 -3790.80 788.55 199 SEG23 SEG23 2624.40 788.55 249 SEG73 SEG73 -615.60 788.55 299 SEG123 SEG123 -3855.60 788.55 200 SEG24 SEG24 2559.60 788.55 250 SEG74 SEG74 -680.40 788.55 300 SEG124 SEG124 -3920.40 788.55

SSD

X-pos Y-pos Pad #

1850

SSD 1851

SSD

X-pos Y-pos Pad #

1850

SSD 1851

SSD 1850

X-pos Y-pos

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

9

Pad #

301 SEG125 SEG125 -3985.20 788.55 302 SEG126 SEG126 -4050.00 788.55 303 SEG127 SEG127 -4114.80 788.55 304 COM40 COM32 -4179.60 788.55 305 COM41 COM33 -4244.40 788.55 306 COM42 COM34 -4309.20 788.55 307 COM43 COM35 -4374.00 788.55 308 COM44 COM36 -4438.80 788.55 309 COM45 COM37 -4503.60 788.55 310 COM46 COM38 -4568.40 788.55 311 COM47 COM39 -4633.20 788.55 312 COM48 COM40 -4698.00 788.55 313 COM49 COM41 -4762.80 788.55 314 COM50 COM42 -4827.60 788.55 315 COM51 COM43 -4892.40 788.55 316 COM52 COM44 -4957.20 788.55 317 COM53 COM45 -5022.00 788.55 318 COM54 COM46 -5086.80 788.55 319 COM55 COM47 -5151.60 788.55 320 COM56 COM48 -5216.40 788.55 321 COM57 COM49 -5281.20 788.55 322 COM58 COM50 -5346.00 788.55 323 N/C N/C -5974.20 889.95 324 COM59 COM51 -5974.20 825.15 325 COM60 COM52 -5974.20 760.35 326 COM61 COM53 -5974.20 695.55 327 COM62 COM54 -5974.20 630.75 328 COM63 COM55 -5974.20 565.95 329 COM64 COM56 -5974.20 501.15 330 COM65 COM57 -5974.20 436.35 331 COM66 COM58 -5974.20 371.55 332 COM67 COM59 -5974.20 306.75 333 COM68 COM60 -5974.20 241.95 334 COM69 COM61 -5974.20 177.15

335 COM70 COM62 -5974.20 112.35 PAD# X [um] Y [um] 336 COM71 COM63 -5974.20 47.55 1 – 130 52.2 60

337 COM72 N/C -5974.20 -17.25 131 – 156 75 45 338 COM73 N/C -5974.20 -82.05 323 – 347 75 45 339 COM74 N/C -5974.20 -146.85 157 – 322 45 75

340 COM75 N/C -5974.20 -211.65 341 COM76 N/C -5974.20 -276.45 342 COM77 N/C -5974.20 -341.25 343 COM78 N/C -5974.20 -406.05 344 COM79 N/C -5974.20 -470.85 345 ICONS ICONS -5974.20 -535.65 346 N/C N/C -5974.20 -600.45 347 N/C N/C -5974.20 -898.05

SSD 1851

SSD

1850

X-pos Y-pos

y

x

SSD1850/51

Pad 1 to 130

Bump Size

10

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

PIN DESCRIPTIONS

RES

This pin is reset signal input. When the pin is low, initialization of the chip is executed.

PS0, PS1

PS0 and PS1 determine the interface protocol between the driver and MCU. Refer to the following table for details.

PS0 PS1 Interface L L 3-wire SPI (write only) L H 4-wire SPI (write only) H L 8080 parallel interface (read and write allowed) H H 6800 parallel interface (read and write allowed)

CS

This pin is chip select input. The chip is enabled for display data/command transfer only when CS is low.

D/ C

This input pin is to identify display data/command cycle. When the pin is high, the data written to the driver will be written into display RAM. When the pin is low, the data will be interpreted as command. This pin must be connected to VSS when 3-lines SPI interface is used.

R/W( WR )

This pin is microprocessor interface signal. When 6800 interface mode is selected (by PS0 and PS1), the signal indicates read mode when high and write mode when low. When 8080 interface mode is selected

(by PS0 and PS1), a data write operation is initiated when

R/W( WR ) is low and the chip is selected.

E(RD )

This pin is microprocessor interface signal. When 6800 interface mode is selected (by PS0 and PS1), a data operation is initiated when selected (PS0 and PS1), a data read operation is initiated when

D0-D7

These pins are 8-bit bi-directional data/command bus to be connected to the microprocessor’s data bus. When serial mode is selected, D7 is the serial data input SDA and D6 is the serial clock input SCK.

INTRS

This pin is an input pin to enable the internal resistor network for the voltage regulator when INTRS is high. When external regulator is used, this pin must be connected to VSS, and external resistor R1/R2 should be connected to VL6, VR and VSS.

REF

This pin is an input pin to enable the internal reference voltage used for the internal regulator. When it is high, an internal reference voltage source will be used. When it is low, an external reference voltage source must be provided to VEXT pin if internal regulator is used.

VDD

Power supply pin.

E( RD ) is high and the chip is selected. When 8080 interface mode is

E( RD ) is low and the chip is selected.

SSD1850/51 Series

Rev 1.2 01/2003

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11

VSS

Ground.

VCI

Reference voltage input for internal DC-DC converter. The voltage of generated VCC equals to the multiple factor (2X, 3X, 4X, 5X or 6X) times VCI with respect to VSS. Note: voltage at this input pin must be larger than or equal to VDD. 6x is available for SSD1851 only.

VCC

This is the most positive voltage supply pin of the chip. It can be supplied externally or generated by the internal DC-DC converter. When using internal DC-DC converter as generator, voltage at this pin is for internal reference only. It CANNOT be used for driving external circuitries.

C1P, C2P, C3P, C4P, C5P, C1N and C2N

When internal DC-DC voltage converter is used, external capacitor(s) is/are connected to these pins. (Reference to application Circuit on P.42)

VL6

This pin is the most positive LCD driving voltage. It can be supplied externally or generated by the internal regulator.

VR

This pin is an input of the internal voltage regulator. When the internal resistors network for the voltage regulator is disabled (INTRS is pulled low), external resistors should be connected between VSS and VR, and VR and VL6, respectively (Please refer to application circuit on P.43).

VEXT

This pin is an input to provide an external voltage reference for the internal voltage regulator when REF pin is pulled L.

VL5, VL4, VL3 and VL2

These are LCD driving voltages. They can be supplied externally or generated by the internal bias divider. They have the following relationship: VL6 > VL5 > VL4 > VL3 > VL2 > VSS

1:a bias

VL5 (a-1)/a*VL6

VL4 (a-2)/a*VL6

VL3 2/a*VL6

VL2 1/a*VL6

For SSD1851, “a” equals to 10 at POR. For SSD1850, “a” equals to 9 at POR.

COM0 - COM79

These pins provide the row driving signal COM0 - COM79 to the LCD panel.

ICONS

This pin is the special icon line COM signal output.

12

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

SEG0 - SEG127

These pins provide the LCD column driving signal. Their voltage level is VSS during sleep mode and standby mode.

S5150

For SSD1851, this pin must be connected to VSS. For SSD1850, this pin must be connected to VDD.

CL

This pin is the external clock input for the device if external clock mode is selected by software command. Under POR operation, this pin should be left opened and internal oscillator will be used after power on reset.

N/C

These No Connection pins should NOT be connected to any signal pins nor shorted together. They should be left open.

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

13

FUNCTIONAL BLOCK DESCRIPTIONS

Command Decoder and Command Interface

This module determines whether the input data is interpreted as data or command. Data is directed to this module based upon the input of the

(GDDRAM). If

D/ C is low, the input at D0-D7 is interpreted as a Command and it will be decoded and

written to the corresponding command register. Reset is of the same function as Power ON Reset (POR). Once

about 1us, all internal circuitry will be back to its initial status. Refer to Command Description section for more information.

MPU Parallel 6800-series Interface

The parallel interface consists of 8 bi-directional data pins (D0-D7), R/

R/W( WR ) input High indicates a read operation from the Graphic Display Data RAM (GDDRAM) or the

status register.

R/W( WR ) input Low indicates a write operation to Display Data RAM or Internal

Command Registers depending on the status of signal (clock) when they are high and low respectively. Refer to P.35, Figure 1 of parallel timing characteristics for Parallel Interface Timing Diagram of 6800-series microprocessors. In order to match the operating frequency of display RAM with that of the microprocessor, pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 4 below.

R/W( WR )

E( RD )

Data bus

write column address

N n n+1 n+2

Figure 4 - display data read with the insertion of dummy read

MPU Parallel 8080-series interface

The parallel interface consists of 8 bi-directional data pins (D0-D7), R/

CS input serves as data latch signal (clock) when it is low. Whether it is display data or status register

read is controlled by Refer to P.37, Figure 2 of parallel timing characteristics for Parallel Interface Timing Diagram of 8080series microprocessor. Similar to 6800-series interface, a dummy read is also required before the first actual display data read.

D/ C . R/W( WR ) and E( RD ) input indicate a write or read cycle when CS is low.

D/ C pin. If D/ C is high, data is written to Graphic Display Data RAM

RES receives a negative reset pulse of

( WR ), D/ C , E(RD ) and CS .

W

D/ C input. The E(RD ) and CS input serves as data latch

dummy read

data read1 data read 2

data read 3

( WR ), E( RD ), D/ C and CS . The

W

14

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

MPU Serial 4-wire Interface

The serial interface consists of serial clock SCK, serial data SDA, D/ C and CS . Input to SDA is shifted

into a 8-bit shift register on every rising edge of SCK in the order of D eighth clock and the content in the shift register is written to the Display Data RAM or command register in the same clock. No extra clock or command is required to end the transmission.

7, D6,...D0. D/ C is sampled on every

MPU Serial 3-wire Interface

Operation is similar to 4-wire serial interface except D/ C is not used. The Set Display Data Length command is used to indicate that a specified number display data byte (1-256) is to be transmitted. Next byte after the display data string is handled as a command. It should be noted that if there is a signal glitch at SCK that causing an out of synchronization in the serial

communication, a hardware reset pulse at

RES pin is required to initialize the chip for re-synchronization.

Modes of operation

6800 parallel 8080 parallel Serial Data Read Yes Yes No Data W rite Yes Yes Yes Command Read Status only Status only No Command Write Yes Yes Yes

Graphic Display Data RAM (GDDRAM)

The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 128 x 81 x 2 = 20736bits. Figure 5 is a description of the GDDRAM address map. For mechanical flexibility, remapping on both Segment and Common outputs are provided respectively. For vertical scrolling of display, an internal register storing the display start line can be set to control the portion of the RAM data to be mapped to the display. Figure 5a and 5b show the cases in which the display start line register are set at 38H or 48H.

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

15

Page address

D3 D2 D1 D0

0 0 0 0

0 0 0 1

| | | |

0 1 1 0

0 1 1 1

1 0 0 0 D0 ---------- ICONS ICONS ICONS

Internal Column Address 00 01 02 03 04 05 06 07 F8 F9 FA FB FC FD FE FF

SEG Outputs SEG0 SEG1 SEG2 SEG3 SEG124 SEG125 SEG126 SEG127

First Byte

Line address

D0(LSB) ---------- 00 COM0 COM8

D7(MSB) ---------- 07 COM7 COM15

D0(LSB) ---------- 08 COM8 COM16

D7(MSB) ---------- 0F COM15 COM23

D0(LSB) ---------- 30 COM48 COM56

D7(MSB) ---------- 37 COM55 COM63

D0(LSB) ---------- 38 COM56 COM0

D7(MSB) ----------

D1 ---------- 01 COM1 COM9

D2 ---------- 02 COM2 COM10

D3 ---------- 03 COM3 COM11

D4 ---------- 04 COM4 COM12

D5 ---------- 05 COM5 COM13

D6 ---------- 06 COM6 COM14

D1 ---------- 09 COM9 COM17

D2 ---------- 0A COM10 COM18

D3 ---------- 0B COM11 COM19

D4 ---------- 0C COM12 COM20

D5 ---------- 0D COM13 COM21

D6 ---------- 0E COM14 COM22

----------

D1 ---------- 31 COM49 CO M57

D2 ---------- 32 COM50 CO M58

D3 ---------- 33 COM51 CO M59

D4 ---------- 34 COM52 CO M60

D5 ---------- 35 COM53 CO M61

D6 ---------- 36 COM54 CO M62

D1 ---------- 39 COM57 COM1

D2 ---------- 3A COM58 COM 2

D3 ---------- 3B COM59 COM 3

D4 ---------- 3C COM60 COM4

D5 ---------- 3D COM61 COM5

D6 ---------- 3E COM62 COM 6

Second Byte

COM Output

(Display

Startline = 0)

3F

COM63 COM7

COM Output

(Display

Startline = 38H)

Mapping depends

ADC = 0 00 01 02 03 7C 7D 7E 7F

ADC = 1 7F 7E 7D 7C 03 02 01 00

on COM scan direction setting

Figure 5a. Graphic Display Data RAM (GDDRAM) Address Map for SSD1850 (with vertical scroll value 38H)

16

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

Page address

D3 D2 D1 D0 Line address

0 0 0 0

0 0 0 1

| | | |

1 0 0 0

1 0 0 1

1 0 1 0 D0 ---------- ICONS ICONS ICONS

Internal Column Address 00 01 02 03 04 05 06 07 F8 F9 FA FB FC FD FE FF

D0(LSB) ---------- 00 COM0 COM8

D7(MSB) ---------- 07 COM7 COM15

D0(LSB) ---------- 08 COM8 COM16

D7(MSB) ---------- 0F COM15 COM23

D0(LSB) ---------- 40 COM64 CO M72

D7(MSB) ---------- 47 COM71 CO M79

D0(LSB) ---------- 48 COM72 COM0

D7(MSB) ----------

ADC = 0 00 01 02 03 7C 7D 7E 7F

ADC = 1 7F 7E 7D 7C 03 02 01 00

SEG Outputs SEG0 SEG1 SEG2 SEG3 SEG124 SEG125 SEG126 SE G127

Figure 5b. Graphic Display Data RAM (GDDRAM) Address Map for SSD1851 (with vertical scroll value 48H)

SSD1850/51 Series

First Byte

Second Byte

D1 ---------- 01 COM1 COM9

D2 ---------- 02 COM2 COM10

D3 ---------- 03 COM3 COM11

D4 ---------- 04 COM4 COM12

D5 ---------- 05 COM5 COM13

D6 ---------- 06 COM6 COM14

D1 ---------- 09 COM9 COM17

D2 ---------- 0A COM10 COM18

D3 ---------- 0B COM11 COM19

D4 ---------- 0C COM12 COM20

D5 ---------- 0D COM13 COM21

D6 ---------- 0E COM14 COM22

----------

D1 ---------- 41 COM65 COM73

D2 ---------- 42 COM66 COM74

D3 ---------- 43 COM67 COM75

D4 ---------- 44 COM68 COM76

D5 ---------- 45 COM69 COM77

D6 ---------- 46 COM70 COM78

D1 ---------- 49 COM73 COM1

D2 ---------- 4A COM74 COM2

D3 ---------- 4B COM75 COM3

D4 ---------- 4C COM76 CO M4

D5 ---------- 4D COM77 CO M5

D6 ---------- 4E COM78 COM6

COM Output

Startline = 0)

4F

COM Output

(Display

COM79 COM7

(Display

Startline = 48H)

Mapping depends on COM scan direction setting

Rev 1.2 01/2003

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17

r

Oscillator Circuit

This module is an On-Chip low power RC oscillator circuitry (Figure 6). The oscillator generates the clock for the DC-DC voltage converter. This clock is also used in the Display Timing Generator.

Oscillator enable

enable

Oscillation Circuit

Internal resistor

Internal pwell resisto

OSC2OSC1

Figure 6. Oscillator Circuitry

enable

Buffer

(CL)

LCD Driving Voltage Generator and Regulator

This module generates the LCD voltage needed for display output. It takes a single supply input and generates necessary bias voltages. It consists of:

1. 2X, 3X, 4X, 5X and 6X DC-DC voltage converter *Note: SSD1850 works up to 5X only. Please refer to application notes on P.42.

2. Voltage Regulator Feedback gain control for initial LCD voltage. External resistors are connected between VSS and VR, and between VR and VL6. These resistors are chosen to give the desired VL6 according to the following equations:

 

1V

6L

 



R

2



+=



R

1



con

GV

**

−

α

63



−=

1

 

210



VV *



refcon



where Vref is the internally generated reference voltage with a known R1 and R2. Typical value for Vref

is 2.1V R1 is the resistance of the resistor between VSS and VR. R2 is the resistance of the resistors between VR and VL6.

α is the software contrast level from 0 to 63.

G = 1 if INTRS = VDD; REF = VDD G = 0.80 if INTRS = VSS; REF = VDD

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SSD1850/51 Series

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LRL

3. Bias Divider If the output op-amp buffer option in Set Power Control Register command is enabled, this circuit block will divide the regulator output (VL6) to give the LCD driving levels (VL2 -VL5). A low power consumption circuit design in this bias divider saves most of the display current comparing to traditional design. Stabilizing Capacitors (0.47~2uF) are required to be connected between these voltage level pins (VL2 VL5) and VSS. If the LCD panel loading is heavy, four additional resistors are suggested to add to the application circuit as following:

VSS VL2 VL3 VL4 VL5 VL6

VSS

RL

C2

RL

+ +

C2 C2 C2 C2

R

+

Remarks:

1. C2 = 0.47~2.0uF

2. RL = 100K~1M (Optional)

++

Connections for hea vy loading applications

4. Contrast Control Software control of 64 voltage levels of LCD voltage.

5. Bias Ratio Selection circuitry Software control of 1/4 to 1/10 bias ratio to match the characteristic of LCD panel. Note: SSD1850 has 1/4 to 1/9 bias only.

6. Self adjust temperature compensation circuitry Provide 2 different temperature compensation grade selections to satisfy the various liquid crystal temperature grades. The grading can be selected by software control. Default temperature coefficient (TC) value is -0.05%/°C.

193 / 209 Bit Latch

A register carries the display signal information. In 128X65/81 display mode, data will be fed to the HVbuffer Cell and level-shifted to the required level.

Level Selector

Level Selector is a control of the display synchronization. Display voltage can be separated into two sets and used with different cycles. Synchronization is important since it selects the required LCD voltage level to the HV Buffer Cell, which in turn outputs the COM or SEG LCD waveform.

HV Buffer Cell (Level Shifter)

HV Buffer Cell works as a level shifter which translates the low voltage output signal to the required driving voltage. The output is shifted out with an internal FRM clock which comes from the Display Timing Generator. The voltage levels are given by the level selector which is synchronized with the internal M signal.

SSD1850/51 Series

Rev 1.2 01/2003

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19

Reset Circuit

When RES input is low, the chip is initialized to the following:

1. Page address is set to 0

2. Column address is set to 0

3. Display is OFF

4. Display Start Line is set to 0 (GDDRAM page 0, D0)

5. Display Offset is set to 0 (COM0 is mapped to ROW0)

6. 128x80 display mode for SSD1851 and 128x64 display mode for SSD1850.

7. Normal/Reverse Display is Normal

8. N-line Inversion Register is 0

9. Entire Display is OFF

10. Power Control Register (VC, VR, VF) is set to (0,0,0)

11. 3X Booster is selected

12. Internal Resistor Ratio register is set to 0H

13. Software Contrast is set to 32

14. LCD Bias Ratio is set to 1/10 for SSD1851 and 1/9 for SSD1850.

15. Normal scan direction of COM outputs

16. Segment remap is disabled (SEG0 display column address 0)

17. Internal oscillator is OFF

18. Test mode is OFF

19. Temperature coefficient is set to PTC0 (-0.05%)

20. Icon display line is OFF

When RESET command is issued, the following parameters are initialized only:

1. Page address is set to 0

2. Column address is set to 0

3. Initial Display Line is set to 0 (point to display RAM page 0, D0)

4. Internal Resistor Ratio register is set to 0H

5. Software Contrast is set to 32

20

SSD1850/51 Series

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N

LCD Panel Driving Waveform

The following is an example of how the Common and Segment drivers may be connected to a LCD panel. The waveforms shown in Figure 7a and 7b illustrate the desired multiplex scheme with N-line Inversion feature is disabled (default).

COM0 COM1 COM2

COM3

Figure 7a. LCD Display Example “0”

COM4 COM5 COM6

COM7

TIME SLOT

0

G

G1G2G3G

4

*

1 2 3 4 5 6 7 8

9

1 2 3 4

. . .

5 6 7 8 9

COM0

COM1

SEG0

*

1 2 3 4 5 6 7 8 9

. . .

. .

*

1 2 3 4 5 6 7 8 9

*

. . .

V

L6

V

L5

V

L4

V

L3

V

L2

V

SS

V

L6

V

L5

V

L4

V

L3

V

L2

V

SS

V

L6

V

L5

V

L4

V

L3

V

L2

V

SS

V

L6

V

L5

V

L4

SEG1

M

* Note: N is the number of multiplex ratio including Icon line. If it is enabled, N is equal to 80 for SSD1851 and 64 for SSD1850 on POR

V V V

L3

L2

SS

Figure 7b. LCD Driving Signal From SSD1850/51

SSD1850/51 Series

Rev 1.2

SOLOMON

01/2003

21

COMMAND TABLE

Hex D7 D6 D5 D4 D3 D2 D1 D0 Command Description

00~0F 0 0 0 0 C3 C2 C1 C0

10~17 0 0 0 1 0 C6 C5 C4

18~1F

20~27 0 0 1 0 0 R2 R1 R0

28~2F 0 0 1 0 1 VC VR VF

30~3F

40~43 0 X 1

L6 0 L5 0 L4 0 L3 0 L2 X L1 X L0

44~47 0 X 1

C6 0 C5 0 C4 0 C3 1 C2 X C1 X C0

48~4B 0 X 1

D6 0 D5 0 D4 1 D3 0 D2 X D1

4C~4F 0 X 1 X 0 X 0

N4 1 N3 1 N2 X N1 X N0

Set Lower Column Address

Set the lower nibble of the column address pointer for RAM access. The pointer is reset to 0 after rest.

Set Upper Column Address

Set the upper nibble of the column address pointer for RAM access. The pointer is reset to 0 after rest.

Reserved Reserved

Set Internal Regulator Resistor Ratio

The internal regulator gain (1+R2/R1)Vcon increases as R2R1R0 is increased from 000b to 111b. The factor, 1+R2/R1, is given by: R2R1R0 = 000: 2.3 (POR) R2R1R0 = 001: 3.0 R2R1R0 = 010: 3.7 R2R1R0 = 011: 4.4 R2R1R0 = 100: 5.1 R2R1R0 = 101: 5.8 R2R1R0 = 110: 6.5

R2R1R0 = 111: 7.2 Set Power Control Register

VC=0: turns OFF the internal voltage

booster (POR)

VC=1: turns ON the internal voltage

booster

VR=0: turns OFF the internal regulator

(POR)

VR=1: turns ON the internal regulator

VF=0: turns OFF the output op-amp

buffer (POR)

VF=1: turns ON the output op-amp

buffer Reserved Reserved

Set Display Start Line

The next command specifies the row

address pointer (0-79) of the RAM data

to be displayed in COM0. This

command has no effect on ICONS. The

pointer is set to 0 after reset. Set Display Offset The next command specifies the

mapping of first display line (COM0) to

one of ROW0~79 (SSD1851) or

(COM0) to one of ROW0~63

(SSD1850). This command has no

effect on ICONS. COM0 is mapped to

ROW0 after reset.

X

Set Multiplex

D0

Ratio

The next command specifies the

number of lines, excluding ICONS, to

be displayed. With Icon is disabled

(POR), duties 1/16~1/80 (SSD1851) or

1/16~1/64 (SSD1850) could be

selected. With Icon enabled, the

available duty ratios are 1/17~ 1/81

(SSD1851) or 1/17~1/65 (SSD1850). Set N-line Inversion

The next command sets the n-line

inversion register from 3 to 33 lines to

reduce display crosstalk. Register

values from 00001b to 11111b are

22

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

50~56 0 1 0 1 0 B2 B1 B0

57~63

64~67 0 1 1 0 0 1 B1 B0

68~80

81 1 X 0 X 0

82 1 1 0 1 0 1 0 1 0

83 1 0 0 0 0 0 1 1

84~87

88 1

89 1

Reserved Reserved

C5 0 C4 0 C3 0 C2 0 C1 1 C0

X3 0 X2 1 X1 0 X0

0

WB3 0 WB2

0

WD3

WD2 0 WD1 0 WD0 1 WC3

WB1

0

WB0 1 WA3

0

WA2 0 WA1 0 WA0

0

WC2 0 WC1 1 WC0

mapped to 3 lines to 33 lines

respectively. Value 00000b disables the

N-line inversion, which is the POR

value. To avoid a fix polarity at some

lines, it should be noted that the total

number of mux (including the icon line)

should NOT be a multiple of the lines of

inversion (n). Set LCD Bias Sets the LCD bias from 1/4 ~ 1/10

according to B2B1B0:

000: 1/4 bias

001: 1/5 bias

010: 1/6 bias

011: 1/7bias

100: 1/8 bias

101: 1/9 bias (POR for SSD1850)

110: 1/9 bias (SSD1850); 1/10 bias

(POR for SSD1851) Reserved Reserved

Set DC-DC Converter Factor

Sets the DC-DC multiplying factor from

2X to 6X B1B0:

00: 2X/3X (POR, 2X or 3X multiplying

depended on the DC-DC converter

hardware configuration)

01: 4X

10: 5X

11: 5X (SSD1850); 6X (SSD1851)

Set Contrast Control Register

The next command sets one of the 64

contrast levels. The darkness increase

as the contrast level increase. The level

is set to 32 after POR. OTP Setting Set the desired VL6 voltage value:

0000: original contrast

0001: original contrast +1 step

0010: original contrast +2 steps

0011: original contrast +3 steps

0100: original contrast +4 steps

0101: original contrast +5 steps

0110: original contrast +6 steps

0111: original contrast +7 steps

1000: original contrast -8 steps

1001: original contrast -7 steps

1010: original contrast -6 steps

1011: original contrast -5 steps

1100: original contrast -4 steps

1101: original contrast -3 steps

1110: original contrast -2 steps

1111: original contrast -1 step OTP Programming

Please refer the sequence of OTP

programming

Reserved Reserved

Set White mode, Frame 2

Set White mode, Frame 4

nd

& 1st

th

& 3rd

Set gray scale mode and register.

These are two-byte commands used to

specify the contrast levels for the gray

scale, 4 levels available.

After power on reset,

SSD1850/51 Series

Rev 1.2 01/2003

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23

8A 1

8B 1

8C 1

8D 1

8E 1

8F 1

90~97 1 0 0 1 0 FRC PW

98~9F

A0~A1 1 0 1 0 0 0 0 S0

A2~A3 1 0 1 0 0 0 1 C0

A4~A5 1 0 1 0 0 1 0 E0

A6~A7 1 0 1 0 0 1 1 R0

A8~A9 1 0 1 0 1 0 0 S0

AA

AB 1 0 1 0 1 0 1 1

AC~AD

AE~AF 1 0 1 0 1 1 1 D0

LB3 0 LB2 0 LB1 0 LB0

LD3 0 LD2 0 LD1 0 LD0 1 LC3

DB3 0 DB2 0 DB1 0 DB0 1 DA3

DD3 0 DD2 0 DD1 0 DD0 1 DC3

BB3 0 BB2 0 BB1 0 BB0 1 BA3

BD3 0 BD2 0 BD1 0 BD0 1 BC3

1

0

LA3

LA2 1 LA1 0 LA0

0

LC2 1 LC1 1 LC0

1

DA2 0 DA1 0 DA0

1

DC2 0 DC1 1 DC0

1

BA2 1 BA1 0 BA0

1

BC2 1 BC1 1 BC0

M1 PWM0

Set Light Gray mode, Frame 2

st

& 1

Set Light Gray mode, Frame 4

rd

& 3

Set Dark Gray mode, Frame 2

st

& 1

Set Dark Gray mode, Frame 4

rd

& 3

Set Black mode, Frame 2

nd

& 1st

Set Black mode, Frame 4th & 3rd

Set PWM and FRC

WA0~3 = WB0~3 = WC0~3 = W D0~3 =

nd

0000

LA0~3 = LB0~3 = LC0~3 = LD0~3 =

0000

DA0~3 = DB0~3 = DC0~3 = DD0~3 =

th

1111

BA0~3 = BB0~3 = BC0~3 = BD0~3 =

1111

nd

Memory Content

Gray Mode

th

1st Byte 2nd Byte

0

1

0

1

0

Light Gray

Dark Gray

1

Sets PWM and FRC for gray-scale

operation.

White

Black

FRC = 0 : 4-frame (POR)

FRC = 1 : 3-frame

PWM1 PWM0 = 00 & 01 : 9-levels

(POR)

PWM1 PWM0 = 10 : 12-levels

PWM1 PWM0 = 11 : 15-levels Reserved Reserved

Set Segment Remap

S0=0: column address 00H is mapped

to SEG0 (POR)

S0=1: column address 7FH is mapped

to SEG0 Set Icon Enable C0=0: Disable icon row (Mux = 16 to

80/64, POR)

C0=1: Enable icon row (Mux = 17 to

81/65) Set Entire Display On/Off

E0=0: Normal display (display

according to RAM contents, POR)

E0=1: All pixels are ON regardless of

the RAM contents

*Note: This command will override the

effect of “Set Normal/Inverse Display” Set Normal/Inverse Display

R0=0: Normal display (display

according to RAM contents, POR)

R0=1: Inverse display (ON and OFF

pixels are inverted)

*Note: This command will not affect the

display of the icon line Set Power Save Mode

S0=0: Standby mode (POR)

S0=1: Sleep mode

Reserved Reserved

Start Internal Oscillator

Oscillator is OFF, after reset, until this

command is issued.

Reserved Reserved

Set Display On/Off

D0=0: Display OFF (POR)

D0=1: Display ON

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SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

B0~BF 1 0 1 1 P3 P2 P1 P0

C0~CF 1 1 0 0 S0 X X X

Set Page Address Set GDDRAM page address (0~10)

Set COM Output Scan Direction

D0~E0

E1 1 1 1 0 0 0 0 1

Reserved Reserved

Exit Power-save Mode

E2 1 1 1 0 0 0 1 0

E3

E4 1 1 1 0 0 1 0 0

Software Reset Initialize some internal registers

Reserved Reserved

Exit N-line Inversion

E5~E7

E8 1

D7 1 D6 1 D5 0 D4 1 D3 0 D2 0 D1 0 D0

E9~EF

F0~FF 1 1 1 1 X X X X

Reserved Reserved

Set Display Data Length

Reserved Reserved

Extended Features

Extended Command Table

Bit Pattern Command Description

11110000 000000X

1X0

11110001 00001X

2X1X0

11110111 0000000X

0

11110010 00000X

2X1X0

SSD1850/51 Series

1X0 : Set VL6 noise reduction X1X0 = 00: Enable (POR)

X

1X0 = 11: Normal

Remarks: This command is only valid for the IC version with G prefix notation on the “DTE” (datecode) field of label printed on die tray cover, intermediates and outer boxes.

2X1X0 : Set TC Value

X

Select Oscillator Source

X2X1X0 = 000: -0.05%/°C (POR) X

2X1X0 = 001: -0.07%/°C

X0 = 0: Internal RC oscillator is selected (POR) X

0 = 1: External oscillator from CL pin is

selected

Oscillator Adjustment

Rev 1.2 01/2003

X

2X1X0 = 000: -9% 2X1X0 = 001: -6%

X X

2X1X0 = 010: -3%

X

2X1X0 = 011: 0 (POR)

X

2X1X0 = 100: +3%

using P3P2P1P0 for RAM access. The

page address is sets to 0 after reset.

S0=0: Normal mode (POR)

S0=1: Remapped mode. COM0 to

COM[N-1] becomes COM[N-1] to

COM0 when the duty is set to N. See

Figure 5 as an example for N equals to

80.

*Note: This command will not affect the

display of the icon lines

DC-DC converter, regulator and divider

status before entering the power-save

mode is restored. At POR, Power-save

Mode is released.

The frame will be inverted once per

frame

This command is valid only at 3-wire

SPI (PS0=PS1=L)

The next command specifies the

number of bytes of display data to be

written after this composite command.

D(7:0)=00: 1 byte of display data is to

be sent

D(7:0)=FF: 256 bytes of display data is

to be sent

Test mode commands and Extended

features, see Extended Command

Table.

SOLOMON

25

X X

X 11111101 xxxx0X

210

11110110 000X

4X3X2X1X0

Other than the above

Frame Frequency Default Setting

Frame Frequency = Fosc / [Mux x (FRAMEFQ + 1) x PWM]

Mux (Icon Enable) FRAMEFQ PWM Fosc

Mux<=17 2

18<=MUX<=33 1

34<=MUX<=49 0

50<=MUX<=65 0

66<=MUX<=81 0

PWM is defined in command Set PWM and FRC.

26

SSD1850/51 Series

Lock / Unlock Interface X2 = 0 : Unlock the IC. The driver accepts any

command and data written.

X

command and data written, except the unlock

command or pin reset.

Frame Frequency Adjust (Please find the default setting in the following table)

FRAMEFQ

X2X1X0 = 000: 0

X

Fosc

X4X3 = 00: 59kHz

X

Set Test Mode Reserved

Rev 1.2 01/2003

5 4

1 2

1 1

0 1

0 0

15 12

9 15 12

9

59kHz 94kHz 59kHz 75kHz 59kHz 75kHz 59kHz 94kHz 75kHz 75kHz 59kHz 94kHz 94kHz 75kHz 59kHz

2X1X0 = 101: +6% 2X1X0 = 110: +9% 2X1X0 = 111: +12%

2 = 1 : Lock the IC. The driver ignores all

2X1X0 = 001: 1 2X1X0 = 010: 2 2X1X0 = 011: 3 2X1X0 = 100: 4 2X1X0 = 101: 5 2X1X0 = 110: 6 2X1X0 = 111: 7

4X3 = 01: 75kHz 4X3 = 10: 94kHz 4X3 = 11: 113kHz

SOLOMON

W

Read Status Byte

A 8 bits status byte will be placed onto the data bus when a read operation is performed if D/ C is low. The status byte is defined as following: D7 D6 D5 D4 D3 D2 D1 D0 Comment BUSY ON

RES

Data Read / Write

To read data from the GDDRAM, input High to R/

Low to

E( RD ) pin and High to D/ C pin for 8080-series parallel mode. No data read is provided for serial

mode. In normal mode, GDDRAM column address pointer will be increased by one automatically after each data read. Also, a dummy read is required before the first data is read. See P.14, Figure 4 in Functional Description.

To write data to the GDDRAM, input Low to mode. For serial interface, it will always be in write mode. GDDRAM column address pointer will be increased by one automatically after each data write. After the data read/write operation (address=127) is executed, the address will be reset to 0 in next data read/write operation.

Address Increment Table (Automatic)

R/

D/ C

0 0 Write Command No 0 1 Read Status No 1 0 W rite Data Yes 1 1 Read Data Yes

W

Address Increment is done automatically after data read/write. The column address pointer of GDDRAM is affected. After the data read/write operation (address=127) is executed, the address will be reset to 0 in next data read/write operation.

Commands Required for R/W( WR ) Actions on RAM

R/

( WR ) Actions on RAMs

Read/Write Data from/to GDDRAM.

* No need to resend the command again if it is set previously. The read / write action to the Display Data RAM does not depend on the display mode. This means the user can change the RAM content whether the target RAM content is being displayed or not.

0 1 0 DS1 DS0 BUSY=0 : Chip is idle

BUSY=1 : Chip is executing instruction ON=0 : Display is OFF ON=1 : Display is ON

RES =0: Chip is idle

RES =1: Chip is executing reset

DS1, DS0 = 00: SSD1850 DS1, DS0 = 01: SSD1851

( WR ) pin and D/ C pin for 6800-series parallel mode,

W

R/W( WR ) pin and High to D/ C pin for 6800-series parallel

( WR )

Action Auto Address Increment

Commands Required

Set GDDRAM Page Address Set GDDRAM Column Address

Read/Write Data

(1011X3X2X1X0)* (0001X (0000X (X

7X6X5X4X3X2X1X0)

3X2X1X0)* 3X2X1X0)*

SSD1850/51 Series

Rev 1.2 01/2003

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27

COMMAND DESCRIPTIONS

Set Display On/Off

This command turns the display on/off, by the value of the LSB.

Set Display Start Line

This command is to set Display Start Line register to determine starting address of display RAM to be displayed by selecting a value from 0 to 63/79. With value equals to 0, D0 of Page 0 is mapped to COM0. With value equals to 1, D1 of Page0 is mapped to COM0. The display start line values of 0 to 63/79 are assigned to Page 0 to 9.

Set Page Address

This command positions the page address to 0 to 8/10 possible positions in GDDRAM. Refer to figure 5. Set Higher Column Address This command specifies the higher nibble of the 7-bit column address of the display data RAM. The column address will be incremented by each data access after it is pre-set by the MCU and returning to 0 once overflow (>127).

Set Lower Column Address

This command specifies the lower nibble of the 7-bit column address of the display data RAM. The column address will be incremented by each data access after it is pre-set by the MCU and returning to 0 once overflow (>127).

Set Segment Re-map

This commands changes the mapping between the display data column address and segment driver. It allows flexibility in layout during LCD module assembly. Refer to figure 5.

Set Normal/Inverse Display

This command sets the display to be either normal/inverse. In normal display, a RAM data of 1 indicates an “ON” pixel. While in reverse display, a RAM data of 0 indicates an “ON” pixel. The icon line is not affected by this command.

Set Entire Display On/Off

This command forces the entire display, including the icon row, to be “ON” regardless of the contents of the display data RAM. This command has priority over normal/inverse display. To execute this command, Set Display On command must be sent in advance.

Set LCD Bias

This command is used to select a suitable bias ratio (1/4 to 1/11) required for driving the particular LCD panel in use. The POR default for SSD1851 is set to 1/10 bias and SSD1850 is set to 1/9.

Software Reset

This command causes some of the internal status of the chip to be initialized:

1. Page address is set to 0

2. Column address is set to 0

3. Initial Display Line is set to 0 (point to display RAM page 0, D0)

4. Internal Resistor Ratio register is set to (0,0,0)

5. Software Contrast is set to 32

Set COM Output Scan Direction

This command sets the scan direction of the COM output allowing layout flexibility in LCD module assembly.

28

SSD1850/51 Series

Rev 1.2 01/2003

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N

Set Power Control Register

This command turns on/off the various power circuits associated with the chip.

Set Internal Regulator Resistors Ratio

This command is to enable any one of the eight internal resistor (IRS) settings for different regulator gains when using internal regulator resistor network (INTRS pin pulled high). The Contrast Control Voltage Range curves is given in the figure below:

Set Contrast Control Register

This command adjusts the contrast of the LCD panel by changing VL6 of the LCD drive voltage provided by the On-Chip power circuits. VL6 is set with 64 steps (6-bit) contrast control register. It is a compound commands:

Set Contrast Control Register

Contrast Level Data

o

Changes

Complete?

Yes

Set Display Offset

The next command specifies the mapping of display start line (COM0 if display start line register equals to

0) to one of ROW0-79. This command has no effect on ICONS. COM0 is mapped to ROW0 after reset.

SSD1850/51 Series

Rev 1.2 01/2003

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29

Set Multiplex Ratio

This command switches default 80 multiplex mode to any multiplex from 16 to 80, if Icon is disabled (POR). When Icon is set enable, the corresponding multiplex ratio setting will be mapped to 17 to 81. The chip pads ROW0-ROW79 will be switched to corresponding COM signal output.

Set Power Save Mode

This command forces the chip to enter Standby or Sleep Mode. LSB of the command will define which mode will be entered.

Exit Power Save Mode

This command releases the chip from either Standby or Sleep Mode and return to normal operation.

Set N-line Inversion

Number of line inversion is set by this command for reducing crosstalk. 3 to 33-line inversion operations could be selected. At POR, this operation is disabled. It should be noted that the total number of mux (including the icon line) should NOT be a multiple of the inversion number (N). Or else, some lines will not be changed their polarity during frame change.

Exit N-line Inversion

This command releases the chip from N-line inversion mode. The driving waveform will be inverted once per frame after issuing this command.

Set DC-DC Converter Factor

Internal DC-DC converter factor is set by this command. For SSD1850, 2X to 5X multiplying factors could be selected. 2X/3X, 4X, 5X and 6X factors are selected using this command. Hardware configuration is used for 2X or 3X setup. For SSD1851, 2X to 6X multiplying factors could be selected.

Set Icon Enable

This command enable/disable the Icon display.

Start Internal Oscillator

After POR, the internal oscillator is OFF. It should be turned ON by sending this command to the chip.

Set Display Data Length

This two-byte command only valid when 3-wire SPI configuration is set by H/W input (PS0=PS1=L). The second 8-bit is used to indicate that a specified number display data byte (1-256) are to be transmitted. Next byte after the display data string is handled as a command.

Set Gray Scale Mode (White/Light Gray/Dark Gray/Black)

Command 88(hex) to 8F(hex) are used to specify the four gray levels’ pulse width at the four possible frames. The four gray levels are called white, light gray, dark gray and black. Each level is defined by 4 registers for 4 consecutive frames. For example, WA is a 4-bit register to define the pulse width of the 1 frame in White mode. WB is a register for 2 registers.

30

SSD1850/51 Series

Rev 1.2 01/2003

nd

frame in White mode etc. Each command specifies two

SOLOMON

st

For 4 FRC,

Memory Content FRAME

1st Byte 2nd Byte

0 0 White WA WB WC WD 0 1 Light Gray LA LB LC LD 1 0 Dark Gray DA DB DC DD 1 1 Black BA BB BC BD

Gray Mode

st

1

2

nd

3

rd

4

th

For 3 FRC,

1st Byte 2nd Byte

Memory Content FRAME

0 0 White WA WB WC WD (XX) 0 1 Light Gray LA LB LC LD (XX) 1 0 Dark Gray DA DB DC DC (XX) 1 1 Black BA BB BC BC (XX)

Gray Mode

st

1

2

nd

3

rd

4

th

(No use)

Set PWM and FRC

This command selects the number of frames in frame rate control, or the number of levels in the pulse width modulation.

Set Test Mode

This command forces the driver chip into its test mode for internal testing of the chip. Under normal operation, user should NOT use this command.

Status Register Read

This command is issued by setting D/ C Low during a data read (refer to figure 1 and 2 parallel interface waveform, P.35-38). It allows the MCU to monitor the internal status of the chip. No status read is provided for serial mode.

EXTENDED COMMANDS

These commands are used, in addition to basic commands, to trigger the enhanced features designed for the chip. These features are on top of general ones.

Set VL6 noise reduction

This command is to enable the VL6 noise reduction. This command is only valid for the IC version with G prefix notation on the “DTE” (datecode) field of label printed on die tray cover, intermediates and outer boxes. For details, please refer to the product change notification document of PC0010 from SSL.

Set Temperature Coefficient (TC) Value

This command is to set 1 out of 2 different temperature coefficients in order to match various liquid crystal temperature grades.

Select Oscillator Source

This command enables the external clock input from CL pin.

Oscillator adjustment

This command is used to adjust the oscillator frequency to desired frame frequency.

Lock/Unlock Interface

After sending the lock command, the interface will be disabled until the unlock command is received. The lock command is suggested whenever the LCD driver will not be accessed for some period. This can minimize incorrect data or command written due to noisy interface.

SSD1850/51 Series

Rev 1.2 01/2003

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31

y

MAXIMUM RATINGS

Symbol Parameter Value Unit

VDD -0.3 to 4.0 V

VCC

Supply voltage

VSS-0.3 to

VSS+18.0

V

VCI Booster Supply Voltage VDD to 4.0 V

Vin Input Voltage

I

Current Drain Per Pin Excluding V and VSS

DD

TA Operating Temperature -40 to +80

T

Storage Temperature Range -65 to +150

stg

VSS-0.3 to

VDD+0.3

V

25 mA

o

C

o

C

* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description section.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions to be taken to avoid application of an voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range V < or = V

. Reliability of operation is enhanced if

DD

unused inputs are connected to an appropriate logic voltage level (e.g., either V Unused outputs must be left open. This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal operation. This device is not radiation protected.

ELECTRICAL CHARACTERISTICS

(Voltages Referenced to VSS, VDD=1.8 to 3.3V, TA=-40 to 85°C; unless otherwise specified.)

Symbol Parameter Test Condition Min

VDD Logic Circuit Supply Voltage

Range Voltage Generator Circuit Supply Voltage Range

IAC

I

DP1

I

DP2

I

SLEEP

VCC

V

SB

LCD

Access Mode Supply Current

DD

Pins)

Drain (V

Display Mode Supply Current Drain (V

Standby Mode Supply Current Drain (V

Sleep Mode Supply Current Drain (V LCD Driving Voltage Generator Output (V

DC-DC Converter Efficiency

LCD Driving Voltage Input (V

CC

Pin)

CC

(Absolute value referenced to V

= 2.7V, Voltage Generator On,

V

DD

4X Converter Enabled, Write accessing, Tcyc = 3.3MHz, Osc. Freq.=31kHz, Display On.

VDD = 2.7V, VCC = 10.8V, Voltage Generator Off, Divider Enabled, Read/Write Halt, Osc. Freq.=31kHz, Display On,

=9V

V

L6

= 2.7V, Vcc=10.8V, Voltage

V

DD

Generator On, 4x DC-DC Converter Enabled Divider Enabled, Read/Write Halt, Osc. Freq.=31kHz, Display On, V

= 9V.

L6

= 2.7V, LCD Driving Waveform

V

DD

Off, Osc. Freq. 31KHz, Read/Write halt.

= 2.7V, LCD Driving Waveform

V

DD

Off, Oscillator Off, Read/W rite halt. Display On, Voltage Generator Enabled, DC/DC Converter Enabled, Osc. Freq. = 31kHz, Regulator Enabled, Divider Enabled.

< 20uA

I

CC

Pin)

Voltage Generator Disabled.

) 1.8

SS

-

VDD

95

4.0

Typ

(at 25°C)

2.7

750

40

200

27

0.5

-

99

-

< or = (Vin or V

SS

or VDD).

SS

Max

3.3

800

60

500

40

2.5

15.0

Unit

µΑ

µA

OUT

V

%

V

)

32

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

Symbol Parameter Test Condition Min Typ Max Unit

V

REF

External Reference Voltage Input

Internal Reference Voltage

Internal Reference Voltage Source Disable (REF pin pulled Low), External Reference voltage input to V

EXT

Internal Reference Voltage Source Enabled (REF pin pulled High), V pin NC.

V

OH1

V

OL1

V

Output High voltage (D

Output Low Voltage (D

LCD Driving Voltage Source (V

L6

Pin)

LCD Driving Voltage Source (V

L6

0-D7

)

Iout = +500µΑ

)

Iout = -500µΑ

L6

Regulator Enabled (VL6 voltage depends on Int/Ext Contrast Control)

L6

Regulator Disable

Pin)

V

IH1

V

IL1

VL6 V

L5

V

L4

V

L3

V

L2

V

L6

V

L5

V

L4

V

L3

V

L2

IOH

I

OL

I

OZ

IIL/IIH

Input high voltage (RES#, PS0, PS1, CS, D/C#, R/W#, D Input Low voltage

, REF, INTRS)

0-D7

(RES#, PS0, PS1, CS, D/C#, R/W#, D

, REF, INTRS)

0-D7

LCD Display Voltage Output

, VL5, VL4, VL3, VL2 Pins)

(V

L6

LCD Display Voltage Input

, VL5, VL4, VL3, VL2 Pins)

(V

L6

Output High Current Source(D

Output Low Current Drain (D

Output Tri-state Current Drain Source (D

0-D7

) Input Current (RES#, PS0, PS1,CS#, E(RD#), D/C#,R/W#(WR#), D

0~D7

0-D7

, REF,

0.8*V

Divider Enabled, 1:a bias ratio, a=4~10 for SSD1851 and a =4~9 for SSD1850.

Voltage reference to V Voltage Generator, Divider Disabled

Vout=V

)

0-D7

)

Vout=0.4V

-1 1

INTRS)

CIN

∆VL6 Variation of VL6 Output (1.8V <

Input Capacitance (all logic pins)

< 3.3V)

V

DD

5 7.5

Regulator Enabled, Internal Contrast Control Enabled, Set Contrast Control Register = 0

PTC0 PTC1

Temperature Coefficient Compensation Temperature Coefficient [POR] Temperature Coefficient

Voltage Regulator Enabled Voltage Regulator Enabled

*The formula for the temperature coefficient is:

0

=

) / (%

C TC

−

0 50

00

050

Cat V C at V

ref

*

pin.

ref

DD

-0.4V

1

25

2.16

V

DD

0.2*V

-0.5

V

CC

-

VDD

0.2*V

-

L6

-

V

CC

V

L6

V

L5

V

L4

V

L3

-

-50

1

, External

SS

EXT

2.10

-

Floating

-

V

L6

(a-1)/a*V (a-2)/a*V

2/a*V 1/a*V

-

L6

2.04

0.8*V

DD

0.0

V

DD

-

DD

0.0

-

V

L5

V

L4

V

L3

V

L2

V

SS

50

-

-1

- ± 2 -

-0.04

-0.06

00 0

CatVC C

%100*

-0.05

-0.07

-0.06

-0.08

V

DD

V

DD

V V V V V

µA

pF

%

% %

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

33

AC ELECTRICAL CHARACTERISTICS

(TA=-40 to 85°C, Voltages referenced to VSS, VDD=VCI=2.7V, unless otherwise specified.)

Symbol Parameter Test Condition Min

F

Frame Frequency

F

FRM

(SSD1851) Fosc / [Mux x (FRAMEFQ+1) x PWM]

Frame Frequency

(SSD1850)

Fosc / [Mux x (FRAMEFQ+1) x PWM]

Display ON, Set 128 x 81 Graphic Display Mode, Icon Line Enabled, 15PWM, Default frame frequency setting Display ON, Set 128 x 65 Graphic Display Mode, Icon Line Enabled, 15PWM, Default frame frequency setting

70 77.4 100 Hz

70 76.9 100 Hz

Typ

(at 25°C)

Max Unit

34

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

TABLE 3a. Parallel Timing Characteristics (TA=-40 to 85°C, VDD=2.7V, VSS=0V)

Symbol Parameter Min Typ Max Unit

t

Clock Cycle Time (write cycle) 100 - - ns

cycle

tAS Address Setup Time 0 - - ns tAH Address Hold Time 0 - - ns

t

Write Data Setup Time 10 - - ns

DSW

t

Write Data Hold Time 2 - - ns

DHW

t

Read Data Hold Time 10 - 30 ns

DHR

tOH Output Disable Time - - 80 ns

t

Access Time - - 25 ns

ACC

PW

tR Rise Time - - 10 ns tF Fall Time - - 10 ns

Chip Select Low Pulse Width (read RAM) Chip Select Low Pulse Width (read command)

CSL

Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read)

CSH

Chip Select High Pulse Width (write)

R/ W

95 40 15 30 30

-

ns

-

ns

-

D/ C

E

CS

D

-D

0

(Write data to driv er)

(Read dat a from driv er)

7

-D

D

0

7

Figure 1a. Parallel 6800-series Interface Timing Characteristics (PS0=H, PS1=H)

t

AS

t

PW

CSL

t

F

t

Valid Data

t

ACC

c ycle

DSW

Valid Data

t

AH

PW

CSH

t

R

t

DHW

t

DHR

t

OH

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

35

TABLE 3b. Parallel Timing Characteristics (TA=-40 to 85°C, VDD=1.8V,VSS=0V)

Symbol Parameter Min Typ Max Unit

t

Clock Cycle Time (write cycle) 100 - - ns

cycle

tAS Address Setup Time 0 - - ns tAH Address Hold Time 0 - - ns

t

Write Data Setup Time 15 - - ns

DSW

t

Write Data Hold Time 5 - - ns

DHW

t

Read Data Hold Time 15 - - ns

DHR

tOH Output Disable Time - - 40 ns

t

ACC

Access Time (RAM) Access Time (Command) Chip Select Low Pulse Width (read RAM)

PW

Chip Select Low Pulse Width (read command)

CSL

Chip Select Low Pulse Width (write)

PW

Chip Select High Pulse Width (read)

CSH

Chip Select High Pulse Width (write) tR Rise Time - - 10 ns tF Fall Time - - 10 ns

R/ W

-

120

55 20 40 40

- - 100 35

-

ns

D/ C

E

CS

D

-D

0

(Write data to driv er)

(Read dat a from driv er)

7

D

-D

0

7

Figure 1b. Parallel 6800-series Interface Timing Characteristics (PS0=H, PS1=H)

t

AS

t

PW

CSL

t

F

t

Valid Data

t

ACC

c ycle

DSW

Valid Data

t

AH

PW

CSH

t

R

t

DHW

t

DHR

t

OH

36

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

TABLE 4a. Parallel Timing Characteristics (TA=-40 to 85°C, VDD=2.7V,VSS=0V)

Symbol Parameter Min Typ Max Unit

t

Clock Cycle Time 100 - - ns

cycle

tAS Address Setup Time 0 - - ns tAH Address Hold Time 0 - - ns

t

Write Data Setup Time 10 - - ns

DSW

t

Write Data Hold Time 2 - - ns

DHW

t

Read Data Hold Time 10 - - ns

DHR

tOH Output Disable Time - - 30 ns

t

ACC

Access Time (RAM) Access Time (Command) Chip Select Low Pulse Width (read RAM)

PW

Chip Select Low Pulse Width (read command)

CSL

Chip Select Low Pulse Width (write)

PW

Chip Select High Pulse Width (read)

CSH

Chip Select High Pulse Width (write) tR Rise Time - - 10 ns tF Fall Time - - 10 ns

D/C

-

95 40 15 30 30

80

25

-

ns

-

ns

-

WR (R/W)

RD (E)

CS

D0-D

D

7

0-D7

(Write dat a to d river)

(Read data from driver )

t

AS

t

PW

CSL

t

F

t

DSW

Valid Dat a

t

AC C

cycl e

Valid Data

t

AH

PW

CSH

t

R

t

DHW

t

DHR

t

OH

Figure 2a. Parallel 8080-series Interface Timing Characteristics (PS0=H, PS1=L)

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

37

TABLE 4b. Parallel Timing Characteristics (TA=-40 to 85°C, VDD=1.8V,VSS=0V)

Symbol Parameter Min Typ Max Unit

t

Clock Cycle Time 100 - - ns

cycle

tAS Address Setup Time 0 - - ns tAH Address Hold Time 0 - - ns

t

Write Data Setup Time 15 - - ns

DSW

t

Write Data Hold Time 5 - - ns

DHW

t

Read Data Hold Time 15 - - ns

DHR

tOH Output Disable Time - - 40 ns

t

ACC

Access Time (RAM) Access Time (Command) Chip Select Low Pulse Width (read RAM)

PW

Chip Select Low Pulse Width (read command)

CSL

Chip Select Low Pulse Width (write)

PW

Chip Select High Pulse Width (read)

CSH

Chip Select High Pulse Width (write) tR Rise Time - - 10 ns tF Fall Time - - 10 ns

D/C

-

120

55 20 40 40

100

35

-

ns

-

ns

-

WR (R/W)

RD (E)

CS

D0-D

D

7

0-D7

(Write dat a to d river)

(Read data from driver )

t

AS

t

PW

CSL

t

F

t

DSW

Valid Dat a

t

AC C

cycl e

Valid Data

t

AH

PW

CSH

t

R

t

DHW

t

DHR

t

OH

Figure 2b. Parallel 8080-series Interface Timing Characteristics (PS0=H, PS1=L)

38

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

TABLE 5a. Serial Timing Characteristics (T

= -40 to 85°C, VDD = 2.7V, VSS =0V)

A

Symbol Parameter Min Typ Max Unit

t

cycle

t

AS

t

AH

t

CSS

t

CSH

t

DSW

t

OHW

t

CLKL

t

CLKH

t

Clock Cycle Time 66 - - ns Address Setup Time 10 - - ns Address Hold Time 5 - - ns Chip Select Setup Time 10 - - ns Chip Select Hold Time 5 - - ns Write Data Setup Time 10 - - ns Write Data Hold Time 10 - - ns Clock Low Time 10 Clock High Time 20 Rise Time -

R

Fall Time -

F

- -

- 10

-

10 ns

D/C

(Required if PS1 = H)

t

AH

t

CS H

t

CLKH

CS

SCK

t

CSS

t

CLKL

t

AS

t

cycle

ns ns ns

SDA

CS

SCK

SDA

t

F

t

DSW

Valid Data

D7 D6 D5 D4 D3 D2 D1 D0

t

R

t

DHW

Figure 3a. Serial Timing Characteristics (PS0=L)

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

39

TABLE 5b. Serial Timing Characteristics (TA = -40 to 85°C, VDD = 1.8V, VSS =0V)

Symbol Parameter Min Typ Max Unit

t

cycle

t

AS

t

AH

t

CSS

t

CSH

t

DSW

t

OHW

t

CLKL

t

CLKH

t

(Required if PS1 = H)

Clock Cycle Time 70 - - ns Address Setup Time 15 - - ns Address Hold Time 10 - - ns Chip Select Setup Time 15 - - ns Chip Select Hold Time 10 - - ns Write Data Setup Time 15 - - ns Write Data Hold Time 15 - - ns Clock Low Time 15 Clock High Time 30 Rise Time -

R

Fall Time -

F

D/C

t

AH

CS

t

CSS

t

AS

t

CS H

- -

- 10

-

10 ns

ns ns ns

t

cycle

t

CLKH

t

R

t

DHW

SCK

SDA

CS

SCK

SDA

t

CLKL

t

F

t

DSW

Valid Data

D7 D6 D5 D4 D3 D2 D1 D0

40

SSD1850/51 Series

Rev 1.2 01/2003

Figure 3b. Serial Timing Characteristics (PS0=L)

SOLOMON

N

R

W

APPLICATION CIRCUIT

ICONS COM0 : : : : COM38 COM39

Remapped COM SCAN Direction [Command: C8

: : :

:

COM41

Remapped COM

SCAN Direction

[Command: C8

COM79

ICONS

RES#

PS0

CONTOL CIRCUIT

DISPLAY PANEL SIZE

128 X 80 + 1 ICON LINE

………………………………………….………….SEG127

SEG0

Segment Remapped

[Command: A1)

SEG127………………………………………………………………………SEG0

COM40

SSD1851 DIE

81 MUX

PS1

CS#

(DIE FACE IP)

VL3

VL2

REGULATOR DIVIDER CIRCUIT

INTRS

R/

D/C

D0-D7

REF

E

VL6

VL4

VL5

V

C1

C3P

C5P

Vcc

BOOSTER CIRCUIT

C1P

C2P

COM40 COM41 : : : : COM79

COM0

C6P

C4P

Remapped COM SCAN Direction [Command: C8]

: : : : :

: : : : : :

COM38 COM39

Remapped COM

SCAN Direction

[Command: C8

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

41

Application Circuit: DC-DC Converter Circuit Configuration

SSD1850/51 IC works from 2X to 6X DC-DC converter. For the capacitor connections, please refer to below circuit diagrams. Note that if the capacitor connection does not match with the software setting of DC-DC Converter Factor (0x64~0x67), abnormal current consumption will be observed.

Vss

Vcc C5P C3P

C1N

C1P C2P

C2N

C4P

+

Vss

Vcc C5P C3P

C1N

C1P C2P

C2N

C4P

+

+ +

-

2X Converter

3X Converter

*Note: Capacitor value = 1.0uF to 4.7uF *Note: SSD1850 works up to 5X only.

Vss

V

CC

-

+ C5P C3P

C1N

C1P C2P

C2N

+

-

+

-

C4P

4X Converter

Vss

V

CC

C5P C3P

C1N

C1P C2P

C2N

C4P

5X Converter

+

Vss

V

C5P

+

C3P

C1N

C1P C2P

C2N

C4P

6X Converter

CC

+

-

+

-

+

42

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

R

Application Circuit: Regulator Circuit and Bias Divider Circuit

Internal Regulator and Bias Divider

[COMMAND: 2F]

VL6 VL5 VL4 VL3 VL2

VSS

Capacitor = 0.47uF – 2.0uF

Remarks: INTRS = ‘H’

External Regulator and Internal Bias Divider

[COMMAND: 2D]

V

Capacitor = 0.47uF – 2.0uF

VL6 VL5

VL4 VL3 VL2

VSS

Remarks: INTRS = ‘L’

External Regulator Bias Divider

[COMMAND: 28]

VCC

VL6

External VCC

VL5 VL4

VSS

Remarks: INTRS = ‘L’

VL3 VL2

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

43

N

OTP Programming Circuit and Sequence

OTP (One Time Programming) is a method to adjust the VL6. In order to eliminate the variations of LCD module in term of contrast level, OTP can be used to achieve the best contrast of every LCD modules.

OTP setting and programming should include two major steps of (1) Find the OTP offset and (2) OTP programming as following,

Step 1. Find the OTP offset

(1) Hardware Reset (sending an active low reset pulse to RES pin) (2) Send original initialization routines (3) Set and display any test patterns (4) Adjust the contrast value (0x81, 0x00~0x3F) until there is the best visual contrast (5) OTP setting steps = Contrast value of the best visual contrast - Contrast value of original

initialization

Example 1:

Contrast value of original initialization = 0x20 Contrast value of the best visual contrast = 0x24 OTP setting steps = 0x24 - 0x20 = +4 OTP setting commands should be (0x82, 0xF4)

Example 2:

Contrast value of original initialization = 0x20 Contrast value of the best visual contrast = 0x1B OTP setting steps = 0x1B - 0x20 = -5 OTP setting commands should be (0x82, 0xFB)

Step 2. OTP programming

(6) Hardware Reset (sending an active low reset pulse to RES pin) (7) Enable Oscillator (0xAB) (8) Connect an external VCC (see diagram below) (9) Send OTP setting commands that we find in step 1 (0x82, 0xF0~0xFF) (10) Send OTP programming command (0x83) (11) W ait at least 2 seconds (12) Hardware Reset Verify the result by repeating step 1. (2) – (3)

SSD1850/51

VCC

+

GND

C

RES

(8)

(1) & (6) & (12)

R

ote: R = 1K ~ 10k ohm

C = 1u ~ 4.7u F

16-18V

GND

OTP Programming Circuit

44

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

A

)

N

A

Flow Chart of OTP Program

Start

Step 1

(i) Hardware reset (ii) Send original initialization routines (iii) Set and display any test patterns

djust the contrast level to the best visual level

ccept the contrast level on panel?

OTP setting step =

djusted contrast value

– Original contrast value

Yes

Step 2

i) Hardware reset ii) Enable oscillator

Connect an external voltage (16-18V) on V pins

(i) Send OTP setting commands (ii) Send OTP programming command

o

(iii) Wait > 2 sec (iv) Hardware reset

i) Send original initialization routines ii) Set and display any test patterns

Inspect the contrast

iii

cc

END

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

45

OTP Example program

Find the OTP offset:

1. Hardware reset by sending an active low reset pulse to

RES pin

2. COMMAND(0XAB) \\Enable oscillator

COMMAND(0X2F) \\ turn on the internal voltage booster, internal regulator and output

op-amp buffer; Select booster level

3. COMMAND(0X48) \\ Set Duty ratio

COMMAND(0X40) \\ 64Mux

COMMAND(0X55) \\ Set Biasing ratio (1/9 BIAS)

4. COMMAND(0X81) \\ Set target gain and contrast.

COMMAND(0X2D) \\ contrast = 45

COMMAND(0X24) \\ gain = 5.1

5. \\ Set target display contents

COMMAND(0XB0) \\ set page address

COMMAND(0x00) \\ set lower nibble column address

COMMAND(0X10) \\ set higher nibble column address

DATA(…) \\ write target content to GDDRAM

COMMAND(0XAF) \\ Set Display On

6. OTP offset calculation… target OTP offset value is +3

OTP programming:

7. Hardware reset by sending an active low reset pulse to

RES pin

8. COMMAND(0XAB) \\ Enable Oscillator

9. Connect an external VCC (16V-18V)

10. COMMAND(0X82) \\ Set OTP offset value to +3 (0011)

COMMAND(0XF3) \\ 0001 X

3X2X1X0

, where X3X2X1X0 is the OTP offset value

11. COMMAND(0X83) \\ Send the OTP programming command

12. Wait at least 2 seconds for programming wait time

13. Hardware reset by sending an active low reset pulse to

RES pin

Verify the result:

14. After OTP programming, procedure 2 to 5 are repeated for inspection of the contrast on the panel

46

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

SSD1851T TAB PACKAGE DIMENSION (1 OF 3)

DO NOT SCALE THIS DRAWING

SSD1850/51 Series

Rev 1.2 01/2003

S

O

L

O

M

O

N

T

1

5

8

1

D

S

SOLOMON

47

SSD1851T TAB PACKAGE DIMENSION (2 OF 3)

DO NOT SCALE THIS DRAWING

48

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

SSD1851T TAB PACKAGE DIMENSION (3 OF 3)

DO NOT SCALE THIS DRAWING

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

49

SSD1851U COF PACKAGE DIMENSION (1 OF 2)

DO NOT SCALE THIS DRAWING

50

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

SSD1851U COF PACKAGE DIMENSION (2 OF 2)

DO NOT SCALE THIS DRAWING

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

51

Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part.

52

SSD1850/51 Series

Rev 1.2 01/2003

SOLOMON

Datasheet SSD1851Z, SSD1851U, SSD1851TR1, SSD1850Z Datasheet (Solomon Systech)

Specifications and Main Features

Frequently Asked Questions

User Manual