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SPT9687
DUAL UL TRAFAST VOL T AGE COMPARA TOR
FEATURES
• Propagation Delay <2.3 ns
• Propagation Delay Skew <300 ps
• Low Power: 185 mW
• Low Offset ±3 mV
• Low Feedthrough and Crosstalk
• Differential Latch Control
GENERAL DESCRIPTION
The SPT9687 is a dual, very high-speed monolithic comparator. It is pin compatible with, and has improved performance over Analog Device's AD9687. The SPT9687 is
designed for use in Automatic Test Equipment (ATE), highspeed instrumentation, and other high-speed comparator
applications.
BLOCK DIAGRAM
Inverting Input
APPLICATIONS
• High-Speed Instrumentation, ATE
• High-Speed Timing
• Window Comparators
• Line Receivers
• A/D Conversion
• Threshold Detection
Improvements over other sources include reduced power
consumption, reduced propagation delays, and higher input
impedance.
The SPT9687 is available in 16-lead SOIC, 16-lead plastic
DIP, 20-lead PLCC and 20-contact LCC packages over the
industrial temperature range. It is also available in die form.
Noninverting Input
+
Latch Enable
Latch Enable
A
Q Output
V
EE
V
CC
GND
Q Output
Latch Enable
Inverting Input
A
B
B
-
+
Q Output
GND
B
Q Output
Latch Enable
Noninverting Input
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: sales@spt.com
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ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
Positive Supply (VCC to GND).................. -0.5 to +6.0 V
Negative Supply (VEE to GND) ................ -6.0 to +0.5 V
Ground Voltage Differential ...................... -0.5 to +0.5 V
Input Voltages
Input Voltage ............................................ -4.0 to +4.0 V
Differential Input Voltage .......................... -5.0 to +5.0 V
Input Voltage, Latch Controls ..................... VEE to 0.5 V
Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
Output
Output Current......................................................30 mA
Temperature
Operating Temperature, ambient ..............-25 to +85 °C
junction....................... +150 °C
Lead Temperature, (soldering 60 seconds) ...... +300 °C
Storage Temperature ..............................-65 to +150 °C
ELECTRICAL SPECIFICATIONS
T A = +25 °C, VCC = +5.0 V, VEE = -5.20 V, RL = 50 Ohm, unless otherwise specified.
TEST TEST SPT9687
PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS
DC ELECTRICAL CHARACTERISTICS
Input Offset Voltage RS = 0 Ohms
Input Offset Voltage RS = 0 Ohms
T
<TA<T
MIN
Offset Voltage Tempco V 4 µV/°C
Input Bias Current I 6 ±20 µA
Input Bias Current T
Input Offset Current I -1.0 +1.0 µA
Input Offset Current T
Input Common Mode Range I -2.5 +2.5 V
Latch Enable
Common Mode Range IV -2.0 0 V
Open Loop Gain V 4000 V/V
Input Resistance V 60 kΩ
Input Capacitance V 3 pF
Input Capacitance (LCC Package) V 1 pF
Power Supply Sensitivity VCC and V
Common Mode Rejection Ratio IV 50 85 dB
Positive Supply Current I 7 11 mA
Negative Supply Current I 27 37 mA
Positive Supply Voltage IV 4.75 5.0 5.25 V
Negative Supply Voltage IV -4.95 -5.2 -5.45 V
Power Dissipation I
<TA<T
MIN
<TA<T
MIN
OUTPUT
OUTPUT LOGIC LEVELS (ECL 10 KH Compatible)
Output High 50 Ohms to -2 V I -.98 -.81 V
Output Low 50 Ohms to -2 V I -1.95 -1.63 V
AC ELECTRICAL CHARACTERISTICS
2
1
1
MAX
MAX
MAX
EE
= 0 mA I 185 250 mW
III -3 ±.5 +3 mV
IV -3.5 +3.5 mV
IV 7 ±38 µA
IV -1.5 +1.5 µA
IV 50 100 dB
Propagation Delay 10 mV OD III 2.0 2.3 ns
Latch Set-up Time IV 0.6 1 ns
SPT9687
SPT
2 3/21/97
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ELECTRICAL SPECIFICATIONS
T A = +25 °C, VCC = +5.0 V, VEE = -5.20 V, RL = 50 Ohm, unless otherwise specified.
TEST TEST SPT9687
PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS
AC ELECTRICAL CHARACTERISTICS
Latch to Output Delay 50 mV OD IV 3 ns
Latch Pulse Width V 2 ns
Latch Hold Time IV 0.5 ns
Rise Time 20% to 80% V 1.2 ns
Fall Time 20% to 80% V 1.2 ns
1
RS = Source impedance.
2
100 mV input step.
TEST LEVEL CODES
2
TEST LEVEL
TEST PROCEDURE
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
Unless otherwise noted, all tests are pulsed
tests; therefore, TJ = TC = TA.
Figure 1 - Timing Diagram
LATCH ENABLE
LATCH ENABLE
DIFFERENTIAL
INPUT VOLTAGE
OUTPUT Q
I
II
100% production tested at the specified temperature.
100% production tested at TA=25 °C, and sample
tested at the specified temperatures.
III
IV
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
V
Parameter is a typical value for information purposes
only.
VI
100% production tested at TA = 25 °C. Parameter is
guaranteed over specified temperature range.
50%
t
H
t
S
V
OD
t
pdL
tpL
t
pLOH
V
50%
REF
± V
OS
The set-up and hold times are a measure of the time required for an input signal to propagate through the
first stage of the comparator to reach the latching circuitry. Input signals occurring before ts will be detected
and held; those occurring after tH will not be detected. Changes between ts and tH may not be detected.
SPT
OUTPUT Q
t
pdH
VIN+ = 100 mV (p-p), V
50%
t
pLOL
= 50 mV
OD
SPT9687
3 3/21/97
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SWITCHING TERMS (Refer to figure 1)
t
INPUT TO OUTPUT HIGH DELAY - The propagation
pdH
delay measured from the time the input signal
crosses the reference voltage (± the input offset
voltage) to the 50% point of an output LOW to HIGH
transition.
t
INPUT TO OUTPUT LOW DELAY - The propagation
pdL
delay measured from the time the input signal crosses
the reference voltage (± the input offset voltage) to the
50% point of an output HIGH to LOW transition.
t
LATCH ENABLE TO OUTPUT HIGH DELAY - The
pLOH
propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to
50% point of an output LOW to HIGH transition.
V
VOLTAGE OVERDRIVE - The difference between
OD
the differential input and the reference voltages.
t
LATCH ENABLE TO OUTPUT LOW DELAY - The
pLOL
propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to the
50% point of an output HIGH to LOW transition.
t
MINIMUM HOLD TIME - The minimum time after the
H
negative transition of the Latch Enable signal that the
input signal must remain unchanged in order to be
acquired and held at the outputs.
t
MINIMUM LATCH ENABLE PULSE WIDTH - The
pL
minimum time that the Latch Enable signal must be
HIGH in order to acquire an input signal change.
t
MINIMUM SET-UP TIME - The minimum time before
S
the negative transition of the Latch Enable signal that
an input signal change must be present in order to be
acquired and held at the outputs.
TIMING INFORMATION
The timing diagram for the comparator is shown in figure 1.
The latch enable (LE) pulse is shown at the top. If LE is high
and LE low in the SPT9687, the comparator tracks the
input difference voltage. When LE is driven low and
high, the comparator outputs are latched into their existing
logic states.
The leading edge of the input signal (which consists of a
50 mV overdrive voltage) changes the comparator output
after a time of t
pdL
or t
(Q or Q). The input signal must be
pdH
maintained for a time ts (set-up time) before the LE falling
edge and LE rising edge and held for time tH after the falling
edge for the comparator to accept data. After tH, the output
ignores the input status until the latch is strobed again. A
minimum latch pulse width of tpL is needed for strobe
operation, and the output transitions occur after a time of
t
pLOH
or t
pLOL
.
LE
GENERAL INFORMATION
The SPT9687 is an ultrahigh-speed dual voltage comparator. It offers tight absolute characteristics. The device has
differential analog inputs and complementary logic outputs
compatible with ECL systems. The output stage is adequate
for driving terminated 50 ohm transmission lines.
The SPT9687 has a complementary latch enable control for
each comparator. Both should be driven by standard ECL logic
levels.
The dual comparator shares the same VCC and VEE connections but have separate grounds for each comparator to
achieve high crosstalk rejection.
Figure 2 - Internal Functional Diagram
V
IN
V
IN
V
EE
+
PRE
AMP
-
REF1REF
V
CC
LATCH
2
GND
CLK
BUF
LE
1
LE
ECL
OUT
GND
2
Q
Q
TYPICAL INTERFACE CIRCUIT
The typical interface circuit using the comparator is shown
in figure 3. Although it needs few external components
and is easy to apply, there are several conditions that
should be met to achieve optimal performance. The very
high operating speeds of the comparator require careful
layout, decoupling of supplies, and proper design of transmission lines.
Since the SPT9687 comparator is a very high frequency and
high gain device, certain layout rules must be followed to
avoid spurious oscillations. The comparator should be soldered to the board with component lead lengths kept as short
as possible. A ground plane should be used, and the input
impedance to the part should be kept as low as possible to
decrease parasitic feedback. If the output board traces are
longer than approximately one-half inch, microstripline techniques must be employed to prevent ringing on the output
waveform. Also, the microstriplines must be terminated at
the far end with the characteristic impedance of the line to
prevent reflections. All supply voltage pins should be decoupled with high frequency capacitors as close to the
device as possible. All ground and N/C pins should be
connected to the same ground plane to further improve noise
immunity and shielding. If using the SPT9687 as a single
comparator, the outputs of the inactive comparator can be
grounded, left open or terminated with 50 Ohms to -2 V. All
outputs on the active comparator, whether used or unused,
should have identical terminations to minimize ground current switching transients.
Note: To ensure proper power up of the device, the input
should be kept below +1.5 V during power up.
SPT
SPT9687
4 3/21/97
Page 5
Hysteresis is obtained by applying a DC bias to the LE pin.
V
LE
= -1.3 V ±100 mV, VLE = -1.3 V.
Represents line termination.
V
EE
V
CC
V
IN
V
REF
Noninverting
Input
Inverting
Input
GND
.1 µF
Q OUTPUT
+
-
Q OUTPUT
LE
300 Ω
-5.2 V
V
O
V
IN
V
LE
100 Ω
100 Ω
V
LE
0.1 µF
300 Ω
LE
.1 µF
R
L
50 Ω
-2 V
R
L
50 Ω
-5.2 V
Figure 3 - Typical Interface Circuit Figure 4 - Typical Interface With Hysteresis
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V
CC
GND
V
EE
.1 µF
Noninverting
Input
V
IN
V
Ref
Inverting
+
-
Q Output
Q Output
Input
R
50 Ω
LE LE
R
50 Ω
L
L
.1 µF
-2 V
ECL
= Represents line termination.
Figure 5 - Equivalent Input Circuit Figure 6 - AC Test Fixture
V
V
CC
C
IN
1 pF
R
IN
V
IN
100 Ω
R
IN
V
IN
100 Ω
V
R2
V
R1
V
EE
Figure 7 - Output Circuit
Q Output
C
1 pF
Q
23
V
Q
3
R
1
IN
Q
1
Q
4
Q
2
R
3
R
2
Q
5
Q
6
Q
8
R
4
Q
9
Q
11
Q
7
V
PRE
V
Q10Q
12
R
5
R6R
7
+
V
IN
-
V
IN
PRE
Figure 8 - Test Load
4.5 mA
R
240 Ω
Q
22
8
Q
24
V
2
Q Output
R
7
240 Ω
1
Q
21
MONITOR
6
L1
6
SEMIRIGID
6
SEMIRIGID
50
L1
6666
MONITOR
R
100 Ω
+
IN
SEMI
RIGID
50
SEMI
RIGID
L
(-4.0 V)
V
CC
(+5.0 V)
15 µF
L2
100
0.1 µF
50
V+
Q
4
DUT
Q
V-+-
LE
LE
L2
100
100
SEMI
RIGID
R
z
GND
L3
0.1 µF
100
0.1 µF
50
SEMI
RIGID
LELELE
MONITOR
50
100
50
0.1 µF
L1
SEMI
RIGID
V
(-5.2 V)
EE
LE
6
SEMI
RIGID
6
SEMI
RIGID
15 µF
15 µF
TANT
--
+
+
V
pD
(-4.0 V)
50
SAMPLING
SCOPE
+
V
OUT
-
V
OUT
50 Ω Coax
50 Ω
R
Z
100 Ω
V
pd
SPT
SPT9687
5 3/21/97
Page 6
16
1
PACKAGE OUTLINES
16-Lead Plastic DIP
G
INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX
A 0.300 7.62
B 0.014 0.026 0.36 0.66
C .100 typ 2.54
D .010 typ 0.25
E 1.150 1.950 29.21 49.53
F 0.290 0.330 7.37 8.38
G 0.246 0.254 6.25 6.45
H 0.740 0.760 18.80 19.30
H
A
D
C
B
F
E
20-Contact Leadless Chip Carrier (LCC)
A
Bottom
B
C
View
D
H
G
Pin 1
F
SYMBOL MIN MAX MIN MAX
C 0.045 0.055 1.14 1.40
D 0.345 0.360 8.76 9.14
G 0.022 0.028 0.56 0.71
H 0.075 1.91
INCHES MILLIMETERS
A .040 typ 1.02
B .050 typ 1.27
E 0.054 0.066 1.37 1.68
F .020 typ 0.51
SPT
E
SPT9687
6 3/21/97
Page 7
PACKAGE OUTLINES
20-Lead Plastic Leaded Chip Carrier (PLCC)
A
B
G
Pin 1
Pin 1
TOP
VIEW
C
D
BOTTOM
VIEW
E
N
M
F
O
SYMBOL MIN MAX MIN MAX
L
K
J
I
H
INCHES MILLIMETERS
A .045 typ 1.14
B
C 0.350 0.356 8.89 9.04
D 0.385 0.395 9.78 10.03
E 0.350 0.356 8.89 9.04
F 0.385 0.395 9.78 10.03
G 0.042 0.056 1.07 1.42
H 0.165 0.180 4.19 4.57
I 0.085 0.110 2.16 2.79
J 0.025 0.040 0.64 1.02
K 0.015 0.025 0.38 0.64
L 0.026 0.032 0.66 0.81
M 0.013 0.021 0.33 0.53
N 0.050 1.27
O 0.290 0.330 7.37 8.38
16-Lead Small Outline Integrated Circuit (SOIC)
F
16
1
C
DE
INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX
A 0.150 0.157 3.81 3.99
B 0.230 0.244 5.84 6.20
C 0.386 0.393 9.80 9.98
D .050 Typ 1.27 Typ
E 0.0138 0.0192 0.35 0.49
A
B
G
F 0.004 0.0098 0.127 0.25
G 0.061 0.068 1.55 1.73
H 0.0075 0.0098 0.19 0.25
I 0.055 0.061 1.40 1.55
I
H
SPT
SPT9687
7 3/21/97
Page 8
PIN ASSIGNMENTS
PIN FUNCTIONS
GND
LE
N/C
LE
V
Q
-IN
Q
16
B
Q
15
B
GND
14
LE
13
B
LE
12
B
V
11
CC
-IN
10
B
+IN
B
18
17
16
15
14
B
Q
1
A
Q
2
A
GND
3
A
LE
4
A
LE
5
A
V
6
EE
-IN
7
A
+IN
89
A
PDIP/SOIC
Q
Q
A
3 2 1 20 19
4
A
5
A
6
7
A
8
EE
TOP VIEW
9 10111213
-INA+IN
LCC/PLCC
Q
N/C
A
A
N/C
+IN
B
B
B
B
GND
LE
B
N/C
LE
V
CC
NAME FUNCTION
Q
A
Q
A
GND
A
LE
A
LE
A
V
EE
-IN
A
+IN
A
+IN
B
-IN
B
B
B
V
CC
LE
B
LE
GND
Q
B
Q
B
B
B
Output A
Inverted Output A
Ground A
Latch Enable A
Inverted Latch Enable A
Negative Supply Voltage
Inverting Input A
Non-Inverting Input A
Non-Inverting Input B
Inverting Input B
Positive Supply Voltage
Latch Enabled B
Inverted Latch Enable B
Ground B
Output B
Inverted Output B
ORDERING INFORMATION
PART NUMBER Temperature Range PACKAGE TYPE
SPT9687SIN -25 to +85 °C 16L PDIP
SPT9687SIP -25 to +85 °C 20L PLCC
SPT9687SIC -25 to +85 °C 20C LCC
SPT9687SIS -25 to +85 °C 16L SOIC
SPT9687SCU +25 °C Die*
*Please see the die specification for guaranteed electrical performance.
Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby
expressly granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited.
WARNING - LIFE SUPPORT APPLICATIONS POLICY - SPT products should not be used within Life Support Systems without the specific
written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably
expected to result in significant personal injury or death.
Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device
failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.
SPT9687
SPT
8 3/21/97
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