Datasheet SPT7935SIT Datasheet (SPT)

SPT7935

12-BIT, 20 MSPS, 79 mW A/D CONVERTER

FEATURES

• 12-Bit, 20 MSPS Analog-to-Digital Converter

• Monolithic CMOS

• Internal Track-and-Hold

• Low Input Capacitance: 1.4 pF

• Low Power Dissipation: 79 mW

• 2.8 – 3.6 V Power Supply Range

• TTL-Compatible Outputs

GENERAL DESCRIPTION

The SPT7935 12-bit, 20 MSPS analog-to-digital converter
has a pipelined converter architecture built in a CMOS
process. It delivers high performance with a typical power
dissipation of only 79 mW. With low distortion and high
dynamic range, this device offers the performance needed

BLOCK DIAGRAM

APPLICATIONS

• CCD Imaging Cameras and Sensors

• Medical Imaging

• RF Communications

• Document and Film Scanners

• Electro-Optics

• Transient Signal Analysis

• Handheld Equipment

for imaging, multimedia, telecommunications and instrumen­tation applications.

The SPT7935 is available in a 44-lead Thin Quad Flat Pack
(TQFP) package in the industrial temperature range (–40 to
+85 °C).

–

G=2

Stage

10

2-Bit
ADC

V

V

VIN+
V

IN

REF

REF

CLK

DACADC +

D<1…0> Pipeline Stage

–

+

–

Clock

Driver

Stage

1

Stage

2

Digital Delays, Error Correction and Output

Digital Output (D0 – D11)

Stage

9

12

Signal Processing Technologies, Inc.

4755 Forge Road, Colorado Springs, Colorado 80907, USA

Phone: [phone] FAX: [phone] Website: http://www.spt.com E-Mail: [e-mail]

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C

Supply Voltages

V

....................................................................

DD

1

V

....................................................................

DD

2

V

....................................................................

DD

3

–0.5 V to +6 V
–0.5 V to +6 V
–0.5 V to +6 V

Temperature

Operating Temperature ............................. –40 to +85 °C

Storage Temperature............................... –65 to +125 °C

Input Voltages

Analog Input.................................–0.5 V to (VDD +0.5 V)

Digital Input .................................. –0.5 V to (VDD +0.5 V)

V

+ .......................................... –0.5 V to (VDD +0.5 V)

REF

V

– .......................................... –0.5 V to (VDD +0.5 V)

REF

CLK .............................................. –0.5 V to (VDD +0.5 V)

Note: 1. Operation at any Absolute Maximum Rating is not

implied. See Electrical Specifications for proper
nominal applied conditions in typical applications.

ELECTRICAL SPECIFICATIONS

TA=T

MIN–TMAX

Bias 2=9.5 µA, Differential Input, Duty Cycle=50%, unless otherwise specified.

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS

DC Accuracy

Resolution 12 Bits
Differential Linearity V ±0.6 LSB
Integral Linearity V ±3.0 LSB
No Missing Codes VI Guaranteed

Analog Input

Input Voltage Range (Differential) IV ±0.6 ±1.0 ±1.7 V
Common Mode Input Voltage IV 1.2 1.65 1.9 V
Input Capacitance V 1.4 pF
Input Bandwidth (Large Signal) V 120 MHz
Offset (Mid-scale) VIN+=VIN–=V
Gain Error V 0.3 % FSR

Reference Voltages

Reference Input Voltage Range IV 0.6 1.0 1.7 V
Negative Reference Voltage (V

Positive Reference Voltage (V
Common Mode Output Voltage (VCM)IO = –1 µA VI 1.3 1.65 1.8 V
V

REF

V

REF

Switching Performance

Maximum Conversion Rate VI 20 MHz
Pipeline Delay IV 7.5 Clocks

(See Timing Diagram)

Aperture Delay Time (T
Aperture Jitter Time V 10 ps-rms

Dynamic Performance

Effective Number of Bits

Signal-To-Noise Ratio

Total Harmonic Distortion

, V

=V

=V

DD

2

=3.3 V, V

DD

3

DD

1

–=1.0 V, V

REF

+=2.0 V, Common Mode Voltage=1.65 V, ƒ

REF

=20 MSPS, Bias 1=90 µA,

CLK

TEST TEST SPT7935

V ±1.0 % FSR

(V

REF

+ – V

REF

–)

CM

–) IV 0.9 1.0 1.3 V

REF

+) IV 1.9 2.0 2.6 V

REF

+ Current V 35 µA
– Current V –25 µA

)V5ns

AP

ƒ

= 5.0 MHz VI 9.2 9.8 Bits

IN

ƒIN = 10.0 MHz V 9.0 Bits
ƒIN = 5.0 MHz VI 59 62 dB

ƒIN = 10.0 MHz V 58 dB
ƒ

= 5.0 MHz VI –68 –61 dB

IN

ƒ

= 10.0 MHz V –60 dB

IN

SPT

SPT7935

2 7/12/00

ELECTRICAL SPECIFICATIONS

TA=T

MIN–TMAX

Bias 2=9.5 µA, Differential Input, Duty Cycle=50%, unless otherwise specified.

, V

DD

=V

=V

2

=3.3 V, V

DD

3

DD

1

–=1.0 V, V

REF

+=2.0 V, Common Mode Voltage=1.65 V, ƒ

REF

=20 MSPS, Bias 1=90 µA,

CLK

TEST TEST SPT7935

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS

Dynamic Performance–Continued

Signal-To-Noise and Distortion

ƒ

= 5 MHz VI 57 61 dB

IN

ƒIN = 10 MHz V 56 dB

Spurious Free Dynamic Range

ƒIN = 5.0 MHz VI 62 70 dB

ƒIN = 10.0 MHz V 61 dB
Differential Phase V 0.2 Degrees
Differential Gain V 0.5 %

Digital Inputs

Logic 1 Voltage VI 80% V
Logic 0 Voltage VI 20% V

DD

DD

Maximum Input Current Low VIN = GND VI ±1 µA
Maximum Input Current High V

IN

= V

DD

VI ±1 µA

Input Capacitance V 1.8 pF

Digital Outputs

Logic 1 Voltage I

= -2 mA VI 85% V

O

DD

95% V

DD

V
Logic 0 Voltage IO = +2 mA VI 0.1 0.4 V
CLK to Output Delay Time (tD)IV4812ns

Power Supply Requirements

Supply Voltages

V

, V

DD1

DD2

, V

DD3

IV 2.8 3.3 3.6 V

Supply Current

I

DD

VI 24 30 mA
Power Dissipation VI 79 100 mW
Power Supply Rejection Ratio (PSRR) V 67 dB

TEST LEVEL CODES

All electrical characteristics are subject to the
following conditions: All parameters having
min/max specifications are guaranteed. The
Test Level column indicates the specific
device testing actually performed during pro­duction and Quality Assurance inspection.
Any blank section in the data column indi­cates that the specification is not tested at the
specified condition.

TEST LEVEL

I

II

III
IV

V

VI

TEST PROCEDURE

100% production tested at the specified temperature.
100% production tested at TA = +25 °C, and sample tested at

the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and

characterization data.
Parameter is a typical value for information purposes only.
100% production tested at TA = +25 °C. Parameter is guaran-

teed over specified temperature range.

SPT

SPT7935

3 7/12/00

2

2

2

TYPICAL PERFORMANCE CHARACTERISTICS

THD, SNR, SINAD vs Input Frequency

80

70

60

50

40

THD, SNR, SINAD (dB)

30

20

0

10

THD, SNR, SINAD vs Temperature

70

68

66

64

62

60

THD, SNR, SINAD (dB)

58

1

Input Frequency (MHz)

10

THD

SNR
SINAD

THD

SNR

SINAD

80

70

60

50

40

THD, SNR, SINAD (dB)

30

20

10

10

150

125

100

75

50

Power Dissipation (mW)

25

THD, SNR, SINAD vs Sample Rate

THD

SNR
SINAD

0

Sample Rate (MSPS)

Note: Bias1 and Bias2 currents optimized for each sample rate.

10

THD
SNR

SINAD

1

Power Dissipation vs Sample Rate

10

56

02570

Temperature (°C)

0

10

Bias 1 Voltage vs Bias 1 Current

3.4

3.2

3.0

2.8

2.6

VBias1 (V)

2.4

2.2

2.0
0 30 60 90 120 150 180

SPT

IBias1 VBias1

30 2.19
60 2.53

90 2.79
120 3.00
150 3.22

IBias1 (µA)

4 7/12/00

0.90

0.85

0.80

0.75

0.70

VBias2 (V)

0.65

0.60

0

Sample Rate (MSPS)

Note: Bias1 and Bias2 optimized for each sample rate.

1

10

Bias 2 Voltage vs Bias 2 Current

IBias2 VBias2

3 0.6975
6 0.7535

9 0.796
12 0.8295
15 0.8595

0 3 6 9 12 15 18

IBias2 (µA)

SPT7935

10

Figure 1 – Timing Diagram

Sampling Points

A

IN

CLK

D

OUT

N-1

N

N+1

t

AP

N+2

t

D

N+6

N+7

N+8

N-2 N-1 N

GENERAL DESCRIPTION

The SPT7935 is an ultra-low power, 12-bit, 20 MSPS ADC.
It has a pipelined architecture and incorporates digital error
correction of the 11 most significant bits. This error correction
ensures good linearity performance for input frequencies up
to Nyquist. The inputs are fully differential, making the device
insensitive to system-level noise. This device can also be
used in a single-ended mode. (See analog input section.)
With the power dissipation roughly proportional to the sam­pling rate, this device is ideal for very low power applications
in the range of 1 to 20 MSPS.

Figure 2 – Typical Interface Circuit

+

68 pF

4.7 µF

.01 µF

12

22

+

N/C
N/C
N/C
GND
Bias1
Bias2
V

CM

GND
VIN+
V

IN

GND

23

11

V

V

REF

REF

–

+

–

RF In

.01 µF

Minicircuit

T1-6T

90 µA

9.5 µA

Ref– In

(+1.15 V)

Ref+ In

(+2.15 V)

(+1.65 V)

51

4.7 µF

TYPICAL INTERFACE CIRCUIT

The SPT7935 requires few external components to achieve
the stated operation and performance. Figure 2 shows the
typical interface requirements when using the SPT7935 in
normal circuit operation. The following sections provide
a description of the functions and outline critical perform­ance criteria to consider for achieving the optimal device
performance.

ANALOG INPUT

The input of the SPT7935 can be configured in various ways
depending on if a single-ended or differential, AC- or DC­coupled input is desired.

.01 µF

V

V

DD1

DD1

SPT7935

GND

+3.3 V CLK In

10 µF

+

.01 µF

V

V

DD2

DD1

U1

V

DD2

AGND

V

DD3

(3 V Logic)

CLK

GND

N/C

V

D11

D10

33

0.1 µF

1

DD3

D0
D1
D2
D3
D4
D5
D6
D7
D8

D9

+3.3 V

44

(LSB)

34

(MSB)

FB

+3.3 V Digital

Decoupling Cap

Interfacing

3 V Logic

DGND

SPT

Notes: All V

DD1

, V

DD2

and V

should be tied together.

DD3

FB = Ferrite Bead; must be placed as close to U1 as possib le.

SPT7935

5 7/12/00

The AC coupled input is most conveniently implemented
using a transformer with a center tapped secondary winding.
The center tap is connected to the VCM pin as shown in
figure 2. To obtain low distortion, it is important that the
selected transformer does not exhibit core saturation at the
full-scale voltage. Proper termination of the input is important
for input signal purity. A small capacitor across the inputs
attenuates kickback noise from the internal sample and hold.

Figure 3 illustrates a solution (based on operational amplifi­ers) that can be used if a DC coupled single-ended input is
desired. The selection criteria of the buffer op-amps is as
follows:

– Open loop gain >75 dB
– Gain bandwidth product >50 MHz
– Total harmonic distortion ≤–75 dB
– Signal to noise ratio >75 dB

POWER SUPPLIES AND GROUNDING

The SPT7935 is operated from a single power supply in the
range of 2.8 to 3.6 volts. Nominal operation is suggested to
be 3.3 volts. All power supply pins should be bypassed as
close to the package as possible. The analog and digital
grounds should be connected together with a ferrite bead as
shown in the typical interface circuit and as close to the ADC
as possible.

REFERENCES

COMMON MODE VOLTAGE
REFERENCE CIRCUIT

The SPT7935 has an on-board common mode voltage refer­ence circuit (VCM). It is typically one-half of the supply voltage
and can drive loads of up to 20 µA. This circuit is commonly
used to drive the center tap of the RF transformer in fully
differential applications. For single-ended applications, this
output can be used to provide the level shifting required for
the single-to-differential converter conversion circuit.

BIAS CURRENT CIRCUITS

The bias currents suggested (Bias 1 and Bias 2 in figure 2)
optimize device performance for the stated sample rate of
20 MSPS. To achieve the best dynamic performance when
operating the device at sample rates other than 20 MSPS, the
bias current levels should be adjusted. Table I shows the
settings for Bias 1 and Bias 2 for selected sample rates. The
“Bias Voltage vs Bias Current” graphs on page 4 show the
relationship between the bias current and the bias voltage.

Table I – Sample Rate Settings

Sample Rate (MHz) Bias 1 (µA) Bias 2 (µA)

1 20 3.5

5 50 6.5
10 80 8.0
20 90 9.5

The SPT7935 has a differential analog input. The voltages
applied to the V
voltage range and are equal to ±(V

REF

+ and V

- pins determine the input

REF

+ – V

REF

REF

–). This
voltage range will be symmetric about the common mode
voltage. Externally generated reference voltages must be
connected to these pins. (See figure 2, Typical Interface
Circuit.) For best performance, these voltages should be
symmetrical about the midpoint of the supply voltage.

Figure 3 – DC-Coupled Single Ended to Differential Conversion (Power Supplies and Bypassing are Not Shown)

V

CM

Input

Voltage

(±0.5 V)

R3

(R3)/2

R3

–
+

R

R2

R2

51 Ω

R

RR

R

ADC

–
+

+
–

51 Ω

15 pF

51 Ω

VIN+

VIN–

SPT

SPT7935

6 7/12/00

CLOCK

INCHES MILLIMETERS

SYMBOL MIN MAX MIN MAX

A 0.472 Typ 12.00 Typ
B 0.394 Typ 10.00 Typ
C 0.394 Typ 10.00 Typ
D 0.472 Typ 12.00 Typ
E 0.031 Typ 0.80 Typ
F 0.012 0.018 0.300 0.45
G 0.053 0.057 1.35 1.45
H 0.002 0.006 0.05 0.15

I 0.018 0.030 0.450 0.750
J 0.039 Typ 1.00 Typ
K 0-7° 0-7°

DIGITAL OUTPUTS

The SPT7935 accepts a low voltage CMOS logic level at
the CLK input. The duty cycle of the clock should be kept as
close to 50% as possible. Because consecutive stages in the
ADC are clocked in opposite phase to each other, a non-50%
duty cycle reduces the settling time available for every other
stage and thus potentially causing a degradation of dynamic
performance.

For optimal performance at high input frequencies, the clock
should have low jitter and fast edges. The rise/fall times
should be kept shorter than 2 ns. Overshoot and undershoot
should be avoided. Clock jitter causes the noise floor to rise
proportional to the input frequency. Because jitter can be
caused by crosstalk on the PC board, it is recommended that
the clock trace be kept as short as possible and standard
transmission line practices be followed.

The digital output data appears in an offset binary code at

3.3 V CMOS logic levels. A negative full scale input results in
an all zeros output code (000…0). A positive full scale input
results in an all 1’s code (111…1). The output data is available

7.5 clock cycles after the data is sampled. The input signal is
sampled on the high to low transition of the input clock. Output
data should be latched on the low to high clock transition as
shown in figure 1, the Timing Diagram. The output data is
invalid for the first 20 clock cycles after the device is powered up.

EVALUATION BOARD

The EB7935 Evaluation Board is available to aid designers in
demonstrating the full performance capability of the
SPT7935. The board includes an on-board clock driver,
adjustable voltage references, adjustable bias current cir­cuits, single-to-differential input buffers with adjustable lev­els, a single-to-differential transformer (1:1), digital output
buffers and 3.3/5 V adjustable logic outputs. An application
note (AN7935) is also available which describes the opera­tion of the evaluation board and provides an example of the
recommended power and ground layout and signal routing.
Contact the factory for price and availability.

A

B

Index

Pin 1

G

SPT

H

E F

PACKAGE OUTLINE

44L TQFP

C

D

K

I

J

7 7/12/00

SPT7935

PIN ASSIGNMENTS PIN FUNCTIONS

D0 (LSB)

V

V

GND

CLK

V

DD3

V

DD2

V

DD2

V

DD1

V

DD1

V

DD1

REF

REF

N/C

V

DD3

D1

D3

D4

D2

44

1
2
3
4
5
6
7
8
9

-

10

+

11

12

N/C

43

13

N/C

42

14

N/C

41

15

N/C

40

16

Bias 1

17

39

Bias 2

38

18

CM

D6

D7D8D9

D5

37

36

35

34

D10

33

D11 (MSB)

32
31

GND

30

GND
GND

29

GND

28

GND

27

GND

26

GND

25

GND

24

GND

19

20

GND

V

V

IN

+

23

21

22

GND

V

IN

-

Name Function

VIN+, VIN– Analog Inputs
V

REF

+, V

– External Reference Inputs

REF

CLK Input Clock
V

CM

Bias 1 Bias Current (90 µA typ)
Bias 2 Bias Current (9.5 µA typ)
D0 – D11 Digital Outputs (D0 = LSB)
GND Analog Ground
V

DD

1

V

DD

2

V

DD

3

N/C No Connect Pins. Recommended to

Common Mode Output Voltage
(1.65 V typ)

Analog Power Supply
Digital Power Supply
Digital Output Power Supply

connect to analog ground.

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE TYPE

SPT7935SIT –40 to +85 °C 44L TQFP

Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby expressly
granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited.

WARNING – LIFE SUPPORT APPLICATIONS POLICY – SPT products should not be used within Life Support Systems without the specific
written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably
expected to result in significant personal injury or death.

Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device
failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.

SPT7935

SPT

8 7/12/00