Datasheet SPT7864SIR Datasheet (SPT)

Signal Processing Technologies, Inc.

4755 Forge Road, Colorado Springs, Colorado 80907, USA

Phone: [phone] Fax: [phone] Web Site: http://www .spt.com e-mail: [e-mail]

SPT7864

10-BIT, 40 MSPS A/D CONVERTER

PRELIMINARY INFORMATION

APPLICATIONS

• High-speed applications where low power dissipation is
required

• Video imaging

• Medical imaging

• Radar receivers

• IR imaging

• Digital communications

FEATURES

• 40 MSPS maximum sample r ate

• 9.5 eff ectiv e n umber of bits at ƒIN = 10 MHz and
ƒS = 40 MSPS

•2 V

P-P

full-scale input range

• Diff erential input 2.5 V common mode

• Internal or external voltage ref erence

• Common-mode v oltage reference output

• +3.3 V / +5 V digital output logic compatibility

• +5 V analog power supply

GENERAL DESCRIPTION

The SPT7864 is a 10-bit, 40 MSPS analog-to-digital con­verter with low power dissipation at only 395 mW typical at
40 MSPS with a power supply of +5.0 V. The digital outputs
are +3 V or +5 V, and are user selectable. The SPT7864
has incorporated proprietary circuit design and CMOS

processing technologies to achieve its advanced perfor­mance. Inputs and outputs are TTL/CMOS compatible to
interface with TTL/CMOS logic systems. Output data for­mat is straight binary.

The SPT7864 is available in a 28-lead SSOP package
over the industrial temperature range.

BLOCK DIAGRAM

Bias

Cell

V

CM

V

DD

GND

10-BIT

40 MSPS

ADC

THA

V

IN

Data

Output

Latches

& Buffers

10

10

GND OV

DD

Bandgap

Reference

2

CLK, CLK

V

IN

REF

H

REF

L

Sleep

1

OR

EXT/INT

D0D9

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SPT7864

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C

Supply V oltages

VDD....................................................................... TBD

OVDD..................................................................... TBD

Input V oltages

Analog Input .......................................................... TBD

CLK Input .............................................................. TBD

Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical

applications.

Output

Digital Outputs....................................................... TBD

T emperature

Operating Temperature ........................... –40 to +85 °C

Storage Temperature ............................ –65 to +150 °C

ELECTRICAL SPECIFICATIONS

TA=T

MIN

to T

MAX

, VDD=+5.0 V , ƒS=40 MSPS, V

RHS

=3.0 V, V

RLS

=2.0 V, unless otherwise specified.

TEST TEST SPT7864

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS
Resolution 10 Bits
DC Accuracy

Differential Linearity Error (DLE) @ +25 °C V ±0.4 LSB

full temperature ±0.75 LSB

Integral Linearity Error (ILE) @ +25 °C V ±0.5 LSB

full temperature ±1.0 LSB

No Missing Codes VI Guaranteed

Analog Input

Input Voltage Range (Differential) V ±1 V
Input Common Mode V 2.5 V
Input Capacitance V 2 pF
Common Mode Rejection Ratio (CMRR) TBD

Timing Characteristics

Conversion Rate VI 40 MSPS
Pipeline Delay (Latency) IV 7 clocks
Output Delay (t

D

) IV TBD TBD TBD ns
Aperture Delay Time V TBD ns
Aperture Jitter Time V TBD ps (rms)

Dynamic Performance

Effective Number of Bits (ENOB)

ƒ

IN

= 10 MHz, ƒ

CLK

= 40 MSPS 25 °C I 9.3 9.5 Bits

–40 °C to +85 °C IV 9.0 9.2 Bits

Signal-to-Noise Ratio (SNR)

ƒ

IN

= 10 MHz, ƒ

CLK

= 40 MSPS 25 °C I 58 59 d B

–40 °C to +85 °C IV 57 5 8 dB

Total Harmonic Distortion (THD)

ƒ

IN

= 10 MHz, ƒ

CLK

= 40 MSPS 25 °C I –71 –68 dB

–40 °C to +85 °C IV –70 –67 dB

Signal-to-Noise and Distortion (SINAD)

ƒ

IN

= 10 MHz, ƒ

CLK

= 40 MSPS 25 °C I 58 59 d B

–40 °C to +85 °C IV 56 5 7 dB

Spurious Free Dynamic Range (SFDR)

ƒ

IN

= 10 MHz, ƒ

CLK

= 40 MSPS 25 °C I 70 73 d B

–40 °C to +85 °C IV 68 7 1 dB

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SPT7864

ELECTRICAL SPECIFICATIONS

TA=T

MIN

to T

MAX

, VDD=+5.0 V , ƒS=40 MSPS, V

RHS

=3.0 V, V

RLS

=2.0 V, unless otherwise specified.

TEST TEST SPT7864

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS
Power Supply Requirements

V

DD

Voltage (Analog Supply) IV 4.75 5.0 5.25 V

OV

DD

Voltage (Output Supply) IV 2.7 3.3/5.0 5.25 V

V

DD

Current VI 74 mA

OV

DD

Current VI 8 mA

Power Dissipation

External Voltage Reference VI 387 417 mW
Internal Voltage Reference VI 395 425 mW

Sleep Mode Power Dissipation

External Voltage Reference VI TBD TBD mW
Internal Voltage Reference VI TBD TBD mW

Power Supply Rejection Ratio (PSRR) V TBD mV/V

Internal References

Common Mode Voltage Reference (V

CM

) IO = –1 µA VI TBD 2.5 TBD V
Common Mode Voltage Tempco V 100 ppm/°C
Output Impedance V TBD kΩ
Current Capability VI TBD µA
Reference Low Output Voltage (V

REFL

) (EXT/INT) = 0 VI 1.95 2.0 2.05 V

Reference High Output Voltage (V

REFH

) (EXT/INT) = 0 VI 2.95 3.0 3.05 V

External References

Reference Low Input Voltage Range (EXT/INT) = 1 IV 1.7 2.0 2.3 V
Reference High Input Voltage Range (EXT/INT) = 1 IV 2.7 3.0 3.3 V

Digital Outputs

Output Voltage High IO = –2 mA VI 85% OV

DD

90% OV

DD

OV

DD

V

Output Voltage Low IO = 2 mA VI 0.2 0.4 V

Digital Inputs

Input High Voltage VI 80% V

DD

V

Input Low Voltage VI 20% V

DD

V
Input High Current VI ±10 µA
Input Low Current VI ±10 µA

Clock Inputs

Clock Inputs High Voltage VI 2 5 V
Clock Inputs Low Voltage VI 0.4 V

TEST LEVEL CODES

All electrical characteristics are subject to the
following conditions:

All parameters having min/max specifications are
guaranteed. The Test Level column indicates the
specific device testing actually performed during
production and Quality Assurance inspection. Any
blank section in the data column indicates that the
specification is not tested at the specified
condition.

TEST PROCEDURE

100% production tested at the specified temperature.
100% production tested at TA = +25 °C, and sample tested

at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and

characterization data.
Parameter is a typical value for information purposes only.
100% production tested at TA = +25 °C. Parameter is

guaranteed over specified temperature range.

TEST LEVEL

I

II

III
IV

V

VI

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SPT7864

INCHES MILLIMETERS

SYMBOL MIN MAX MIN MAX

A 0.397 0.407 10.07 10.33
B 0.002 0.008 0.05 0.21
C 0.0256 typ 0.65 typ
D 0.010 0.015 0.25 0.38
E 0.004 0.008 0.09 0.20
F 0.066 0.070 1.68 1.78
G 0.025 0.037 0.63 0.95
H 0.301 0.311 7.65 7.90

I 0.205 0.212 5.20 5.38

Figure 1 – Driving Differential Inputs with a

Differential Configuration

Figure 2 – Driving Differential Inputs with a Single-

Ended Configuration

V

IHD

V

ICM

V

ILD

V

ID

V

IH

V

ICM

V

IL

PACKAGE OUTLINE

28-Lead SSOP

1

28

A

B

CD

E

F

G

I

H

H

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SPT7864

Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is
hereby expressly granted to copy this literature for informational purposes only. Copying this material for any other use is strictly
prohibited.

WARNING – LIFE SUPPORT APPLICATIONS POLICY – SPT products should not be used within Life Support Systems without
the specific written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it
fails, can be reasonably expected to result in significant personal injury or death.

Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device
failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE TYPE

SPT7864SIR –40 to +85 °C 28L SSOP

PIN FUNCTIONS

Name Function

GND Analog ground
V

DD

Analog +5 V
OGND Output ground
OV

DD

Supply voltage for digital outputs +5 V or

+3.3 V
REF

L

Reference pin low, input for external

reference, bypass with capacitor (100 nF)

when internal reference is selected.
REF

H

Reference pin high, input f or external

reference, bypass with capacitor (100 nF)

when internal voltage is selected.
V

CM

2.5 V common mode v oltage ref erence output

V

IN

Non-inverted analog input
V

IN

Inverted analog input
CLK Clock input pin
CLK Complement of clock input pin, internally

biased to 1.5 V; if single-ended clock is used,

bypass to GND with 100 nF
D0–D9 Digital outputs; D0 = LSB; 3.3 V/5 V

compatible
OR Overrange bit; 3.3 V/5 V compatible
EXT/INT EXT/INT = 1, e xternal reference used; internal

reference powered do wn

EXT/INT = 0, internal reference used;

internally pulled down
Sleep Sleep = 1, normal operation; internally pulled

up

Sleep = 0, powered-down mode

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

GND

V

DD

REF

L

REF

H

V

CM

GND

V

DD

V

IN

CLK

D0
D1
D2
D3
D4

OGND

OV

DD

OGND
OV

DD

D5
D6

D7
D8
D9 (MSB)

EXT/INT

V

IN

SPT7864

28L SSOP

CLK

OR

Sleep

PIN ASSIGNMENTS