Datasheet SPT7863SCS, SPT7863SCT Datasheet (SPT)

SPT

SPT7863

SIGNAL PROCESSING TECHNOLOGIES

FEATURES

• Monolithic 40 MSPS Converter

• 160 mW Power Dissipation

• On-Chip Track-and-Hold

• Single +5 V Power Supply

• TTL/CMOS Outputs

• 5 pF Input Capacitance

• Low Cost

• Tri-State Output Buffers

• High ESD Protection: 3,500 V Minimum

• Selectable +3 V or +5 V Logic I/O

GENERAL DESCRIPTION

The SPT7863 is a 10-bit monolithic, low cost, ultralow power
analog-to-digital converter capable of minimum word rates
of 40 MSPS. The on-chip track-and-hold function assures
very good dynamic performance without the need for exter­nal components. The input drive requirements are mini­mized due to the SPT7863's low input capacitance of only
5 pF.

Power dissipation is extremely low at only 160 mW typical at
40 MSPS with a power supply of +5.0 V. The digital outputs

10-BIT, 40 MSPS,160 mW A/D CONVERTER

APPLICATIONS

• All High-Speed Applications Where
Low Power Dissipation is Required

• Video Imaging

• Medical Imaging

• Radar Receivers

• IR Imaging

• Digital Communications

are +3 V or +5 V, and are user selectable. The SPT7863 is
pin-compatible with the entire family of SPT 10-bit, CMOS
converters (SPT7835/40/50/55/60/61) which simplifies up­grades. The SPT7863 has incorporated proprietary circuit
design and CMOS processing technologies to achieve its
advanced performance. Inputs and outputs are TTL/CMOS
compatible to interface with TTL/CMOS logic systems. Out­put data format is straight binary.

The SPT7863 is available in 28-lead SOIC and 32-lead small
(7 mm square) TQFP packages over the commercial tem­perature range.

BLOCK DIAGRAM

A

IN

CLK In

Enable

Data
Valid

Ref

In

Signal Processing Technologies, Inc.

Timing

and

Control

1:16
Mux

P1

P2

.

.

.

P15

P16

ADC Section 1

T/H

ADC Section 2

ADC Section 15

ADC Section 16

T/H

.
.
.

Auto-

Zero

CMP

Auto-

Zero

CMP

Reference Ladder

11-Bit

SAR

DAC

11-Bit

SAR

DAC

11

.
.
.

11

V

REF

4755 Forge Road, Colorado Springs, Colorado 80907, USA

Phone: [phone] FAX: [phone]

11

11

.
.
.

11

11

11-Bit

16:1
Mux/

Error

Correction

D10 Overrange

D9 (MSB)

D8

D7

D6

D5

D4

D3

D2

D1

DØ (LSB)

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C

Supply Voltages

AVDD.........................................................................+6 V

Output

Digital Outputs .......................................................10 mA

DVDD........................................................................+6 V

Temperature

Input Voltages

Analog Input..................................-0.5 V to AVDD +0.5 V

V

............................................................................

REF

0 to AV

CLK Input .................................................................. V

AV

DD

- DV

...............................................................

DD

±100 mV

DD
DD

Operating Temperature ................................. 0 to +70 °C

Junction Temperature ......................................... +175 °C

Lead Temperature, (soldering 10 seconds)........ +300 °C

Storage Temperature................................-65 to +150 °C

AGND - DGND...................................................±100 mV

Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal

applied conditions in typical applications.

ELECTRICAL SPECIFICATIONS

TA=T

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS

Resolution 10 Bits
DC Accuracy

Analog Input

Reference Input

Reference Settling Time

Conversion Characteristics

Dynamic Performance

to T

MAX

Integral Nonlinearity VI ±1.0 LSB
Differential Nonlinearity VI ±0.5 LSB
No Missing Codes VI Guaranteed

Input Voltage Range VI V
Input Resistance IV 50 kΩ
Input Capacitance V 5.0 pF
Input Bandwidth (Small Signal) V 250 MHz
Offset V ±2.0 LSB
Gain Error V ±0.2 %

Resistance VI 300 500 600 Ω
Bandwidth V 100 150 MHz
Voltage Range

V

RLS

V

RHS

V

RHS

∆(V

RHF

∆(V

RLS

V

RHS

V

RLS

Maximum Conversion Rate VI 40 MHz
Minimum Conversion Rate IV 2 MHz
Pipeline Delay (Latency) IV 12
Aperture Delay Time V 4.0 ns
Aperture Jitter Time V 30 ps(p-p)

Effective Number of Bits

fIN=3.58 MHz VI 9.2 Bits
fIN=10 MHz V 8.7 Bits

, AVDD=DVDD=+5.0 V, VIN=0 to 4 V, fS=40 MSPS, V

MAX

TEST TEST SPT7863

IV 0 - 2.0 V
IV 3.0 - AV

- V

RLS

- V

- V

)V90mV

RHS

)V75mV

RLF

V 1.0 4.0 5.0 V

V15Clock Cycles
V20Clock Cycles

RHS

=4.0 V, V

RLS

=0.0 V, unless otherwise specified.

RLS

V

RHS

DD

V

V

Clock Cycles

SPT

SPT7863

2 4/30/98

ELECTRICAL SPECIFICATIONS

TA=T

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS

Dynamic Performance

Spurious Free Dynamic Range f
Differential Phase V ±0.3 Degree
Differential Gain V ±0.3 %

Inputs

Digital Outputs

Power Supply Requirements

to T

MAX

Signal-to-Noise Ratio
(without Harmonics)

fIN=3.58 MHz VI 55 57 dB
fIN=10 MHz V 54 dB

Harmonic Distortion

f

IN

fIN=10 MHz V 62 dB

Signal-to-Noise and Distortion

(SINAD)
f

IN

fIN=10 MHz V 54 dB

Logic 1 Voltage VI 2.0 V
Logic 0 Voltage VI 0.8 V
Maximum Input Current Low VI -10 +10 µA
Maximum Input Current High VI -10 +10 µA
Input Capacitance V +5 pF

Logic 1 Voltage I
Logic 0 Voltage IOL = 1.6 mA VI 0.4 V
t

RISE

t

FALL

Output Enable to Data Output Delay 20 pF load, TA = +25 °C V 10 ns

Voltages OV

Currents AI
Power Dissipation VI 160 210 mW

, AVDD=DVDD=+5.0 V, VIN=0 to 4 V, fS=40 MSPS, V

MAX

TEST TEST SPT7863

=3.58 MHz VI 64 67 dB

=3.58 MHz VI 54 57 dB

=3.580 MHz V 70 dB

IN

= 0.5 mA VI 3.5 V

OH

15 pF load V 10 ns
15 pF load V 10 ns

50 pF load over temp. V 22 ns

IV 3.0 5.0 V
IV 4.75 5.0 5.25 V
IV 4.75 5.0 5.25 V
VI 17 21 mA
VI 16 21 mA

DV
AV

DI

DD
DD

DD
DD
DD

RHS

=4.0 V, V

=0.0 V, unless otherwise specified.

RLS

TEST LEVEL CODES

All electrical characteristics are subject to the
following conditions:

All parameters having min/max specifications
are guaranteed. The Test Level column indi­cates the specific device testing actually per­formed during production and Quality Assur­ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.

SPT

TEST LEVEL

I

II

III
IV

V

VI

3 4/30/98

TEST PROCEDURE

100% production tested at the specified temperature.
100% production tested at TA = +25 °C, and sample

tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design

and characterization data.
Parameter is a typical value for information purposes

only.
100% production tested at TA = +25 °C. Parameter is

guaranteed over specified temperature range.

SPT7863

Figure 1A: Timing Diagram 1

A

A

A

A

A

A

A

A

A

A

A

A

A

ANALOG IN

CLOCK IN

SAMPLING

CLOCK

(Internal)

DATA OUTPUT

DATA VALID

Figure 1B: Timing Diagram 2

CLOCK IN

1

3

5

t

CLK

t

C

t

CH

t

CL

7

INVALID

9

11

13

17

15

VALID

13245

DATA

Data Ø Data 1 Data 2 Data 3

OUTPUT

DATA
VALID

Table I - Timing Parameters

DESCRIPTION PARAMETERS MIN TYP MAX UNITS

Conversion Time t
Clock Period t
Clock High Duty Cycle t
Clock Low Duty Cycle t
Clock to Output Delay (15 pF Load) t
Clock to DAV t

SPT

t

OD

t

S

t

S

C

CLK

CH

CL

OD

S

t

CH

t

CL

t

CLK

25 ns
40 50 60 %
40 50 60 %

17 ns
10 ns

ns

SPT7863

4 4/30/98

TYPICAL INTERFACE CIRCUIT

Very few external components are required to achieve the
stated device performance. Figure 1 shows the typical inter­face requirements when using the SPT7863 in normal circuit
operation. The following sections provide descriptions of the
major functions and outline critical performance criteria to
consider for achieving the optimal device performance.

Figure 1 - Typical Interface Circuit

Ref In
(+4 V)

V

CLK IN

IN

V

V

V

V

V

V

CLK

DAV

AV

RHF

RHS

RLS

RLF

IN

CAL

DD

SPT7863

AGND DGND*

D10

Interfacing

Logics

D0

EN

DV

DD

The high sample rate is achieved by using multiple SAR ADC
sections in parallel, each of which samples the input signal in
sequence. Each ADC uses 16 clock cycles to complete a
conversion. The clock cycles are allocated as follows:

Table II - Clock Cycles

Clock Operation

1 Reference zero sampling
2 Auto-zero comparison
3 Auto-calibrate comparison
4 Input sample
5-15 11-bit SAR conversion
16 Data transfer

The 16 phase clock, which is derived from the input clock,
synchronizes these events. The timing signals for adjacent
ADC sections are shifted by one clock cycle so that the analog
input is sampled on every cycle of the input clock by exactly
one ADC section. After 16 clock periods, the timing cycle
repeats. The latency from analog input sample to the corre­sponding digital output is 12 clock cycles.

FB1

DGND

+5 V

Digital

RTN

10 µF

+D5

+D5

+

+5 V

Digital

FB2

+A5

AGND

+A5

+

10 µF

+5 V

Analog

NOTES: 1)FB3 is to be located as closely to the device as possible.

*To reduce the possibility of latch-up, avoid
connecting the DGND pins of the ADC to the
digital ground of the system.

+5 V

Analog

RTN

2)There should be no additional connections to the right of FB1 and FB2.

3)All capacitors are 0.1 µF surface-mount unless otherwise specified.

4)FB1, FB2 and FB3 are 10 µH inductors or ferrite beads.

FB3

Enable/Tri-State

(Enable = Active Low)

POWER SUPPLIES AND GROUNDING

SPT suggests that both the digital and the analog supply
voltages on the SPT7863 be derived from a single analog
supply as shown in figure 1. A separate digital supply should
be used for all interface circuitry. SPT suggests using this
power supply configuration to prevent a possible latch-up
condition on power up.

OPERATING DESCRIPTION

The general architecture for the CMOS ADC is shown in the
block diagram. The design contains 16 identical successive
approximation ADC sections, all operating in parallel, a 16­phase clock generator, an 11-bit 16:1 digital output multi­plexer, correction logic, and a voltage reference generator
which provides common reference levels for each ADC section.

• Since only 16 comparators are used, a huge power savings
is realized.

• The auto-zero operation is done using a closed loop
system that uses multiple samples of the comparators
response to a reference zero.

• The auto-calibrate operation, which calibrates the gain
of the MSB reference and the LSB reference, is also
done with a closed loop system. Multiple samples of the
gain error are integrated to produce a calibration voltage for
each ADC section.

• Capacitive displacement currents, which can induce sam­pling error, are minimized since only one comparator
samples the input during a clock cycle.

• The total input capacitance is very low since sections of the
converter which are not sampling the signal are isolated
from the input by transmission gates.

VOLTAGE REFERENCE

The SPT7863 requires the use of a single external voltage
reference for driving the high side of the reference ladder. It
must be within the range of 3 V to 5 V. The lower side of the
ladder is typically tied to AGND (0.0 V), but can be run up to

2.0 V with a second reference. The analog input voltage

range will track the total voltage difference measured be­tween the ladder sense lines, V

RHS

and V

RLS

.

Force and sense taps are provided to ensure accurate and
stable setting of the upper and lower ladder sense line
voltages across part-to-part and temperature variations. By
using the configuration shown in figure 2, offset and gain
errors of less than ±2 LSB can be obtained.

SPT

SPT7863

5 4/30/98

Figure 2 - Ladder Force/Sense Circuit

R/2

R

R

R

R

R

R

R/2

R=30 Ω (typ)
All capacitors are 0.01 µF

V

RLF

(AGND)

0.0 V

V

RLS

(0.075 V)

V

RHS

(+3.91 V)

90 mV

75 mV

+4.0 V

External

Reference

1

AGND

Figure 3 - Simplified Reference Ladder Drive Circuit

Without Force/Sense Circuit

+

-

-

+

2

V

RHF

3

V

RHS

4 N/C

5

V

RLS

6

V

RLF

7

V

IN

All capacitors are 0.01 µF

In cases where wider variations in offset and gain can be
tolerated, V
tied directly to V

can be tied directly to V

Ref

as shown in figure 3. Decouple force and

RLF

and AGND can be

RHF

sense lines to AGND with a .01 µF capacitor (chip cap
preferred) to minimize high-frequency noise injection. If this
simplified configuration is used, the following considerations
should be taken into account:

The drive requirements for the analog inputs are very minimal
when compared to most other converters due to the SPT7863's
extremely low input capacitance of only 5 pF and very high
input resistance in excess of 50 kΩ.

The analog input should be protected through a series
resistor and diode clamping circuit as shown in figure 4.

The reference ladder circuit shown in figure 3 is a simplified
representation of the actual reference ladder with force and
sense taps shown. Due to the actual internal structure of the
ladder, the voltage drop from V
to the voltage drop from V

RLF

Typically, the top side voltage drop for V

RHF

to V

to V

RLS

is not equivalent

RHS

.

RHF

equal:

V

- V

RHF

and the bottom side voltage drop for V

V

- V

RLS

= 2.25 % of (V

RHS

= 1.9 % of (V

RLF

RHF

RHF

- V

- V

RLF

) (typical),

RLF

to V

RLS

) (typical).

Figure 3 shows an example of expected voltage drops for a
specific case. Vref of 4.0 V is applied to V
to AGND. A 90 mV drop is seen at V
75 mV increase is seen at V

ANALOG INPUT

VIN is the analog input. The input voltage range is from V
to V
respect to the voltage reference. (See voltage reference
section.)

SPT

(typically 4.0 V) and will scale proportionally with

RHS

(= 0.075 V).

RLS

and V

RHF

(= 3.91 V) and a

RHS

to V

will equal:

RLF

RLF

RHS

is tied

CALIBRATION

The SPT7863 uses an auto calibration scheme to en­sure 10-bit accuracy over time and temperature. Gain and
offset errors are continually adjusted to 10-bit accuracy
during device operation. This process is completely trans-

will

parent to the user.
Upon power-up, the SPT7863 begins its calibration algo-

rithm. In order to achieve the calibration accuracy required,
the offset and gain adjustment step size is a fraction of a 10­bit LSB. Since the calibration algorithm is an oversampling
process, a minimum of 10,000 clock cycles are required.
This results in a minimum calibration time upon power-up
of 250 µsec (for a 40 MHz clock). Once calibrated, the
SPT7863 remains calibrated over time and temperature.

Since the calibration cycles are initiated on the rising edge of
the clock, the clock must be continuously applied for the
SPT7863 to remain in calibration.

RLS

INPUT PROTECTION

All I/O pads are protected with an on-chip protection circuit
shown in figure 5. This circuit provides ESD robustness to

3.5 kV and prevents latch-up under severe discharge condi-

tions without degrading analog transition times.

6 4/30/98

SPT7863

Figure 4 - Recommended Input Protection Circuit

+V

AV

DD

CLOCK INPUT

The SPT7863 is driven from a single-ended TTL-input clock.
Because the pipelined architecture operates on the rising edge of
the clock input, the device can operate over a wide range of input
clock duty cycles without degrading the dynamic performance.

D1

47 Ω

D2

-V

D1 = D2 = Hewlett Packard HP5712 or equivalent

Figure 5 - On-Chip Protection Circuit

V

DD

120 Ω

120 Ω

Pad

DIGITAL OUTPUTS

The digital outputs (D0-D10) are driven by a separate supply

ADCBuffer

(OVDD) ranging from +3 V to +5 V. This feature makes it
possible to drive the SPT7863's TTL/CMOS-compatible out­puts with the user's logic system supply. The format of the
output data (D0-D9) is straight binary. (See table III.) The
outputs are latched on the rising edge of CLK. These outputs
can be switched into a tri-state mode by bringing EN high.

Table III - Output Data Information

ANALOG INPUT OVERRANGE OUTPUT CODE

D10 D9-D0

+F.S. + 1/2 LSB 1 11 1111 1111
+F.S. -1/2 LSB O 11 1111 111Ø
+1/2 F.S. O ØØ ØØØØ ØØØØ
+1/2 LSB O OO OOOO OOOØ

0.0 V O OO OOOO OOOO

Analog

(Ø indicates the flickering bit between logic 0 and 1).

OVERRANGE OUTPUT

The OVERRANGE OUTPUT (D10) is an indication that the
analog input signal has exceeded the positive full scale input
voltage by 1 LSB. When this condition occurs, D10 will switch
to logic 1. All other data outputs (D0 to D9) will remain at
logic 1 as long as D10 remains at logic 1. This feature makes
it possible to include the SPT7863 into higher resolution
systems.

SPT

EVALUATION BOARD

The EB7863 evaluation board is available to aid designers in
demonstrating the full performance of the SPT7863. This
board includes a reference circuit, clock driver circuit, output
data latches and an on-board reconstruction of the digital
data. An application note describing the operation of this
board as well as information on the testing of the SPT7863 is
also available. Contact the factory for price and availability.

SPT7863

7 4/30/98

PACKAGE OUTLINES

28-Lead SOIC

INCHES MILLIMETERS

SYMBOL MIN MAX MIN MAX

28

I H

1

A 0.696 0.712 17.68 18.08
B 0.004 0.012 0.10 0.30
C .050 typ 0.00 1.27
D 0.014 0.019 0.36 0.48
E 0.009 0.012 0.23 0.30
F 0.080 0.100 2.03 2.54
G 0.016 0.050 0.41 1.27
H 0.394 0.419 10.01 10.64

I 0.291 0.299 7.39 7.59

B

CD

C D

E F

A
B

A

F

E

32-Lead TQFP

G H

I

J

H

G

INCHES MILLIMETERS

SYMBOL MIN MAX MIN MAX

A 0.347 0.355 8.90 9.10
B 0.269 0.277 6.90 7.10
C 0.347 0.355 8.90 9.10
D 0.269 0.277 6.90 7.10
E 0.027 0.035 0.68 0.89
F 0.012 0.018 0.30 0.45
G 0.053 0.057 1.35 1.45
H 0.002 0.006 0.05 0.15

I 0.039 typ 1.00 typ
J 0.004 0.008 0.09 0.20
K0° 7° 0° 7°
L 0.018 0.029 0.45 0.75

SPT

K

L

SPT7863

8 4/30/98

PIN ASSIGNMENTS

PIN FUNCTIONS

V

RLF

V

IN

AGND

AGND

V

CAL

AV

DD

AV

DD

DV

D1Ø

27

28

D10

27

D9

26

D8

25

D7

24

D6

23

D5

22

OV

DD

21

OGND

20

D4

19

D3

18

D2

17

D1

16

DØ

15

EN

D8

D9

25

26

24

D7

23

D6

22

D5

21

OV

DD

20

OGND

19

D4

18

D3

17

D2

Name Function

AGND Analog Ground
V
V
V
V
V
V
AV
DV

RHF
RHS
RLS
RLF
CAL
IN

DD
DD

Reference High Force
Reference High Sense
Reference Low Sense
Reference Low Force
Calibration Reference
Analog Input
Analog V
Digital V

DD

DD

DGND Digital Ground
CLK Input Clock f

EN

Output Enable

=fs (TTL)

CLK

D0-9 Tri-State Data Output, (DØ=LSB)
D10 Tri-State Output Overrange
DAV Data Valid Output
OV

DD

Digital Output Supply

OGND Digital Output Ground

1

AGND

2

V

RHF

3

V

RHS

4

N/C

5

V

RLS

6

V

RLF

7

V

IN

AGND

8

V

9

CAL

10

AV

DD

1

DV

DD

1

DGND

12

CLK

13

DAV

14

V

RLS

32

1

2

3

4

5

6

7

DD

8

V

RHS

31

V

RHF

30

SOIC

AGND

29

TQFP

AGND

28

DGND

DV

DD

DGND

CLK

DAV

13

12

10

11

9

16

14

15

D1

EN

DØ

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE TYPE

SPT7863SCS 0 to +70 °C 28L SOIC
SPT7863SCT 0 to +70 °C 32L TQFP

Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby expressly
granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited.

Covered by Patent Numbers 5262779 and 5272481.
WARNING - LIFE SUPPORT APPLICATIONS POLICY - SPT products should not be used within Life Support Systems without the specific

written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably
expected to result in significant personal injury or death.

Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device
failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.

SPT

SPT7863

12 4/30/98