Page 1
SPT7862
10-BIT, 40 MSPS, DUAL-CHANNEL A/D CONVERTER
FEATURES
• Dual-channel, 10-Bit, 40 MSPS analog-to-digital
converter
• Low power dissipation: 320 mW (typical)
• Internal track-and-hold
• Single +5 volt supply
• Tri-state, TTL/CMOS-compatible outputs
• Selectable +3 or +5 V logic I/O
• High ESD protection of 3,500 volts minimum
GENERAL DESCRIPTION
The SPT7862 contains two separate 10-bit CMOS analogto-digital converters that have sampling rates of up to 40
MSPS. Each device has its own separate clock and reference inputs so that they can be used independently in
multichannel applications or can be driven from the same
inputs for demanding quadrature demodulation and S-video
applications. On-chip track-and-hold and advanced proprietary circuit design in a CMOS process technology provide
very good dynamic performance.
BLOCK DIAGRAM
AV
DD
AGND DV
APPLICATIONS
• Video set-top boxes
• Cellular base stations
• QPSK/QAM RF demodulation
• S-video digitizers
• Composite video digitizers
• Portable and handheld instrumentation
• Medical ultrasound
• Cable modems
• Video frame grabbers
The SPT7862 operates from a single +5 V supply. Digital
data outputs are user selectable at +3 or +5 V. Output data
format is straight binary.
The SPT7862 is available in a 64-lead TQFP package
(10 x 10 mm) over the industrial temperature range of
–40 °C to +85 °C.
DGND
DD
OV
(+3.3/5.0 V)
DDA
V
INA
V
INRA
V
RHFA
V
RHSA
V
RLFA
V
RLSA
CLK A
V
INB
V
INRB
V
RHFB
V
RHSB
V
RLFB
V
RLSB
CLK B
ADC
Reference
Ladder
Timing
Generation
ADC
Reference
Ladder
Timing
Generation
Output
Buffers
Output
Buffers
DA9–0
OGND
DAV
A
EN
OV
DDB
DB9–0
OGND
DAV
B
A
(+3.3/5.0 V)
B
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: sales@spt.com
Page 2
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
AVDD.........................................................................+6 V
Output
Digital Outputs .......................................................10 mA
DVDD.........................................................................+6 V
Temperature
Input Voltages
Analog Input................................. –0.5 V to AVDD +0.5 V
V
................................................................. 0 to AV
REF
CLK Input ...................................................................V
AV
– DVDD......................................................±100 mV
DD
DD
DD
Operating Temperature ............................. –40 to +85 °C
Junction Temperature ......................................... +175 °C
Lead Temperature, (soldering 10 seconds)........ +300 °C
Storage Temperature............................... –65 to +150 °C
AGND – DGND ..................................................±100 mV
Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA=T
PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS
Resolution 10 Bits
DC Accuracy
Analog Input
MIN
to T
, AVDD=DVDD=OVDD=+5.0 V, VIN=0 to 4 V, ƒS=40 MSPS, V
MAX
=4.0 V, V
RHS
=0.0 V, unless otherwise specified.
RLS
TEST TEST SPT7862
Integral Nonlinearity V ±1.0 LSB
Differential Nonlinearity V ±0.5 LSB
Input Voltage Range IV V
RLS
V
RHS
V
Input Resistance V 29 kΩ
Input Capacitance V 5.0 pF
Input Bandwidth (Small Signal) V 250 MHz
Offset V ±2.0 LSB
Gain Error V ±2.0 LSB
Reference Input
Resistance V 500 Ω
Voltage Range
IV 0 – 2.0 V
IV 3.0 – AV
DD
V 1.0 4.0 5.0 V
∆(V
∆(V
V
V
V
RHF
RLS
RLS
RHS
RHS
– V
– V
– V
RLS
)V90mV
RHS
)V75mV
RLF
Conversion Characteristics
Maximum Conversion Rate VI 40 MHz
Minimum Conversion Rate IV 2 MHz
Pipeline Delay (Latency) IV 12 Clock Cycles
Aperture Delay Time V 4.0 ns
Aperture Jitter Time V 7 ps(rms)
Dynamic Performance
Effective Number of Bits
= 3.58 MHz V 9.1 Bits
ƒ
IN
= 10.0 MHz VI 7.8 8.3 Bits
ƒ
IN
Signal-to-Noise Ratio
(without Harmonics)
= 3.58 MHz V 57.9 dB
ƒ
IN
ƒ
= 10.0 MHz TA = +25 °C I 52 54.2 dB
IN
ƒ
= 10.0 MHz TA = T
IN
MIN
to T
MAX
IV 47 dB
V
SPT
SPT7862
2 2/23/00
Page 3
ELECTRICAL SPECIFICATIONS
TA=T
MIN
to T
, AVDD=DVDD=OVDD=+5.0 V, VIN=0 to 4 V, ƒS=40 MSPS, V
MAX
=4.0 V, V
RHS
=0.0 V, unless otherwise specified.
RLS
TEST TEST SPT7862
PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS
Dynamic Performance
Harmonic Distortion 9 Distortion bins from
ƒ
= 3.58 MHz 1024 pt FFT V –63 dB
IN
= 10.0 MHz TA = +25 °C I –55.7 –52 dB
ƒ
IN
= 10.0 MHz TA = T
ƒ
IN
MIN
to T
MAX
IV –52 dB
Signal-to-Noise and Distortion
(SINAD)
= 3.58 MHz V 56.7 dB
ƒ
IN
ƒ
= 10.0 MHz TA = +25 °C I 49 51.8 dB
IN
= 10.0 MHz TA = T
ƒ
IN
MIN
to T
MAX
IV 46 dB
Spurious Free Dynamic Range
ƒ
= 10.0 MHz V 56.8 58.3 60 dB
IN
Differential Phase V ±0.3 Degree
Differential Gain V ±0.3 %
Channel-to-Channel Crosstalk
= 3.58 MHz V 74 dB
ƒ
IN
= 10.0 MHz V 67 dB
ƒ
IN
Inputs
Logic 1 Voltage VI 2.1 V
Logic 0 Voltage VI 0.8 V
Maximum Input Current Low VI –10 +10 µA
Maximum Input Current High VI –10 +10 µA
Input Capacitance V +5 pF
Digital Outputs
Logic 1 Voltage IOH = 0.5 mA VI OVDD –0.5 V
Logic 0 Voltage I
t
RISE
t
FALL
= 1.6 mA VI 0.44 V
OL
15 pF load V 10 ns
15 pF load V 10 ns
Output Enable to Data
Output Delay 20 pF load, TA = +25 °C V 10 ns
50 pF load over temp. V 22 ns
Power Supply Requirements
Voltages OV
DV
AV
Currents AI
OI
DD
DD
DD
DD
DD
+ DI
DD
IV 3.0 5.0 V
IV 5.0 V
IV 5.0 V
VI 52 62 mA
VI 12 14 mA
Power Dissipation VI 320 380 mW
Power Supply Refection Ratio V 70 dB
TEST LEVEL CODES
All electrical characteristics are subject to the following conditions:
All parameters having min/max specifications are
guaranteed. The Test Level column indicates the
specific device testing actually performed during
production and Quality Assurance inspection. Any
blank section in the data column indicates that the
specification is not tested at the specified condition.
TEST LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at TA=25 °C, and sample tested at
the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and
characterization data.
Parameter is a typical value for information purposes only.
100% production tested at T
= 25 °C. Parameter is guaran-
A
teed over specified temperature range.
SPT
SPT7862
3 2/23/00
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Figure 1a – Timing Diagram 1
ANALOG IN
CLOCK IN
SAMPLING
CLOCK
(Internal)
1
2
3
4
5
6
7
INVALID
9
8
11
10
12
13
14
15
VALID
17
16
DATA OUTPUT
DATA V ALID
Figure 1b – Timing Diagram 2
t
CLK
t
C
t
CH
t
CL
CLOCK IN
DATA
OUTPUT
DATA VALID
Data Ø
Data 1
t
OD
t
S
t
S
Table I – Timing Parameters
DESCRIPTION PARAMETERS MIN TYP MAX UNITS
Conversion Time t
Clock Period t
Clock High Duty Cycle t
Clock Low Duty Cycle t
Clock to Output Delay
(30 pF Load) t
Clock to DAV (30 pF load) t
C
CLK
CH
CL
OD
S
t
CLK
25 ns
40 50 60 %
40 50 60 %
17 20 ns
10 16 ns
ns
13245
Data 2 Data 3
t
CH
t
CL
SPT
SPT7862
4 2/23/00
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TYPICAL PERFORMANCE CHARACTERISTICS
THD, SNR, SINAD vs Input Frequency
70
65
60
55
50
THD
SNR
SINAD
THD, SNR, SINAD (dB)
45
40
0 5 10 15 20
Input Frequency (MHz)
THD, SNR, SINAD vs Temperature
70
65
ƒIN = 10 MHz
THD, SNR, SINAD vs Sample Rate
70
65
60
55
50
THD, SNR, SINAD (dB)
45
40
1
0
Power Dissipation vs Sample Rate
600
500
ƒIN = 10 MHz
SNR
SINAD
52040
10 30 50
THD
Sample Rate (MSPS)
ƒIN = 10 MHz
60
THD
55
50
SINAD
THD, SNR, SINAD (dB)
45
40
–55 –40 0 25 70 85 125
–25
Temperature (°C)
Spectral Response
Amplitude (dB)
SNR
400
300
200
Power Dissipation (mW)
100
0
0
1
52040
10 30 50
Sample Rate (MSPS)
60
SPT
Frequency (MHz)
SPT7862
5 2/23/00
Page 6
Figure 2 – Typical Interface Circuit
Ref In (+4V)
V
INA
Clock
Ref In (+4V)
V
INB
Clock
INA
INB
V
V
V
V
V
V
CLK
V
V
V
V
V
V
INB
V
INRB
CLK
AV
RHFA
RHSA
RLSA
RLFA
INA
INRA
CAL
RHFB
RHSB
RLSB
RLFB
A
B
DD
SPT7862
AGND
DGND*
OV
DA9–0
OGND
DAV
OV
DB9–0
OGND
DAV
DV
DD
DDA
A
A
DDB
B
B
EN
(Enable = Active Low)
+D5V
+3V/5V
10
Interface
Logic
+3V/5V
10
Interface
Logic
Enable/Tri-State
+A5
+A5
*To reduce the possibility of latch-up, avoid connecting
the DGND pins of the ADC to the digital ground of the system.
NOTES: 1. FB is a 10 µH inductor or ferrite bead. It is
to be located as close to the device as possible.
2. All capacitors are 0.1 µF surface-mount, unless
otherwise specified.
+5V
Analog
+
10 µF
+5V
Analog
Return
TYPICAL INTERFACE CIRCUIT
Very few external components are required to achieve the
stated device performance. Figure 2 shows the typical interface requirements when using the SPT7862 in normal
circuit operation. The following sections provide descriptions of the major functions and outline critical performance
criteria to consider for achieving the optimal device
performance.
POWER SUPPLIES AND GROUNDING
SPT suggests that both the digital and the analog supply
voltages on the SPT7862 be derived from a single analog
supply as shown in figure 2. A separate digital supply should
be used for all interface circuitry. SPT suggests using this
power supply configuration to prevent a possible latch-up
condition on power up.
OPERATING DESCRIPTION
The general architecture for the dual CMOS ADC is shown
in the block diagram. Each ADC design contains 16 identical successive approximation (SAR) ADC sections (all operating in parallel), a 16-phase clock generator, an 11-bit 16:1
digital output multiplexer, correction logic, and a voltage reference generator which provides common reference levels
for each ADC section.
+D5V
FB
+D5
+
10 µF
+5V
Digital
Return
+5V
Digital
The high sample rate is achieved by using multiple SAR
ADC sections in parallel, each of which samples the input
signal in sequence. Each SAR ADC uses 16 clock cycles to
complete a conversion. The clock cycles are allocated as
follows:
Table II – Clock Cycles
Clock Operation
1 Reference zero sampling
2 Auto-zero comparison
3 Auto-calibrate comparison
4 Input sample
5–15 11-bit SAR conversion
16 Data transfer
The 16-phase clock, which is derived from the input clock,
synchronizes these events. The timing signals for adjacent
SAR ADC sections are shifted by one clock cycle so that the
analog input is sampled on every cycle of the input clock by
exactly one SAR ADC section. After 16 clock periods, the
timing cycle repeats. The latency from analog input sample
to the corresponding digital output is 12 clock cycles.
SPT
SPT7862
6 2/23/00
Page 7
• Since only 16 comparators are used, a huge power savings is realized.
• The auto-zero operation is done using a closed loop system that uses multiple samples of the comparator’s
response to a reference zero.
• The auto-calibrate operation, which calibrates the gain
of the MSB reference and the LSB reference, is also
done with a closed loop system. Multiple samples of
the gain error are integrated to produce a calibration voltage for each SAR ADC section.
• Capacitive displacement currents, which can induce sampling error, are minimized since only one comparator
samples the input during a clock cycle.
• The total input capacitance is very low, since sections of
the converter which are not sampling the signal are isolated from the input by transmission gates.
VOLTAGE REFERENCE
The SPT7862 requires the use of a single external voltage
reference for driving the high side of each reference ladder.
Each ladder is totally independent and may operate at different voltage levels. The high side of the reference ladder
must operate within a range of 3 V to 5 V. The lower side of
each ladder is typically tied to AGND (0.0 V), but can be run
up to 2.0 V with a second reference. The analog input voltage range will track the total voltage difference measured
between the ladder sense lines, V
Force and sense taps are provided to ensure accurate and
stable setting of the upper and lower ladder sense line voltages across part-to-part and temperature variations. By
using the configuration shown in figure 3, offset and gain
errors of less than ±2 LSB can be obtained.
RHS
and V
RLS
.
Figure 3 – Ladder Force/Sense Circuit for Each ADC
1
AGND
+
2
V
-
-
+
RHF
3
V
RHS
4 N/C
5
V
RLS
6
V
RLF
7
V
IN
All capacitors are 0.01 µF
Figure 4 – Simplified Reference Ladder Drive Circuit
Without Force/Sense Circuit
+4.0 V
External
Reference
V
RLF
0.0 V
V
RHS
(+3.91 V)
V
RLS
(0.075 V)
(AGND)
90 mV
75 mV
R/2
R
R
R
R
R
R
R/2
R=30 Ω (typ)
All capacitors are 0.01 µF
In cases in which wider variations in offset and gain can be
tolerated, the external reference can be tied directly to V
and AGND can be tied directly to V
as shown in figure 4.
RLF
RHF
Decouple force and sense lines to AGND with a .01 µF capacitor (chip cap preferred) to minimize high-frequency
noise injection. If this simplified configuration is used, the
following considerations should be taken into account:
The reference ladder circuit shown in figure 4 is a simplified
representation of the actual reference ladder with force and
sense taps shown. Due to the actual internal structure of the
ladder, the voltage drop from V
to the voltage drop from V
RLF
RHF
to V
to V
RLS
is not equivalent
RHS
.
SPT
Typically, the top side voltage drop for V
RHF
to V
RHS
will
equal:
V
– V
RHF
and the bottom side voltage drop for V
V
– V
RLS
= 2.25 % of (V
RHS
= 1.9 % of (V
RLF
RHF
RHF
– V
– V
RLF
RLS
) (typical).
RLF
) (typical),
to V
RLF
will equal:
Figure 4 shows an example of expected voltage drops for a
specific case. V
tied to AGND. A 90 mV drop is seen at V
a 75 mV increase is seen at V
of 4.0 V is applied to V
REF
(= 0.075 V).
RLS
and V
RHF
(= 3.91 V) and
RHS
RLF
is
SPT7862
7 2/23/00
Page 8
ANALOG INPUT
V
and V
INA
the respective input returns. Each input return is typically
tied to its respective low side reference ladder sense line.
(See Figure 2.) The input voltage range is from V
(typically 4.0 V) and will scale proportionally with respect to
the voltage reference. (See the Voltage Reference section.)
The drive requirements for the analog inputs are very minimal, when compared to most other converters, due to the
SPT7862’s extremely low input capacitance of only 5 pF
and a high input resistance in excess of 29 kΩ.
Each analog input should be protected through a series
resistor and diode clamping circuit as shown in figure 5.
are the analog inputs and V
INB
INRA
and V
RLS
INRB
to V
are
RHS
Figure 6 – On-Chip Protection Circuit
V
DD
120 Ω
120 Ω
Pad
Analog
Figure 5 – Recommended Input Protection Circuit
+V
D1
47 Ω
D2
–V
D1 = D2 = Hewlett Packard HP5712 or equivalent
AV
ADCBuffer
DD
CALIBRATION
The SPT7862 uses a user-transparent, auto-calibration
scheme to ensure 10-bit accuracy over time and temperature. Gain and offset errors are continually adjusted to 10-bit
accuracy during device operation.
Upon power up, the SPT7862 begins its calibration algorithm. In order to achieve the calibration accuracy required,
the offset and gain adjustment step size is a fraction of a 10bit LSB. Since the calibration algorithm is an oversampling
process, a minimum of 10,000 clock cycles are required.
This results in a minimum calibration time upon power up of
250 µsec (for a 40 MHz clock). Once calibrated, the
SPT7862 remains calibrated over time and temperature.
Since the calibration cycles are initiated on the rising edge
of the clock, the clock must be continuously applied for the
SPT7862 to remain in calibration.
INPUT PROTECTION
All I/O pads are protected with an on-chip protection circuit
shown in figure 6. This circuit provides ESD robustness and
prevents latch-up under severe discharge conditions without degrading analog transition times.
CLOCK INPUT
Each ADC is driven independently from a single-ended
TTL-input clock. Because the pipelined architecture operates on the rising edge of the clock input, each ADC can
operate over a wide range of input clock duty cycles without
degrading the dynamic performance.
DIGITAL OUTPUTS
The digital outputs (DA9–0 and DB9–0) are driven by separate supplies (OV
and OV
DDA
) ranging from +3 V to
DDB
+5 V. This feature makes it possible to drive the SPT7862’s
TTL/CMOS-compatible outputs with the user’s logic system
supply. Each digital output supply may be driven independently. The format of the output data (D0–D9) is straight
binary. (See Table III.) The outputs are latched on the rising
edge of CLK. The EN pin controls tri-stating of both data
output ports. These outputs can be switched into a tri-state
mode by bringing EN high.
Table III – Output Data Information
ANALOG INPUT OVERRANGE OUTPUT CODE
+F.S. + 1/2 LSB 1 11 1111 1111
+F.S. –1/2 LSB 0 11 1111 111Ø
+1/2 F.S. 0 ØØ ØØØØ ØØØØ
+1/2 LSB 0 0 0 0000 000Ø
0.0 V 0 00 0000 0000
D10 D9–D0
(Ø indicates the flickering bit between logic 0 and 1)
EVALUATION BOARD
The EB7862 evaluation board is available to aid designers
in demonstrating the full performance of the SPT7862.
This board includes a reference circuit, clock driver circuit,
output data latches and an on-board reconstruction of the
digital data. An application note describing the operation of
this board as well as information on the testing of the
SPT7862 is also available. Contact the factory for price and
availability.
SPT
SPT7862
8 2/23/00
Page 9
PACKAGE OUTLINE
64-Lead TQFP
A
64 49
B
G
SYMBOL MIN MAX MIN MAX
INCHES MILLIMETERS
A 0.465 0.480 11.80 12.20
B 0.390 0.398 9.90 10.10
1
Index
48
C 0.017 0.023 0.42 0.58
D 0.006 0.010 0.15 0.26
E 0.295 typ 7.5 typ
F 0.433 typ 0.000 11 typ
E F
G 0.055 0.067 1.40 1.70
H 0.005 0.005 0.125 0.132
I 0-10° 0-10°
J 0.012 0.028 0.30 0.70
16
C D
K
3217
33
H
K 0.000 0.008 0.00 0.20
J
I
SPT
SPT7862
9 2/23/00
Page 10
PIN ASSIGNMENTS PIN FUNCTIONS
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
AGND
AGND
V
RHFA
V
RHFB
V
RHSA
V
RHSB
V
INRA
DB0
DDB
N/C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
INRBVRLSAVRLSBVRLFAVRLFB
OV
OGND
B
EN
DGND
CLKB
DAV
N/C
B
SPT7862
TOP VIEW
64L TQFP
N/C
AGND
V
AGND
INB
CLKA
V
INA
DV
DD
AGND
OGND
OV
DAV
A
A
DA0
N/C
DDA
49505152535455565758596061626364
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
3029282726252423222120191817
31
32
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
AGND
AGND
AV
AV
N/C
AGND
AGND
Pin Name Description
V
INA
V
INB
V
INRA
V
INRB
V
RHFA/B
V
RHSA/B
V
RLFA/B
V
RLSA/B
AV
DD
DV
DD
OVDD A/B Digital Output Power Supply +3.3 V to +5.0 V
DD
DD
AGND Analog Ground
Analog Input (A)
Analog Input (B)
Analog Input Return (A)
Analog Input Return (B)
V
High Force Input A/B
REF
V
High Sense Input A/B
REF
V
Low Force Input A/B
REF
V
Low Sense Input A/B
REF
Analog V
Digital V
DD
DD
DGND Digital Ground
OGND A/B Digital Output Ground
CLK A/B Input Clock A/B (separate)
V
CAL
N/C
AGND
AGND
N/C
EN Enable Outputs (Active Low)
D0–9A Data Outputs A (10 bits)
D0–9B Data Outputs B (10 bits)
DAV A/B Data Available A/B
V
CAL
Decoupling Pin
ORDERING INFORMATION
PART NUMBER TEMPERATURE RANGE PACKAGE TYPE
SPT7862SIT –40 to +85 °C 64-Lead TQFP
Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby expressly
granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited.
Covered by Patent Numbers 5262779 and 5272481.
WARNING – LIFE SUPPORT APPLICATIONS POLICY – SPT products should not be used within Life Support Systems without the specific
written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably
expected to result in significant personal injury or death.
Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device
failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.
SPT7862
SPT
10 2/23/00
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