Page 1
SPT7824
10-BIT, 40 MSPS, TTL OUTPUT A/D CONVERTER
FEATURES
• Monolithic 40 MSPS Converter
• On-Chip Track/Hold
• Bipolar ±2.0 V Analog Input
• 57 dB SNR @ 3.58 MHz Input
• Low Power (1.0 W Typical)
• 5 pF Input Capacitance
• TTL Outputs
GENERAL DESCRIPTION
The SPT7824 A/D converter is a 10-bit monolithic converter
capable of word rates a minimum of 40 MSPS. On board
track/hold function assures excellent dynamic performance
without the need for external components. Drive requirement problems are minimized with an input capacitance of
only 5 pF.
Inputs and outputs are TTL compatible to interface with TTL
logic systems. An overrange output signal is provided to
BLOCK DIAGRAM
APPLICATIONS
• Medical Imaging
• Professional Video
• Radar Receivers
• Instrumentation
• Electronic Warfare
• Digital Communications
indicate overflow conditions. Output data format is straight
binary. Power dissipation is very low at only 1.0 watt with
power supply voltages of +5.0 and -5.2 volts. The SPT7824
also provides a wide input voltage swing of ±2.0 volts.
The SPT7824 is available in 28-lead ceramic sidebrazed DIP,
PDIP and SOIC packages over the commercial, industrial and
military temperature ranges. Consult the factory for availability of die and /833 versions.
Analog
Input
Coarse
A/D
Analog
Prescaler
T/H Amplifier
Bank
Successive Interpolation
Stage i
Successive Interpolation
Stage i+1
Successive Interpolation
Stage N
4
Digital
10
Decoding Network
Output
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: (719) 528-2300 FAX: (719) 528-2370
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ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
VCC...........................................................................+6 V
Output
Digital Outputs .......................................... +30 to -30 mA
VEE........................................................................... -6 V
Temperature
Input Voltages
Analog Input............................................... VFB≤VIN≤V
VFT, V
..............................................................
FB
+3.0 V, -3.0 V
Reference Ladder Current .....................................12 mA
CLK Input.................................................................. V
FT
CC
Operating Temperature ............................-55 to +125 °C
1
Junction Temperature
..............................................
+175 °C
Lead Temperature, (soldering 10 seconds)........ +300 °C
Storage Temperature................................-65 to +150 °C
Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA=T
specified.
PARAMETERS CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX UNITS
Resolution 10 10 Bits
DC Accuracy (+25 °C)
- T
MIN
Integral Nonlinearity 100 kHz Sample Rate V ±1.0 ±1.5 LSB
Differential Nonlinearity V ±0.5 ±0.75 LSB
No Missing Codes VI Guaranteed Guaranteed
, VCC=+5.0 V, VEE=-5.2 V, DVCC=+5.0 V, VIN=±2.0 V, VSB=-2.0 V, VST=+2.0 V, f
MAX
TEST TEST SPT7824A SPT7824B
±
Full Scale
=40 MHz, 50% clock duty cycle, unless otherwise
CLK
Analog Input f
Input Voltage Range V ±2.0 ±2.0 V
Input Bias Current V
Input Bias Current T
Input Resistance VI 100 300 100 300 kΩ
Input Resistance T
Input Capacitance V 5 5 pF
Input Bandwidth 3 dB Small Signal V 120 120 MHz
+FS Error V ±2.0 ±2.0 LSB
-FS Error V ±2.0 ±2.0 LSB
Reference Input f
Reference Ladder Resistance VI 500 800 500 800 Ω
Reference Ladder Tempco V 0.8 0.8 Ω/°C
Timing Characteristics
Maximum Conversion Rate VI 40 40 MHz
Overvoltage Recovery Time V 20 20 ns
Pipeline Delay (Latency) IV 1 1
Output Delay TA=+25 °C V 14 18 14 18 ns
Aperture Delay Time T
Aperture Jitter Time T
Acquisition Time TA=+25 °C V 12 12 ns
Dynamic Performance
Effective Number of Bits
=1 MHz 8.7 8.2 Bits
f
IN
=3.58 MHz 8.7 8.2 Bits
f
IN
fIN=10.0 MHz 7.3 6.9 Bits
=1 MHz
CLK
=0 V VI 30 60 30 60 µA
IN
=-55 to +125 °CIV 75 75µA
A
=-55 to +125 °C IV 75 300 75 300 kΩ
A
=1 MHz
CLK
=+25 °CV1 1ns
A
=+25 °C V 5 5 ps-RMS
A
Clock Cycle
Typical thermal impedances (unsoldered, in free air): 28L sidebrazed DIP: θja = 50 °C/W, 28L plastic DIP: θja = 50°C/W,
28L SOIC: θ
SPT
= 100 °C/W.
ja
2 3/11/97
SPT7824
Page 3
ELECTRICAL SPECIFICATIONS
TA=T
MIN-TMAX
PARAMETERS CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX UNITS
Dynamic Performance
Signal-To-Noise Ratio
(without Harmonics)
Harmonic Distortion
Signal-to-Noise and Distortion
Spurious Free Dynamic Range T
Differential Phase
Differential Gain T
Digital Inputs f
Logic 1 Voltage VI 2.4 4.5 2.4 4.5 V
Logic 0 Voltage VI 0.8 0.8 V
Maximum Input Current Low T
Maximum Input Current High T
Pulse Width Low (CLK) IV 10 10 ns
Pulse Width High (CLK) IV 10 300 10 300 ns
Digital Outputs f
Logic "1" Voltage VI 2.4 2.4 V
Logic "0" Voltage VI 0.6 0.6 V
Power Supply Requirements
VoltagesV
CurrentsI
Power Dissipation T
Power Supply Rejection +5 V ±0.25 V, -5.2 V ±0.25 V V 1.0 1.0 LSB
*Temperature tested /883 only.
, VCC=+5.0 V, VEE=-5.2 V, DVCC=+5.0 V, VIN=±2.0 V, VSB=-2.0 V, VST=+2.0 V, f
=40 MHz, 50% clock duty cycle unless otherwise specified.
CLK
TEST TEST SPT7824A SPT7824B
f
=1 MHz TA=+25 °C I 55 57 52 54 dB
IN
f
=3.58 MHz TA=+25 °C I 55 57 52 54 dB
IN
=10.0 MHz TA=+25 °C I 48 50 46 48 dB
f
IN
=1 MHz TA=+25 °C I 54 56 52 54 dB
f
IN
f
=3.58 MHz TA=+25 °C I 54 56 52 54 dB
IN
=10.0 MHz TA=+25 °C I 46 48 43 45 dB
f
IN
=1 MHz TA=+25 °C I 52 54 49 51 dB
f
IN
f
=3.58 MHz TA=+25 °C I 52 54 49 51 dB
IN
f
=10.0 MHz TA=+25 °C I 44 46 41 43 dB
IN
CC
DV
CC
-V
EE
CC
DI
CC
-I
EE
=0 to +70, -25 to +85 °CIV 5355 5052 dB
T
A
T
=-55 to +125 °C* IV 49 51 46 48 dB
A
=0 to 70, -25 to +85 °CIV 5355 5052 dB
T
A
T
=-55 to +125 °C* IV 49 51 46 48 dB
A
T
=0 to 70, -25 to +85 °CIV 4547 4345 dB
A
T
=-55 to +125 °C* IV 41 43 39 41 dB
A
=0 to 70, -25 to +85 °CIV 5153 4951 dB
T
A
T
=-55 to +125 °C* IV 50 52 48 50 dB
A
=0 to 70, -25 to +85 °CIV 5153 4951 dB
T
A
T
=-55 to +125 °C* IV 50 52 48 50 dB
A
T
=0 to 70, -25 to +85 °CIV 4547 4144 dB
A
T
=-55 to +125 °C* IV 44 46 40 42 dB
A
=0 to 70, -25 to +85 °CIV 49 46 dB
T
A
T
=-55 to +125 °C* IV 48 45 dB
A
=0 to 70, -25 to +85 °CIV 49 46 dB
T
A
T
=-55 to +125 °C* IV 48 45 dB
A
=0 to 70, -25 to +85 °CIV 43 40 dB
T
A
T
=-55 to +125 °C* IV 40 37 dB
A
=+25 °C, fIN=1 MHz V 67 67 dB
A
TA=+25 °C, fIN = 3.58 & 4.35 MHz V 0.2 0.2 Degree
=+25 °C, fIN = 3.58 & 4.35 MHz V 0.5 0.7 %
A
=1 MHz
CLK
=+25 °C I 0 +5 +20 0 +5 +20 µA
A
=+25 °C I 0 +5 +20 0 +5 +20 µA
A
=1 MHz
CLK
IV 4.75 5.25 4.75 5.25 V
IV 4.75 5.0 5.25 4.75 5.0 5.25 V
IV -4.95 -5.2 -5.45 -4.95 -5.2 -5.45 V
TA=+25 °C I 118 145 118 145 mA
TA=+25 °C I 40 55 40 55 mA
TA=+25 °C I 40 57 40 57 mA
=+25 °C I 1.0 1.3 1.0 1.3 W
A
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TEST LEVEL CODES
TEST LEVEL
TEST PROCEDURE
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
Figure 1A - Timing Diagram
N
t
pwH
II
III
IV
V
VI
t
pwL
I
100% production tested at the specified temperature.
100% production tested at TA = +25 °C, and sample
tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
Parameter is a typical value for information purposes
only.
100% production tested at TA = +25 °C. Parameter is
guaranteed over specified temperature range.
N+1
N+2
CLK
Output
Data
Figure 1B - Single Event Clock
CLK
Output
Data
Table I - Timing Parameters
PARAMETERS DESCRIPTION MIN TYP MAX UNITS
t
d
t
pwH
t
d
N-2 N-1
t
d
Data Valid
N
Data Valid
N+1
Data Valid
CLK to Data Valid Prop Delay - 14 18 ns
CLK High Pulse Width 10 - 300 ns
SPT
t
pwL
CLK Low Pulse Width 10 - - ns
SPT7824
4 3/11/97
Page 5
TYPICAL PERFORMANCE CHARACTERISTICS
20
30
40
50
60
70
80
10
0
10
1
10
2
SNR, THD, SINAD vs Sample Rate
Sample Rate (MSPS)
SNR, THD, SINAD (dB)
THD
SINAD
f
IN
= 1 MHz
SNR
80
70
60
50
40
30
Total Harmonic Distortion (dB)
20
80
70
60
THD vs Input Frequency
80
70
fs = 40 MSPS
0
10
Input Frequency (MHz)
1
10
2
10
60
50
40
Signal-to-Noise Ratio (dB)
30
20
0
10
SNR vs Input Frequency
fs = 40 MSPS
1
10
Input Frequency (MHz)
2
10
SINAD vs Input Frequency
fs =40 MSPS
Signal-to-Noise and Distortion (dB)
Amplitude (dB)
-120
SPT
50
40
30
20
0
10
Input Frequency (MHz)
1
10
Spectral Response
0
-30
-60
-90
f
= 40 MSPS
S
fIN = 1 MHz
0 12345678910
Input Frequency (MHz)
2
10
SNR, THD, SINAD vs Temperature
65
60
SNR
55
THD
SINAD
50
= 40 MSPS
SNR, THD, SINAD (dB)
45
40
-25 0 +25 +50 +75
f
S
= 1 MHz
f
IN
Temperature (°C)
SPT7824
5 3/11/97
Page 6
TYPICAL INTERFACE CIRCUIT
The SPT7824 requires few external components to achieve
the stated operation and performance. Figure 2 shows the
typical interface requirements when using the SPT7824 in
normal circuit operation. The following section provides a
description of the pin functions and outlines critical performance criteria to consider for achieving the optimal device
performance.
POWER SUPPLIES AND GROUNDING
The SPT7824 requires -5.2 V and +5 V analog supply
voltages. The +5 V supply is common to analog VCC and
digital DVCC. A ferrite bead in series with each supply line is
intended to reduce the transient noise injected into the analog
VCC. These beads should be connected as closely as possible to the device. The connection between the beads and
the SPT7824 should not be shared with any other device.
Each power supply pin should be bypassed as closely as
possible to the device. Use 0.1 µF for VEE and VCC, and
0.01 µ F for DVCC (chip caps are preferred).
Figure 2 - Typical Interface Circuit
AGND and DGND are the two grounds available on the
SPT7824. These two internal grounds are isolated on the
device. The use of ground planes is recommended to achieve
optimum device performance. DGND is needed for the DV
CC
return path (40 mA typical) and for the return path for all digital
output logic interfaces. AGND and DGND should be separated from each other and connected together only at the
device through a ferrite bead.
A Schottky or hot carrier diode connected between AGND
and VEE is required. The use of separate power supplies
between VCC and DVCC is not recommended due to potential
power supply sequencing latch-up conditions. Using the
recommended interface circuit shown in figure 2 will provide
optimum device performance for the SPT7824.
V
OUT
Tri m
-
6
R1
100 Ω
± 2.5 V Max
6
5
- 5.2 V
4
.01 µF
10 kΩ
30 kΩ
1 µF
1 µF
30 kΩ
C1
+
.01 µF
+
CLK
(TTL)
V
(±2 V)
+ 5 V
+5 V
IN
2
V
IC1
IN
+
C19
1 µF
(REF-03)
4
GND
32
1
+
IC2
10 kΩ
OP-07
8
7
.01 µF
Notes to prevent latch-up due to power sequencing:
1) D1 = Schottky or hot carrier diode, P/N IN5817.
2) FB = Ferrite bead, Fair Rite P/N 2743001111
to be mounted as close to the device as possible. The f errite bead to the
ADC connection should not be shared with any other device.
3) C1-C11 = Chip cap (recommended) mounted as close to the device's pin
as possible.
4) Use of a separate supply for VCC and DVCC is not recommended.
5) R1 provides current limiting to 45 mA.
6) C6, C7, C8 and C9 should be ten times larger than C10 and C11.
7) C8 = C9 = a 0.1 µF cap in parallel with a 4.7 µF cap.
+2.5 V
-2.5 V
.01 µF
.01 µF
.01 µF
C5
.01 µF
CLK
V
IN
V
FT
C2
C3
C4
R
V
ST
2R
2R
V
RM
2R
2R
V
SB
R
V
FB
EE
EE
V
V
C6
.1 µF
C7
.1 µF
D1
10 µF
+
-5.2 V
(Analog)
AGND
10 µF
AGND
COARSE
A/D
ANALOG
PRESCALER
SUCCESSIVE
INTERPOLATION
STA GE # 1
SUCCESSIVE
INTERPOLATION
STA GE # N
CC
AGND
V
C8
C9
FB
+
(Analog)
V
+5 V
4
D E C O D I N G N E T W O R K
CC
CC
CC
.01 µF
.01 µF
DGND
DV
C10
C11
DGND
DV
FB
DGND
FB
D10 (Overrange)
D9 (MSB)
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
D I G I T A L O U T P U T S
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VOLTAGE REFERENCE
The SPT7824 requires the use of two voltage references:
VFT and VFB. VFT is the force for the top of the voltage
reference ladder (+2.5 V typ), VFB (-2.5 V typ) is the force for
the bottom of the voltage reference ladder. Both voltages are
applied across an internal reference ladder resistance of
800 ohms. The +2.5 V voltage source for reference VFT must
be current limited to 20 mA maximum if a different driving
circuit is used in place of the recommended reference circuit
shown in figures 2 and 3. In addition, there are three
reference ladder taps (VST, VRM and VSB). VST is the sense for
the top of the reference ladder (+2.0 V), VRM is the midpoint
of the ladder (0.0 V typ) and VSB is the sense for the bottom
of the reference ladder (-2.0 V). The voltages seen at VST and
VSB are the true full scale input voltages of the device when
VFT and VFB are driven to the recommended voltages (+2.5 V
and -2.5 V typical respectively). These points should be used
to monitor the actual full scale input voltage of the device and
should not be driven to the expected ideal values as is
commonly done with standard flash converters. When not
being used, a decoupling capacitor of .01 uF (chip carrier
preferred) connected to AGND from each tap is recommended
to minimize high frequency noise injection.
Figure 3 - Analog Equivalent Input Circuit
V
CC
V
IN
V
FT
ever, because the device is laser trimmed to optimize performance with ± 2.5 V references, the accuracy of the device will
degrade if operated beyond a ± 2% range.
The following errors are defined:
+FS error = top of ladder offset voltage = ∆(+FS -VST+1 LSB)
-FS error = bottom of ladder offset voltage = ∆(-FS -V
SB
-1 LSB)
where the +FS (full scale) input voltage is defined as the
output transition between 1-10 and 1-11 and the -FS input
voltage is defined as the output transition between 0-00 and
0-01.
ANALOG INPUT
VIN is the analog input. The full scale input range will be 80% of
the reference voltage or ±2 V with VFB=-2.5 V and VFT=+2.5 V.
The drive requirements for the analog inputs are minimal
when compared to conventional Flash converters due to the
SPT7824’s extremely low input capacitance of only 5 pF and
very high input resistance of 300 kΩ. For example, for an input
signal of ± 2 V p-p with an input frequency of 10 MHz, the peak
output current required for the driving circuit is only 628 µA.
CLOCK INPUT
The SPT7824 is driven from a single-ended TTL input (CLK).
The CLK pulse width (tpwH) must be kept between 10 ns and
300 ns to ensure proper operation of the internal track-andhold amplifier. (See timing diagram.) When operating the
SPT7824 at sampling rates above 3 MSPS, it is recommended that the clock input duty cycle be kept at 50% to
optimize performance. (See figure 4.) The analog input
signal is latched on the rising edge of the CLK.
Analog Prescaler
V
EE
An example of a reference driver circuit recommended is
shown in figure 2. IC1 is REF-03, the +2.5 V reference with a
tolerance of 0.6% or +/- 0.015 V. The potentiometer R1 is
10 kΩ and supports a minimum adjustable range of up to
150 mV. IC2 is recommended to be an OP-07 or equivalent
device. R2 and R3 must be matched to within 0.1% with good
TC tracking to maintain a 0.3 LSB matching between VFT and
VFB. If 0.1% matching is not met, then potentiometer R4 can
be used to adjust the VFB voltage to the desired level. VFT and
VFB should be adjusted such that VST and VSB are exactly
+2.0 V and -2.0 V respectively.
The analog input range will scale proportionally with respect
to the reference voltage if a different input range is required.
The maximum scaling factor for device operation is ± 20% of
the recommended reference voltages of VFT and VFB. How-
The clock input must be driven from fast TTL logic (VIH ≤4.5 V,
T
<6 ns). In the event the clock is driven from a high
RISE
current source, use a 100 Ω resistor in series to current limit
to approximately 45 mA.
Figure 4 - SNR vs Clock Duty Cycle
59
57
55
53
Duty
51
49
47
Signal-to-Noise Ratio (dB)
45
43
30 35 40 45 50 55 60 65 70 75
Duty Cycle of Positive Clock Pulse (%)
Cycle
=
tpwLtpwH
tpwH
tpwL
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SPT7824
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Page 8
DIGITAL OUTPUTS
OVERRANGE OUTPUT
The format of the output data (D0-D9) is straight binary. (See
table II.) The outputs are latched on the rising edge of CLK
with a propagation delay of 14 ns (typ). There is a one clock
cycle latency between CLK and the valid output data. (See
timing diagram.)
Table II - Output Data Information
ANALOG INPUT OVERRANGE OUTPUT CODE
D1O D9-DO
>+2.0 V + 1/2 LSB 1 11 1111 1111
+2.0 V -1 LSB O 11 1111 111Ø
0.0 V O ØØ ØØØØ ØØØØ
-2.0 V +1 LSB O OO OOOO OOOØ
<-2.0 V O OO OOOO OOOO
(Ø indicates the flickering bit between logic 0 and 1).
The rise times and fall times of the digital outputs are not
symmetrical. The propagation delay of the rise time is typically 14 ns and the fall time is typically 6 ns. (See figure 5.)
The nonsymmetrical rise and fall times create approximately
8 ns of invalid data.
The OVERRANGE OUTPUT (D10) is an indication that the
analog input signal has exceeded the positive full scale input
voltage by 1 LSB. When this condition occurs, D10 will switch
to logic 1. All other data outputs (D0 to D9) will remain at
logic 1 as long as D10 remains at logic 1. This feature makes
it possible to include the SPT7824 into higher resolution
systems.
EVALUATION BOARD
The EB7824 Evaluation Board is available to aid designers in
demonstrating the full performance of the SPT7824. This
board includes a reference circuit, clock driver circuit, output
data latches and an on-board reconstruction of the digital
data. An application note describing the operation of this
board as well as information on the testing of the SPT7824 is
also available. Contact the factory for price and availability.
Figure 5 - Digital Output Characteristics
N
CLK In
Data Out
(Actual)
Data Out
2.4 V
3.5 V
2.4 V
0.8 V
0.5 V
6 ns
typ.
(N-2)
tpd1
(14 ns typ.)
(N-2)
Invalid
Invalid
(Equivalent)
Data
Data
(N-1)
(N-1)
N+1
Rise Time
≤ 6 nsec
Invalid
Data
Invalid
Data
(N)
(N-1)
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SPT7824
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Page 9
PACKAGE OUTLINES
INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX
A 0.200 5.08
B 0.120 0.135 3.05 3.43
C 0.020 0.51
D 0.100 2.54
E 0.067 1.70
F 0.013 0.33
G 0.170 0.180 4.32 4.57
H 0.622 15.80
I 0.555 14.10
J 1.460 37.08
K 0.085 2.16
28-Lead Sidebrazed
28
H
SYMBOL MIN MAX MIN MAX
I
1
J
G
A
INCHES MILLIMETERS
A 0.077 0.093 1.96 2.36
B 0.016 0.020 0.41 0.51
C 0.095 0.105 2.41 2.67
D .050 typ 0.00 1.27
E 0.040 0.060 1.02 1.52
F 0.215 0.235 5.46 5.97
G 1.388 1.412 35.26 35.86
H 0.585 0.605 14.86 15.37
I 0.009 0.012 0.23 0.30
J 0.600 0.620 15.24 15.75
E
F
C
B
D
28-Lead Plastic DIP
28
1
J
A
B
C
SPT
K
I
H
G
F
D
E
SPT7824
9 3/11/97
Page 10
B
28
1
CD
A
PACKAGE OUTLINES
28-Lead SOIC
SYMBOL MIN MAX MIN MAX
I H
F
E
INCHES MILLIMETERS
A 0.696 0.712 17.68 18.08
B 0.004 0.012 0.10 0.30
C .050 typ 0.00 1.27
D 0.014 0.019 0.36 0.48
E 0.009 0.012 0.23 0.30
F 0.080 0.100 2.03 2.54
G 0.016 0.050 0.41 1.27
H 0.394 0.419 10.01 10.64
I 0.291 0.299 7.39 7.59
G
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PIN ASSIGNMENTS
PIN FUNCTIONS
DGND
Name Function
1
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
DIP/PDIP/SOIC
D6
8
D7
9
D8
D9
D10
DGND
DV
CC
10
11
12
13
14
28
DV
CC
V
27
EE
AGND
26
V
25
CC
V
24
FB
V
23
SB
V
22
RM
V
21
IN
20
V
ST
19
V
FT
18
V
CC
17
AGND
V
16
EE
CLK
15
DGND Digital Ground
D0-D9 TTL Outputs (D0=LSB)
D10 TTL Output Overrange
CLK Clock
V
EE
-5.2 V Supply (Analog)
AGND Analog Ground
V
V
DV
V
V
V
V
V
CC
IN
CC
RM
FT
ST
FB
SB
+5.0 V Supply (Analog)
Analog Input
Digital +5.0 V Supply
Middle of Voltage Reference Ladder
Force for Top of Reference Ladder
Sense for Top of Reference Ladder
Force for Bottom of Reference Ladder
Sense for Bottom of Reference Ladder
ORDERING INFORMATION
PART NUMBER TEMPERATURE RANGE PACKAGE TYPE
SPT7824AIJ -25 to +85 °C 28L Sidebrazed DIP
SPT7824BIJ -25 to +85 °C 28L Sidebrazed DIP
SPT7824ACN 0 to +70 °C 28L Plastic DIP
SPT7824BCN 0 to +70 °C 28L Plastic DIP
SPT7824ACS 0 to +70 °C 28L SOIC
SPT7824BCS 0 to +70 °C 28L SOIC
SPT7824AMJ -55 to +125 °C 28L Sidebrazed DIP
SPT7824BMJ -55 to +125 °C 28L Sidebrazed DIP
Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby expressly
granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited.
WARNING - LIFE SUPPORT APPLICATIONS POLICY - SPT products should not be used within Life Support Systems without the specific
written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably
expected to result in significant personal injury or death.
Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device
failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.
SPT
SPT7824
11 3/11/97
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