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SPT7810
10-BIT, 20 MSPS, ECL OUTPUT A/D CONVERTER
FEATURES
• Monolithic 20 MSPS Converter
• On-Chip Track/Hold
• Bipolar ±2.0 V Analog Input
• 60 dB SNR @ 1 MHz Input
• Low Power (1.3 W Typical)
• 5 pF input Capacitance
• ECL Outputs
GENERAL DESCRIPTION
The SPT7810 A/D converter is a 10-bit monolithic converter
capable of word rates of a minimum of 20 MSPS. On board
track/hold function assures excellent dynamic performance
without the need for external components. Drive requirement problems are minimized with an input capacitance of
only 5 pF.
Inputs and outputs are ECL to provide a higher level of noise
immunity in high speed system applications. An overrange
output signal is provided to indicate overflow conditions.
BLOCK DIAGRAM
APPLICATIONS
• Medical Imaging
• Professional Video
• Radar Receivers
• Instrumentation
• Electronic Warfare
• Digital Communications
Output data format is straight binary. Power dissipation is
very low at only 1.3 watts with power supply voltages of +5.0
and -5.2 volts. The SPT7810 also provides a wide input
voltage swing of ±2.0 volts.
The SPT7810 is available in a 28-lead ceramic sidebrazed
DIP, PDIP, and die form. Commercial and industrial temperature ranges are currently offered. Contact the factory for
availability of military temperature range and /883 processed
units.
Analog
Input
Coarse
A/D
Analog
Prescaler
T/H Amplifier
Bank
Successive Interpolation
Stage i
Successive Interpolation
Stage i+1
Successive Interpolation
Stage N
4
10
Decoding Network
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: (719) 528-2300 FAX: (719) 528-2370
Digital
Output
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ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
VCC............................................................... -0.3 to +6 V
Output
Digital Outputs .......................................... +30 to -30 mA
VEE............................................................... +0.3 to -6 V
Temperature
Input Voltages
Analog Input............................................... VFB≤VIN≤V
VFT, VFB. ................................................... +3.0 V, -3.0 V
Reference Ladder Current .....................................12 mA
FT
Operating Temperature ..............................-25 to +85 °C
(1)
Junction Temperature
..............................................
175 °C
Lead Temperature, (soldering 10 seconds).......... 300 °C
Storage Temperature................................-65 to +150 °C
Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA=T
PARAMETERS CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX UNITS
Resolution 10 10 Bits
DC Accuracy (+25 °C) ± Full Scale
- T
min
Integral Nonlinearity 250 kHz Sample Rate V ±1.0 ±1.5 LSB
Differential Nonlinearity V ±0.5 ±0.75 LSB
No Missing Codes VI Guaranteed Guaranteed
, VCC=+5.0 V, VEE=-5.2 V, VIN=±2.0 V, VSB=-2.0 V, VST=+2.0 V, f
max
TEST TEST SPT7810A SPT7810B
=20 MHz, 50% clock duty cycle, unless otherwise specified.
clock
Analog Input
Input Voltage Range VI ±2.0 ±2.0 V
Input Bias Current VIN=0 V VI 30 60 30 60 µA
Input Resistance VI 100 300 100 300 kΩ
Input Capacitance V 5 5 pF
Input Bandwidth 3 dB Small Signal V 120 120 MHz
+FS Error V ±2.0 ±2.0 LSB
-FS Error V ±2.0 ±2.0 LSB
Reference Input
Reference Ladder Resistance VI 500 800 500 800 Ω
Reference Ladder Tempco V 0.8 0.8 Ω/°C
Timing Characteristics
Maximum Conversion Rate VI 20 20 MHz
Overvoltage Recovery Time V 20 20 ns
Pipeline Delay (Latency) IV 1 1
Output Delay TA=+25 °CV5 5ns
Aperture Delay Time TA=+25 °CV1 1ns
Aperture Jitter Time TA=+25 °C V 5 5 ps-RMS
Dynamic Performance
Effective Number of Bits
f
=1 MHz 9.2 8.7 Bits
IN
f
=3.58 MHz 8.8 8.3 Bits
IN
fIN=10.3 MHz 7.5 7.0 Bits
Typical thermal impedances: 28L sidebrazed DIP. θja = 50 °C/W,
28L plastic DIP θja = 50 °C/W.
Clock Cycle
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ELECTRICAL SPECIFICATIONS
TA=T
PARAMETERS CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX UNITS
Dynamic Performance
- T
min
Signal-To-Noise Ratio
(without Harmonics)
Harmonic Distortion
Signal-to-Noise and Distortion
Spurious Free Dynamic Range +25 °C, f
Differential Phase +25 °C, fIN=3.58 & 4.35 MHz V 0.2 0.2 Degree
Differential Gain +25 °C, fIN=3.58 & 4.35 MHz V 0.5 0.7 %
, VCC=+5.0 V, VEE=-5.2 V, VIN=±2.0 V, VSB=-2.0 V, VST=+2.0 V, f
max
TEST TEST SPT7810A SPT7810B
=1 MHz +25 °C I 57 60 54 57 dB
f
IN
fIN=3.58 MHz +25 °C I 56 58 53 55 dB
fIN=10.3 MHz +25 °C I 50 53 47 49 dB
fIN=1 MHz +25 °C I 57 60 54 57 dB
fIN=3.58 MHz +25 °C I 56 58 53 55 dB
fIN=10.3 MHz +25 °C I 46 48 43 45 dB
fIN=1 MHz +25 °C I 55 57 52 54 dB
fIN=3.58 MHz +25 °C I 54 55 51 52 dB
fIN=10.3 MHz +25 °C I 44 47 41 44 dB
=1 MHz V 67 67 dB
IN
IV 55 58 52 55 dB
IV 54 56 51 53 dB
IV 47 50 44 46 dB
IV 54 57 51 54 dB
IV 53 55 50 52 dB
IV 45 47 42 44 dB
IV 52 49 dB
IV 51 48 dB
IV 43 40 dB
=20 MHz, 50% clock duty cycle, unless otherwise specified.
CLK
Digital Inputs
Logic 1 Voltage VI -1.1 -1.1 V
Logic 0 Voltage VI -1.5 -1.5 V
Maximum Input Current Low VI -500 ±200 +750 -500 ±200 +750 µA
Maximum Input Current High VI -500 ±300 +750 -500 +300 +750 µA
Pulse Width Low (CLK) IV 20 20 ns
Pulse Width High (CLK) IV 20 300 20 300 ns
Digital Outputs
Logic 1 Voltage 50 Ω to -2 V VI -1.1 -0.8 -1.1 -0.8 V
Logic 0 Voltage 50 Ω to -2 V VI -1.8 -1.5 -1.8 -1.5 V
Power Supply Requirements
Voltages V
Currents I
Power Dissipation Outputs Open VI 1.3 1.6 1.3 1.8 W
Power Supply Rejection Ratio (5 V ±0.25 V, -5.2 V ±2.0 V) V 1.0 1.0 LSB
-V
-I
CC
EE
CC
EE
IV +4.75 -5.0 +5.25 +4.75 +5.0 +5.25 V
IV -4.95 -5.2 -5.45 -4.95 -5.2 -5.45 V
VI 140 170 140 190 mA
VI 115 140 115 160 mA
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TEST LEVEL CODES
TEST LEVEL
TEST PROCEDURE
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
Figure 1A: Timing Diagram
N
t
pwH
CLK
t
pwL
II
III
IV
V
VI
I
100% production tested at the specified temperature.
100% production tested at TA=25 °C, and sample
tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
Parameter is a typical value for information purposes
only.
100% production tested at TA = 25 °C. Parameter is
guaranteed over specified temperature range.
N+1
N+2
CLK
Output
Data
t
d
Data Valid
N
Data Valid
N+1
Figure 1B: Single Event Clock
CLK
CLK
t
d
Output
Data
Data Valid
Table I - Timing Parameters
PARAMETERS DESCRIPTION MIN TYP MAX UNITS
t
d
t
pwH
CLK to Data Valid Prop Delay - 5 ns
CLK High Pulse Width 20 - 300 ns
t
pwL
SPT
CLK Low Pulse Width 20 - - ns
SPT7810
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SPECIFICATION DEFINITIONS
APERTURE DELAY
Aperture delay represents the point in time, relative to the
rising edge of the CLOCK input, that the analog input is
sampled.
APERTURE JITTER
The variations in aperture delay for successive samples.
DIFFERENTIAL GAIN (DG)
A signal consisting of a sine wave superimposed on various
DC levels is applied to the input. Differential gain is the
maximum variation in the sampled sine wave amplitudes at
these DC levels.
DIFFERENTIAL PHASE (DP)
A signal consisting of a sine wave superimposed on various
DC levels that is applied to the input. Differential phase is the
variation in the sampled sine wave phases at these DC levels.
EFFECTIVE NUMBER OF BITS (ENOB)
SINAD = 6.02N + 1.76, where N is equal to the effective
number of bits.
DIFFERENTIAL NONLINEARITY (DNL)
Error in the width of each code from its theoretical value.
(Theoretical = VFS/2N)
INTEGRAL NONLINEARITY (INL)
Linearity error refers to the deviation of each individual code
(normalized) from a straight line drawn from -Fs through +Fs.
The deviation is measured from the edge of each particular
code to the true straight line.
OUTPUT DELAY
Time between the clock's triggering edge and output data
valid.
OVERVOLTAGE RECOVERY TIME
The time required for the ADC to recover to full accuracy after
an analog input signal 125% of full scale is reduced to 50%
of the full-scale value.
SIGNAL-TO-NOISE RATIO (SNR)
The ratio of the fundamental sinusoid power to the total noise
power. Harmonics are excluded.
SINAD - 1.76
N =
6.02
± FULL-SCALE ERROR (GAIN ERROR)
Difference between measured full scale response
[(+Fs) - (-Fs)] and the theoretical response (+4 V -2 LSBs)
where the +FS (full scale) input voltage is defined as the
output transition between 1-10 and 1-11 and the -FS input
voltage is defined as the output transition between 0-00 and
0-01.
INPUT BANDWIDTH
Small signal (50 mV) bandwidth (3 dB) of analog input stage.
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
The ratio of the fundamental sinusoid power to the total noise
and distortion power.
TOTAL HARMONIC DISTORTION (THD)
The ratio of the total power of the first 64 harmonics to the
power of the measured sinusoidal signal.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
The ratio of the fundamental sinusoidal amplitude to the
single largest harmonic or spurious signal.
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TYPICAL PERFORMANCE CHARACTERISTICS
2
80
70
60
50
40
Signal-to-Noise Ratio (dB)
30
20
0
10
80
70
60
SNR vs Input Frequency
fs = 20 MSPS
1
Input Frequency (MHz)
10
SINAD vs Input Frequency
fs =20 MSPS
80
70
60
50
40
Total Harmonic Distortion (dB)
30
20
0
10
10
80
70
60
THD vs Input Frequency
fs = 20 MSPS
1
10
Input Frequency (MHz)
SNR, THD, SINAD vs Sample Rate
SNR, THD
2
10
50
40
30
Signal-to-Noise and Distortion (dB)
20
0
10
Spectral Response
0
-30
-60
Amplitude (dB)
-90
1
10
Input Frequency (MHz)
fs = 20 MSPS
fin = 1 MHz
2
10
50
f
40
in = 1 MHz
SNR, THD, SINAD (dB)
30
20
0
10
65
SNR
60
55
50
SNR, THD, SINAD (dB)
45
SINAD
1
10
Sample Rate (MSPS)
SNR, THD, SINAD vs Temperature
THD
SINAD
f
s = 20 MSPS
f
in = 1 MHz
THD
SNR
2
10
-120
0 12345678910
SPT
Input Frequency (MHz)
40
-25 0 +25 +50 +75
Temperature (°C)
SPT7810
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TYPICAL INTERFACE CIRCUIT
The SPT7810 requires few external components to achieve
the stated operation and performance. Figure 2 shows the
typical interface requirements when using the SPT7810 in
normal circuit operation.
the SPT7810. The AGND and the DGND ground planes
should be separated from each other and only connected
together at the device through an inductance. Doing this will
minimize the ground noise pickup.
VOLTAGE REFERENCE
The following section provides a description of the pin functions and outlines critical performance criteria to consider for
achieving the optimal device performance.
POWER SUPPLIES AND GROUNDING
The SPT7810 requires the use of two supply voltages, V
EE
and VCC. Both supplies should be treated as analog supply
sources. This means the VEE and VCC ground returns of the
device should both be connected to the analog ground
plane. All other -5.2 V requirements of the external digital
logic circuit should be connected to the digital ground plane.
Each power supply pin should be bypassed as closely as
possible to the device with .01 µF and 10 µF capacitors as
shown in figure 2.
The two grounds available on the SPT7810 are AGND and
DGND. DGND is used only for ECL outputs and is to be
referenced to the output pulldown voltage. These grounds
are not tied together internal to the device. The use of ground
planes is recommended to achieve the best performance of
Figure 2 - Typical Interface Circuit
The SPT7810 requires the use of two voltage references:
VFT and VFB. VFT is the force for the top of the voltage
reference ladder (+2.5 V typ), VFB (-2.5 V typ) is the force for
the bottom of the voltage reference ladder. Both voltages are
applied across an internal reference ladder resistance of 800
ohms. In addition, there are 3 reference ladder taps (VST,V
RM
and VSB). VST is the sense for the top of the reference ladder
(+2.0 V), VRM is the midpoint of the ladder (0.0 V typ)
and VSB is the sense for the bottom of the reference
ladder (-2.0 V). The voltages seen at VST and VSB are the
true full scale input voltages of the device when VFT and V
FB
are driven to the recommended voltages (+2.5 V and -2.5 V
typical respectively). These points should be used to monitor
the actual full scale input voltage of the device and should not
be driven to the expected ideal values as is commonly done
with standard flash converters. When not being used, a
decoupling capacitor of .01 uF connected to AGND from
each tap is recommended to minimize high frequency noise
injection.
An example of a reference driver circuit recommended is
shown in figure 2. IC1 is REF-03, the +2.5 V reference with a
10 µF
+
CLK-IN
CLK-IN
Analog
Input
Analog
Input
+5 V
IC1
(REF-03)
2
VIN
GND
.01 µF
*R2 and R3
matched to 0.1%
VOUT
4
CLK
CLK
VIN1
VIN2
+
.01 µF
6
Tri m
5
+5 V
7
R4
10 kΩ
10 µF
+2.5 V
R1
10 kΩ
*
R2
30 kΩ
3
2
+
-
IC2
(OP-07)
-5.2 V
4
1
8
6
.01 µF
10 µF
VFT
VST
.01 µF
VRM
.01 µF
R3
*
30 kΩ
VSB
.01 µF
VFB
-2.5 V
.01 µF
+
NOTE: D1=D2=1N5817 or equivalent. (Used to prevent damage caused by power sequencing.)
VEE
-5.2 V +5 V
D1
2
DGND
( -2 V RTN )
D10 (OVERRANGE)
D9 (MSB)
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
DG
10 µF
+
.01 µF
Digital Outputs
11 x 50 Ω
-2 V-5.2 V +5 V
AG
AGND
( 5 V RTN &
-5.2 V RTN )
4
Decoding Network
DG
AG
L
10 µH
Coarse
A/D
ANALOG
PRESCALER
R
2R
2R
2R
2R
R
VEE
T/H AMPLIFIER
BANK
SUCCESSIVE
INTERPOLATION
STAGE # i
SUCCESSIVE
INTERPOLATION
STAGE # N
VCC
VCC
10 µF
+
.01 µF
D2
+
10 µF
.01 µF
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Page 8
tolerance of 0.6% or ± 0.015 V. The potentiometer R1 is
C
C
C
10 kΩ and supports a minimum adjustable range of up to 150
mV. IC2 is recommended to be an OP-07 or equivalent
device. R2 and R3 must be matched to within 0.1% with good
TC tracking to maintain a 0.3 LSB matching between VFT and
VFB. If 0.1% matching is not met, then potentiometer R4 can
be used to adjust the VFB voltage to the desired level. R1 and
R4 should be adjusted such that VST and VSB are exactly
+2.0 V and -2.0V respectively.
The analog input range will scale proportionally with respect
to the reference voltage if a different input range is required.
The maximum scaling factor for device operation is ± 20% of
the recommended reference voltages of VFT and VFB. However, because the device is laser trimmed to optimize performance with ± 2.5 V references, the accuracy of the device will
degrade if operated beyond a ± 2% range.
The following errors are defined:
+FS error = top of ladder offset voltage = ∆(+FS -VST+1 LSB)
-FS error = bottom of ladder offset voltage = ∆(-FS -V
SB
-1 LSB)
where the +FS (full scale) input voltage is defined as the
output transition between 1-10 and 1-11 and the -FS input
voltage is defined as the output transition between 0-00 and
0-01.
ANALOG INPUT
V
IN1
and V
are the analog inputs. Both inputs are tied to
IN2
the same point internally. Either one may be used as an
analog input “sense” and the other for an input “force." The
inputs can also be tied together and driven from the same
source. The full scale input range will be 80% of the reference
voltage or ±2 volts with VFB=-2.5 V and VFT=+2.5 V.
DIGITAL OUTPUTS
The format of the output data (D0-D9) is straight binary.
These outputs are ECL with the output circuit shown in
figure 4. The outputs are latched on the rising edge of CLK
with a propagation delay of 4 ns. There is a one clock cycle
latency between CLK and the valid output data (see timing
diagram). These digital outputs can drive 50 ohms to ECL
levels when pulled down to -2 V. The total specified power
dissipation of the device does not include the power used by
these loads. The additional power used by these loads can
vary between 10 and 300 mW typically (including the overrange
load) depending on the output codes. If lower power levels
are desired, the output loads can be reduced, but careful
consideration to the capacitive loads in relation to the operating frequency must be considered.
Table II - Output Data Information
ANALOG INPUT OVERRANGE OUTPUT CODE
D1O D9-DO
>+2.0 V + 1/2 LSB 1 11 1111 1111
+2.0 V -1 LSB O 11 1111 111Ø
0.0 V O ØØ ØØØØ ØØØØ
-2.0 V +1 LSB O OO OOOO OOOØ
<-2.0 V O OO OOOO OOOO
(Ø indicates the flickering bit between logic 0 and 1).
Figure 3 - Output Circuit
AGND
DGND
The drive requirements for the analog inputs are minimal
when compared to conventional Flash converters due the
SPT7810’s extremely low input capacitance of only 5 pF and
very high input resistance of 300 kΩ. For example, for an input
signal of ± 2 V p-p with an input frequency of 10 MHz, the peak
output current required for the driving circuit is only 628 µA.
CLOCK INPUT
The clock inputs (CLK,
) are designed to be driven
LK
differentially with ECL levels. The clock may be driven single
ended since
is internally biased to -1.3 V.
LK
may be
LK
left open, but a .01 µF bypass capacitor to AGND is recommended. As with all high speed circuits, proper terminations
are required to avoid signal reflections and possible ringing
that can cause the device to trigger at an unwanted time.
The CLK pulse width (tpwH) must be kept between 10 ns and
300 ns to ensure proper operation of the internal track-and-hold
amplifier. (See timing diagram.) When operating the SPT7810
at sampling rates above 3 MSPS, it is recommended that the
clock input duty cycle be kept at 50% to optimize performance.
The analog input signal is latched on the rising edge of the CLK.
SPT
Data Out
OVERRANGE OUTPUT
The OVERRANGE OUTPUT (D10) is an indication that the
analog input signal has exceeded the positive full scale input
voltage by 1 LSB. When this condition occurs, D10 will switch
to logic 1. All other data outputs (D0 to D9) will remain at logic 1
as long as D10 remains at logic 1. This feature makes it
possible to include the SPT7810 into higher resolution systems.
EVALUATION BOARD
The EB7810 evaluation board is available to aid designers in
demonstrating the full performance of the SPT7810. This
board includes a reference circuit, clock driver circuit, output
data latches and an on-board reconstruction of the digital
data. An application note describing the operation of this
board as well as information on the testing of the SPT7810 is
also available. Contact the factory for price and availability.
SPT7810
8 3/11/97
Page 9
PACKAGE OUTLINE
28-Lead Sidebrazed
28
H
SYMBOL MIN MAX MIN MAX
I
1
J
G
A
INCHES MILLIMETERS
A 0.077 0.093 1.96 2.36
B 0.016 0.020 0.41 0.51
C 0.095 0.105 2.41 2.67
D .050 typ 0.00 1.27
E 0.040 0.060 1.02 1.52
F 0.215 0.235 5.46 5.97
G 1.388 1.412 35.26 35.86
H 0.585 0.605 14.86 15.37
I 0.009 0.012 0.23 0.30
J 0.600 0.620 15.24 15.75
E
F
C
B
D
28-Lead Plastic DIP
K
28
SYMBOL MIN MAX MIN MAX
I
1
J
A
B
C
D
E
F
H
G
INCHES MILLIMETERS
A 0.200 5.08
B 0.120 0.135 3.05 3.43
C 0.020 0.51
D 0.100 2.54
E 0.067 1.70
F 0.013 0.33
G 0.170 0.180 4.32 4.57
H 0.622 15.80
I 0.555 14.10
J 1.460 37.08
K 0.085 2.16
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PIN ASSIGNMENTS
1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
DGND
CLK
2
3
4
5
6
7
8
9
10
11
12
13
14
Sidebrazed
and PDIP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDGND
EE
AGND
V
CC
V
FB
V
SB
V
RM
V
IN1
V
IN2
V
ST
V
FT
V
CC
AGND
V
EE
CLK
PIN FUNCTIONS
Name Function
DGND Digital Ground
D0-D9 ECL Outputs (D0=LSB)
D10 ECL Output Overrange
CLK Clock Input
CLK
V
EE
AGND Analog Ground
V
CC
V
, V
IN1
IN2
V
FT
V
ST
V
FB
V
SB
V
RM
Inverted Clock Input
-5.2 V Supply
+5.0 V supply
Inputs (tied together at the die)
Force for Top of Reference Ladder
Sense for Top of Reference Ladder
Force for Bottom of Reference Ladder
Sense for Bottom of Reference Ladder
Middle of Reference Ladder
ORDERING INFORMATION
PART NUMBER TEMPERATURE RANGE PACKAGE TYPE
SPT7810AIJ -25 to +85 °C 28L Sidebrazed DIP
SPT7810BIJ -25 to +85 °C 28L Sidebrazed DIP
SPT7810ACN 0 to +70 °C 28L Plastic DIP
SPT7810BCN 0 to +70 °C 28L Plastic DIP
SPT7810BCU +25 °C Die*
*Please see the die specification for guaranteed electrical performance.
Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby expressly
granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited.
WARNING - LIFE SUPPORT APPLICATIONS POLICY - SPT products should not be used within Life Support Systems without the specific
written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably
expected to result in significant personal injury or death.
Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device
failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.
SPT
SPT7810
10 3/11/97
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