Datasheet SPT7730 Datasheet (Fairchild Semiconductor)

SPT7730

A

A

8-BIT, 3.0 MSPS, SERIAL OUTPUT A/D CONVERTER

FEATURES

• 8-Bit, 1 kHz to 3.0 MSPS Analog-to-Digital Converter

• Monolithic CMOS

• Serial Output

• Internal Sample-and-Hold

• Analog Input Range: 0 to 2 V Nominal; 3.3 V Max

• Power Dissipation (Excluding Reference Ladder)
45 mW at +5 V
16 mW at +3 V

• Single Power Supply: +3 V to +5 V Range

• High ESD Protection: 3,000 V Minimum

GENERAL DESCRIPTION

The Fairchild 8-bit, 3.0 MSPS, serial analog-to-digital con­verter delivers excellent high speed conversion performance
with low cost and low power. The serial port protocol is
compatible with the serial peripheral interface (SPI) or
MICROWIRE™ industry standard, high-speed synchronous
MPU interfaces. The large input bandwidth and fast transient
response time allow for CCD applications operating up to

3.0 MSPS.

APPLICATIONS

• Handheld and Desktop Scanners

• DSP Interface Applications

• Portable Digital Radios

• Portable and Handheld Applications

• Automotive Applications

• Remote Sensing

The device can operate with a power supply range from +3 V
to +5 V with very low power dissipation. The small package
size makes this part excellent for handheld applications
where board space is a premium. The SPT7730 is available
in an 8-lead SOIC package over the commercial tempera­ture range. Contact the factory for availability of die and
industrial temperature range versions.

BLOCK DIAGRAM

Analog Input

Start Convert

Clock

Ground

Track-and-Hold

SAR
8-Bit

A/D

AAAAAAAAAAAAAAAAAA

Timing And Control

Serial

Output

Logic

AAAAAAAAAAAAAAAAAA

V

REF+

V

REF-

V

DD

Data Out

ABSOLUTE MAXIMUM RATING (Beyond which damage may occur)

1

Supply Voltages

VDD...........................................................................+6 V

Input Voltages

Analog Input ................................................. -0.7 to +6 V

V

+ ........................................................... -0.7 to +6 V

REF

V

- ............................................................ -0.7 to +6 V

REF

Clock and SC............................................... -0.7 to +6 V

Output

Data Out ................................................................10 mA

Temperature

Operating, ambient ..................................... 0 to 70 °C

junction........................................ + 175 °C

Lead, Soldering (10 seconds) ...........................+ 300 °C

Storage ................................................... -65 to + 150 °C

Note: 1. Operation at any Absolute Maximum Ratings is not implied. See Electrical Specifications for proper nominal applied

conditions in typical applications.

ELECTRICAL SPECIFICATIONS

TA = +25 °C, VDD = +5.0 V, VIN = 0 to +3 V, f

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS

DC ELECTRICAL CHARACTERISTICS

DC Performance

Resolution 8 Bits
Differential Linearity I ±0.2 ±0.5 LSB
Integral Linearity I ±0.2 ±0.5 LSB
No Missing Codes I Guaranteed

Analog Input

Input Voltage Range
Input Resistance I 5 MΩ
Input Capacitance IV 5 pF
Input Bandwidth (Small Signal) IV 30 MHz
Offset IV -2 +2 % of FSR
Gain Error IV -2 +2 % of FSR

Reference Input

Resistance IV 250 280 350 Ω
Voltage Range

2

V

REF-

2

V

REF+

V

REF+ -VREF-

Reference Settling Time IV 90 ns

Timing Characteristics

Maximum Conversion Rate I 3.0 1.0 MSPS
Minimum Conversion Rate IV 1 kSPS
Maximum External Clock Rate I 36 12 MHz
Minimum External Clock Rate IV 12 kHz
Aperture Delay Time IV 5 ns
Aperture Jitter Time IV 5 ps
Data Ouput LSB Hold Time T

1

Percentages refer to percent of [(V

2

∆ = Minimum (V

1

1

(∆) IV 1/10 V

REF+

REF+ -VREF-

)

= 36 MHz, fS = 3.0 MSPS, V

CLK

REF

TEST TEST

to T

MIN

) -(V

REF-

MAX

)]

+ = +3.0 V, V

IV V

REF-

IV -4% 0 V
IV V

- = 0.0 V, unless otherwise specified.

REF

+4% V

+∆ 2/3 V

REF-

DD

REF+

REF+

-6% V

-∆ V

DD

V
V

IV 6 8 ns

SPT7730

2 12/19/97

ELECTRICAL SPECIFICATIONS

TA = +25 °C, VDD = +5.0 V, VIN = 0 to +3 V, f

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS

Dynamic Performance

Effective Number of Bits

f

= 500 kHz IV 7.5 Bits

IN

Signal-to-Noise Ratio

fIN = 500 kHz IV 47 dB

Harmonic Distortion

fIN = 500 kHz IV 60 dB

Power Supply Requirements

+V

Supply Voltage IV 3 5.5 V

DD

+V

Supply Current VDD = 3.0 V IV 5.4 7 mA

DD

Power Dissipation V

3

Excluding the reference ladder.

3

TEST LEVEL CODES

All electrical characteristics are subject to the
following conditions:

All parameters having min/max specifications
are guaranteed. The Test Level column indi­cates the specific device testing actually per­formed during production and Quality Assur­ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.

= 36 MHz, fS = 3.0 MSPS, V

CLK

TEST TEST

= 5.0 V I 9 10 mA

V

DD

= 3.0 V IV 16 22 mW

DD

VDD = 5.0 V I 45 50 mW

TEST LEVEL

I

II

+ = +3.0 V, V

REF

- = 0.0 V, unless otherwise specified.

REF

TEST PROCEDURE

100% production tested at the specified temperature.
100% production tested at TA=25 °C, and sample

tested at the specified temperatures.
III
IV

QA sample tested only at the specified temperatures.

Parameter is guaranteed (but not tested) by design

and characterization data.

V

Parameter is a typical value for information purposes

only.
VI

100% production tested at TA = 25 °C. Parameter is

guaranteed over specified temperature range.

SPT7730

3 12/19/97

GENERAL DESCRIPTION AND OPERATION

The SPT7730 is an 8-bit analog-to-digital converter that
uses a successive approximation architecture to perform
data conversion. Each conversion cycle is 12 clocks in
length. When the Not Start Convert (SC) line is held low,
conversion begins on the next rising edge of the input clock.
When the conversion cycle begins, the data output pin is
forced low until valid data output begins.

The first two clock cycles are used to perform internal offset
calibrations and to track the analog input. The analog input
is then sampled using an internal track-and-hold amplifier on
the falling edge of the third clock cycle. On clock cycles 4
through 12, an 8-bit successive approximation conversion is
performed, and the data is output starting with the MSB.

Serial data output begins with output of the MSB. See the
Data Output Timing section for details. Each bit of the data
conversion is sequentially determined and placed on the
data output pin at the clock rate. This process continues until
the LSB has been determined and output. At this point, if the

line is high, the data output pin will be forced into a high

SC

impedance state, and the converter will go into an idle state
waiting for the SC line to go low. This is referred to as Single
Shot Mode. See Modes of Operation for details.

If the SC is either held low through the entire 12 clock
conversion cycle (free run mode) or is brought low prior to the
trailing edge of the twelfth clock cycle (synchronous mode),
the data output pin goes low and stays low until valid data
output begins. Because the chip has either remained se­lected in the free run mode or has been immediately selected
again in the synchronous mode, the next conversion cycle
begins immediately after the twelfth clock cycle of the previ­ous conversion. See Modes of Operation for details.

TYPICAL INTERFACE CIRCUIT

CLOCK INPUT

The SPT7730 requires a 50% ±10 % duty cycle clock running
at 12 times the desired sample rate. The clock may be
stopped in between conversion cycles without degradation
of operation (single shot type of operation), however, the
clock should remain running during a conversion cycle.

POWER SUPPLY

The SPT7730 requires only a single supply and operates
from 3.0 V to 5.0 V. Fairchild recommends that a 0.01 µF chip
capacitor be placed as close as possible to the supply pin.

DATA OUTPUT SET UP AND HOLD TIMING

As figure 8 shows, all of the data output bits (except the LSB)
remains valid for a duration equivalent to one clock period
and delayed by 8 ns after the falling edge of clock. Because
the data converter enters into a next conversion ready state
at the leading edge of clock 12, the LSB bit is valid for a

duration equivalent to only the clock pulse width low
and delayed by 8 ns after the falling edge of clock. Care

should be taken to ensure that the LSB is latched into an
external latch with the proper amount of set and hold time.

DATA OUTPUT CODING

The coding of the output is straight binary. (See table I.)

Table I - Data Output Coding

ANALOG INPUT OUTPUT CODE D7 - DO
+FS - 1/2 LSB 1111 111Ø
+1/2 FS ØXXX XXXX
+1/2 LSB OOOO OOOØ
V

REF-

OOOO OOOO

Ø indicates the flickering bit between logic O and 1.
X indicates the flickering bit between logic 1 and O.

ANALOG INPUT AND REFERENCE SETTLING TRACK
AND HOLD TIMING

Figure 9 shows the timing relationship between the input
clock and SC versus the analog input tracking and reference
settling. The analog input is tracked from the twelfth clock
cycle of the previous conversion to the third clock cycle of the
current conversion. On the falling edge of the third clock
cycle, the analog input is held by the internal sample-and­hold. After this sample, the analog input may vary without
affecting data conversion.

The reference ladder inputs (V

REF

+ and V

-) may be

REF

changed starting on the falling edge of the eleventh clock
cycle of the previous conversion and must be settled by the
falling edge of the third clock cycle of the current conversion.
(See figure 9.)

VOLTAGE REFERENCE AND ANALOG INPUT

The SPT7730 requires the use of a single external voltage
reference for driving the high side of the reference ladder.
The V
VDD = +5 V, then V

+ can be a maximum of 2/3 VDD. For example, if

REF

+ max = (2/3) * 5 V = +3.3 V. The lower

REF

side of the ladder is typically tied to AGND (0.0 V) but can be
run up to a voltage that is 1/10th of VDD below V

V

- max. = V

REF

+ - (1/10) * VDD.

REF

REF

+:

For example,

if VDD = +5 V and V
V

- max. = 3 V - (1/10)* 5 V = 2.5 V.

REF

+ = 3 V, then

REF

The +Full Scale (+FS) of the analog input is expected to be 6%
of [(V
of the analog input is expected to be 4% of [(V
above V

REF

+)-(V

REF

-)] below V

REF

-. (See figure 1.)

+ and the -Full Scale (-FS)

REF

REF

+) - (V

REF

-)]

Therefore,
Analog +FS = V
Analog -FS = V

+ - 0.06 * [(V

REF

- +0.04 * [(V

REF

REF

REF

+) - (V

+) - (V

REF

REF

-)], and

-)].

For example,

if V

+ = 3 V and V

REF

- = 0 V, then

REF

Analog + FS = 3 V - 0.06 * [3 V- 0 V ] = 2.82 V, and
Analog - FS = 0 V + 0.04 * [3 V - 0 V] = 0.12 V.

SPT7730

4 12/19/97

Figure 1 - Analog Input Full-Scale Range

V

+

REF

+FS

Full-Scale Range

-FS

V

-

REF

6% of [(V

REF

+) - (V

4% of [(V

REF

-)]

REF

+) - (V

REF

-)]

The drive requirements for the analog input are minimal
when compared to most other converters due to the
SPT7730’s extremely low input capacitance of only 5 pF and
very high input resistance of greater than 5 MΩ.

If the input buffer amplifier supply voltages are greater than
VDD + 0.7 V or less than Ground - 0.7 V, the analog input
should be protected through a series resistor and a diode
clamping circuit as shown in figure 2.

Figure 2 - Recommended Input Protection Circuit

ADCBuffer

AV

DD

+V

D1

47 Ω

D2

MODES OF OPERATION

The SPT7730 has three modes of operation.The mode of
operation is based strictly on how the SC is used.

SINGLE SHOT MODE

When SC goes low, conversion starts on the next rising edge
of the clock (defined as the first conversion clock). The MSB
of data is valid 8 ns after the falling edge of the fourth
conversion clock. (See figure 8.)

The conversion is complete after 12 clock cycles. At the
falling edge of the twelfth clock cycle, if SC is high (not
selected), the data output goes to a high impedance state,
and no more conversions will take place until the next SC low
event. (See the single shot mode timing diagram in figure 4.)

SYNCHRONIZED MODE

When SC goes low, conversion will start on the next rising
edge of the clock (defined as the first conversion clock). The
MSB is valid 8 ns after the falling edge of the fourth conver­sion clock.

The first conversion is complete after 12 clock cycles. At
any time after the falling edge of the twelfth clock cycle,
may go low again to initiate the next conversion. When the

goes low, the conversion starts on the rising edge of the

SC

next clock. (See the synchronized mode timing diagram
in figure 5.)

The data output will go to a high impedance state until the
next conversion is initiated.

SC

-V

D1 = D2 = Hewlett Packard HP5712 or equivalent

INPUT PROTECTION

All I/O pads are protected with an on-chip protection circuit
shown in figure 3. This circuit provides ESD robustness to
>3.0 kV and prevents latch-up under severe discharge
conditions without degrading analog transition times.

Figure 3 - On-Chip Protection Circuit

V

DD

120 Ω

120 Ω

Pad

Analog

FREE RUN MODE

When SC goes low, conversion starts on the next rising edge
of the clock (defined as the first conversion clock). The MSB
data is valid 8 ns after the falling edge of the fourth conver­sion clock.

As long as SC is held low, the device operates in the free run
mode. New conversions start after every twelfth cycle with
valid data available 8 ns after the falling edge of the fourth
clock within each new conversion cycle.

The data output remains low between conversion cycles.
(See the free run mode timing diagram in figure 6.)

SPT7730

5 12/19/97

Figure 4 - Single Shot Mode Timing Diagram

5
A

4
A

Clock

Data Out A7 A1

td=8 ns

1
1
A

1
2

A

td=8 ns td=8 ns td=8 ns

MSB

A0

LSB

t

SC

Start Convert

Clock

Serial Data Out

1

2

A

A3A

Latch

MSB

4

5

A

A

A7 A6 A5 A4 A3 A2 A1 A0

MSB LSB

Start

Conversion

Sample

Analog Input

Figure 5 - Synchronous Mode Timing Diagram

t

SC

Start Convert

Clock

Serial Data Out

Start

1

2
A

3
A4A

Sample

Analog Input

A

A

Latch

MSB

5
A

A7 A6 A5 A4

MSB LSB

6
A7A

6
A

7A8

8

9A10A11A12

A

11

A

A

A0A1

12

A

High Z State

A

High Z State

t

SC

Latch

MSB

1
B2B

3
B4B

5
B

B7

MSB

Sample

Analog Input

B

Figure 6 - Free Run Mode Timing Diagram

Start Convert

Clock

Serial Data Out

Start

1

2
A

3
A4A

Sample

Analog Input

A

A

Latch

MSB

5

6

A

7A8

A

1

A

1
A

A1

MSB LSB

1

1

2

B2B

A

3
B4B

A0

Sample

Analog Input

B

Figure 7 - Typical Interface Circuit Figure 8 - Data Output Timing

V

V

REF+

0 V

REF IN

V

IN

REF

Analog In

V

REF

Ground

+

-

V

DD

Data Out

Clock

SC

+V

DD

.01 µF.01 µF

+V

DD

0 V

+V

DD

0 V

+V

DD

0 V

5B6

B7 B6 B5A7 A6 A5 A4

MSB

7

B

B

6 12/19/97

SPT7730

Figure 9 - Analog Input Track-and-Hold Timing and Reference Settling-and-Hold Timing

SC

Clock

V

REF+

A

IN

Synchronous Mode

1

A

*

The rising edge of the SC line can occur any time between the
rising edge of clock 1A and the falling edge of clock 12A.

The reference settling window can be extended in the

**

synchronous mode by adding extra clocks between conversion
cycles. The example shown is the minimum number of clocks
required (12) per conversion cycle.

2
A

3
A

Sample

Input

*

4

A

Ref Hold

11

Single Shot Mode

SC

(

12

A

A

Ref Settling Window

high, no B cycle)

Free Run Mode (SC always Ø)

1
B

2
B

3
B

4

B

**

Sample

Input

G

PACKAGE OUTLINE

8-Lead SOIC

A

SYMBOL MIN MAX MIN MAX

B

INCHES MILLIMETERS

A 0.187 0.194 4.80 4.98
B 0.228 0.242 5.84 6.20
C 0.050 typ 1.27 typ
D 0.014 0.019 0.35 0.49
E 0.005 0.010 0.13 0.25
F 0.060 0.067 1.55 1.73
G 0.055 0.060 1.40 1.55
H 0.149 0.156 3.81 3.99

I0° 8° 0° 8°

J 0.007 0.010 0.19 0.25

K 0.016 0.035 0.41 0.89

H

F

C D E

I J

K

SPT7730

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PIN ASSIGNMENTS

Start Convert

External V

Analog In

External V

REF

REF

Ground

+

1

2

-

3

4

8

7

6

5

V

DD

Data Out

Clock

Start Convert

PIN FUNCTIONS

Name Function

Analog In Analog Signal Input

Start Convert. A high-to-low transition on
this input begins the conversion cycle and
enables serial data output.

Clock Clock that drives A/D conversion cycle and

the synchronous serial data output

Data Out Serial Data. Tri-state serial data output for

the A/D result driven by the CLOCK input

External V

External V

V

DD

GND Analog and Digital Ground

+ External voltage reference for top of

REF

reference ladder

- External voltage reference for bottom of

REF

reference ladder
Analog and Digital +3 V to +5 V

Power Supply Input

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE

SPT7730SCS 0 to +70 °C 8L SOIC
SPT7730SCU* +25 °C Die*

*Please see the die specification for guaranteed electrical performance.

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO
IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF
ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF
OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.

www.fairchildsemi.com © Copyright 2002 Fairchild Semiconductor Corporation

2. A critical component is any component of a life support device or system
whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its safety or effectiveness.

SPT7730

8 12/19/97