Datasheet SPT7725 Datasheet (Fairchild Semiconductor)

SPT7725

8-BIT, 300 MSPS, FLASH A/D CONVERTER

TECHNICAL DATA

AUGUST 17, 2001

FEATURES

• Metastable errors reduced to 1 LSB

• Low input capacitance: 10 pF

• Wide input bandwidth: 210 MHz

• 300 MSPS conversion rate

• Typical power dissipation: 2.2 watts

GENERAL DESCRIPTION

The SPT7725 is a monolithic flash A/D converter capable
of digitizing a two volt analog input signal into 8-bit digital
words at a 300 MSPS (typ) update rate.

For most applications, no external sample-and-hold is re­quired for accurate conversion due to the device’s narrow
aperture time, wide bandwidth, and low input capacitance.
A single standard –5.2 volt power supply is required for
operation of the SPT7725, with nominal power dissipation

BLOCK DIAGRAM

V

RTS

V

RTF

Analog Input

(Force or Sense)

AGND DGND V

Preamp Comparator

256

255

EE

Clock
Buffer

APPLICATIONS

• Digital oscilloscopes

• Transient capture

• Radar, EW, ECM

• Direct RF down-conversion

• Medical electronics: ultrasound, CAT instrumentation
of 2.2 W. A proprietary decoding scheme reduces meta-

stable errors to the 1 LSB lev el.
The SPT7725 is available in 42-lead ceramic sidebrazed

DIP, surface-mount 44-lead cerquad, and 46-lead PGA
packages (all are pin-compatible with the SPT7710); the
cerquad and PGA packages allow access to additional
reference ladder taps, an overrange bit, and a data ready
output. The SPT7725 is available in the industrial tem­perature range.

LINV MINV

DRINV

MSB D7

DREAD

Convert

V
V

V

V

V

RBF

RBS

CLK
CLK

R3

R2

R1

(Sense or Force)

152

151

128

256 to

127

64

63

2

1

2

8-Bit

Encoder

V

EE

D6

D5

D4

D3

D2

D1

LSB D0

AGNDAnalog Input

ECL

Latches

and

Buffers

Overrange

D7 MSB

D6

D5

These functions are

D4

available in the PGA and
cerquad packages only.

D3

D2

D1

D0 LSB

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C

Supply Voltages

Negative Supply Voltage (VEE TO GND) –7.0 to +0.5 V

Ground Voltage Differential ....................–0.5 to +0.5 V

Input Voltage

Analog Input Voltage ...............................V

to +0.5 V

EE

Temperature

Operating Temperature,ambient............. –25 to +85 °C

junction ...................... +150 °C

Lead Temperature, (soldering 10 seconds) ..... +300 °C

Storage Temperature............................ –65 to +150 °C

Reference Input Voltage..........................VEE to +0.5 V

Digital Input Voltage ................................VEE to +0.5 V

Reference Current V

Output

Digital Output Current ............................... 0 to –30 mA

RTF

to V

........................25 mA

RBF

Note: 1. Operation at any Absolute Maximum Rating is not implied. See

Electrical Specifications for proper nominal applied conditions
in typical applications.

ELECTRICAL SPECIFICATIONS

TA= T

PARAMETERS CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX UNITS
DC Accuracy

Analog Input

to T

MIN

, VEE=–5.2 V , R

MAX

Source

=50 Ω, V

=–2.00 V , VR2=–1.00 V , V

RBF

=0.00 V , ƒ

RTF

=250 MHz, Duty Cycle=50%, unless otherwise specified.

CLK

TEST TEST SPT7725A SPT7725B

Integral Linearity Error ƒ
Differential Linearity Error ƒ

= 100 kHz VI –0.75 ±0.60 +0.75 –0.95 ±0.80 +0.95 LSB

CLK

= 100 kHz VI –0.75 +0.75 –0.95 +0.95 LSB

CLK

No missing codes Guaranteed Guaranteed

Offset Error V
Offset Error V

RT
RB

VI –30 +30 –30 +30 mV

VI –30 +30 –30 +30 mV
Input Voltage Range VI –2.0 0.0 –2.0 0.0 Volts
Input Capacitance Over full

input range V 10 10 pF
Input Resistance V 15 15 kΩ
Input Current VI 250 500 250 500 µA
Input Slew Rate V 1,000 1,000 V/µs
Large Signal Bandwidth V
Small Signal Bandwidth V

=F.S. V 210 210 MHz

IN

=500 mV

IN

P-P

V 335 335 MHz

Clock Synchronous

Input Currents V 40 40 µA

Reference Input

Ladder Resistance VI 100 200 300 100 200 300 Ω
Reference Bandwidth V 10 10 MHz

Timing Characteristics

Maximum Sample Rate IV 250 300 250 300 MSPS
Clock to Data Delay V 2.4 2.4 ns
Output Delay Tempco V 2 2 ps/°C
CLK-to-Data Ready Delay (t

) V 2.0 2.0 ns

D

Aperture Jitter V 5 5 ps
Acquisition Time V 1.5 1.5 ns

Dynamic Performance

Signal-to-Noise Ratio ƒ

= 3.58 MHz VI 45 47 44 46 dB

IN

= 50 MHz VI 39 42 38 41 dB

ƒ

IN

Total Harmonic Distortion ƒIN = 3.58 MHz VI –52 –48 –50 –46 dB

= 50 MHz VI –43 –40 –42 –39 dB

ƒ

IN

Signal-to-Noise and Distortion ƒ

= 3.58 MHz VI 44 46 42 44 dB

IN

(SINAD) ƒIN = 50 MHz VI 37 39 35 37 dB

2 8/17/01

SPT7725

ELECTRICAL SPECIFICATIONS

TA= T

MIN

to T

MAX

, VEE=–5.2 V , R

Source

=50 Ω, V

=–2.00 V , VR2=–1.00 V , V

RBF

=0.00 V , ƒ

RTF

=250 MHz, Duty Cycle=50%, unless otherwise specified.

CLK

TEST TEST SPT7725A SPT7725B

PARAMETERS CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX UNITS
Digital Inputs

Digital Input High Voltage
(MINV, LINV) VI –1.1 –0.7 –1.1 –0.7 Volts
Digital Input Low Voltage
(MINV, LINV) VI –2.0 –1.5 –2.0 –1.5 Volts
Clock Low Width, t
Clock High Width, t

PWL

PWH

VI 2.2 2.0 2 1.8 ns
VI 2.2 2.0 2 1.8 ns

Digital Outputs

Digital Output High Voltage 50 Ω to –2 V VI –1.1 –1.1 Volts
Digital Output Low Voltage 50 Ω to –2 V VI –1.5 –1.5 Volts

Power Supply Requirements

Supply Current +25 °C VI 425 550 425 550 mA
Power Dissipation +25 °C VI 2.2 2.9 2.2 2.9 W

TEST LEVEL CODES

All electrical characteristics are subject to the
following conditions:

All parameters having min/max specifications
are guaranteed. The Test Level column indi­cates the specific device testing actually per­formed during production and Quality Assur­ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.

LEVEL TEST PROCEDURE

I 100% production tested at the specified temperature.

II 100% production tested at TA = +25 °C, and sample tested at the

specified temperatures.
III QA sample tested only at the specified temperatures.
IV Parameter is guaranteed (but not tested) by design and characteri-

zation data.

V Parameter is a typical value for information purposes only.

VI 100% production tested at TA = +25 °C. Parameter is guaranteed

over specified temperature range.

Unless otherwise noted, all test are pulsed
tests; therefore, T

= TC = TA.

J

SPT7725

3 8/17/01

TYPICAL PERFORMANCE CHARACTERISTICS

SNR vs Input Frequency

52

50

S = 250 MSPS

48

46

44

42

40

Signal-to-Noise Ratio (dB)

38

36

34

1 10 100

Input Frequency (MHz)

THD vs Input Frequency

75

70

65

60

55

50

45

40

Total Harmonic Distortion (dB)

35

30

1 10 100

S = 250 MSPS

Input Frequency (MHz)

SINAD vs Input Frequency SNR, THD, SINAD vs Temperature

52

50

S = 250 MSPS

48

46

44

42

40

38

Signal-to-Noise and Distortion (dB)

36

34

1 10 100

Input Frequency (MHz)

50

45

40

SNR, THD, SINAD (dB)

35

30

40 20 0 20 40 60 80

Temperature (°C)

S = 250 MSPS
IN = 100 MHz

THD

SNR

SINAD

SPT7725

4 8/17/01

Figure 1 – Typical Interface Circuit 1

.01 µF

EE

100116

Analog Input
Can Be Either
Force Or Sense

.01 µF

V

2.2
Q1 (1N2907A)

2.2 µF

50 W

(Analog)

EE

10

2 V

Typical Voltage Limiter

R

S

D1

49.9

5.2

D1=D2=HP, 1N 5712

*See below

+

U1



R

T

D2

Analog Input
Can Be Either
Force Or Sense

Voltage
Limiter

V

Ref

2 V

+

U2



V

Convert

V

.01 µF

50 W

RTF

V

R2

V

RBF

V

CLK

CLK

.01 µF

L

AGND

V

IN

Preamp Comparator

256

255

152

151

128

127

64

63

2

1

IN

2

AGND

.01 µF

Clock
Buffer

2.2 µF

.01 µF

V

EE

5.2 V

V

EE

5.2 V

256 To

8-Bit

Encoder

LINV MINV

ECL

Latches

And

Buffers

DGND

MSB D7

D6

D5

D4

D3

D2

D1

LSB D0

.01 µF

50 W

50 W

2 V (Digital)

GENERAL DESCRIPTION

The SPT7725 is a fast monolithic 8-bit parallel flash A/D
converter. The nominal conversion rate is 300 MSPS and
the analog bandwidth is in excess of 200 MHz. A major ad­vance over previous flash converters is the inclusion of
256 input preamplifiers between the reference ladder and
input comparators. (See block diagram.) This not only re­duces clock transient kickback to the input and reference
ladder due to a low AC beta but also reduces the effect of
the dynamic state of the input signal on the latching char­acteristics of the input comparators. The preamplifiers act
as buffers and stabilize the input capacitance so that it re­mains constant for varying input voltages and frequencies
and, therefore, makes the part easier to drive than previ­ous flash converters. The SPT7725 incorporates a propri­etary decoding scheme that reduces metastable errors
(sparkle codes or

flyers

) to a maximum of 1 LSB.

The SPT7725 has true differential analog and digital data
paths from the preamplifiers to the output buffers (Current
Mode Logic) for reducing potential missing codes while
rejecting common mode noise.

Signature errors are also reduced by careful layout of the
analog circuitry. Every comparator also has a clock buffer
to reduce differential delays and to improve signal-to­noise ratio. The output drive capability of the device can
provide full ECL swings into 50 Ω loads.

TYPICAL INTERFACE CIRCUIT

The typical interface circuit is shown in figure 1. The
SPT7725 is relatively easy to apply depending on the
accuracy needed in the intended application. Wire-wrap
may be employed with careful point-to-point ground con­nections if desired, but to achieve the best operation, a

SPT7725

5 8/17/01

Figure 2 – Typical Interface Circuit 2 (PGA and Cerquad packages only)

*See below

Typical Voltage Limiter

R

S

D1

49.9

5.2

U1 and U2=
Rail-to-Rail Op Amp

D1=HP, 1N5712

Q1=1N2222A

Q2=1N2907A

R = 1 kW, .1%

+

U1



R

T

D2

Voltage
Limiter

V

REF

2 V

V

Analog

CC

Input

Force

2.2 µF

10-25 W

10-25 W

10-25 W

(Analog)

V

50 W

2 V

22

.01 µF

EE

.01 µF

Q1

V

RTS

V

.01 µF

V

.01 µF

V

.01 µF

V

V

CLK

CLK

50 W

10 W

R3

R2

R1

RBF

RBS

Analog Input

(Sense)

.01 µF

D1

V

RTF

V

IN

Preamp Comparator

256

192

191

151

128

127

64

63

2

1

2

V

IN

V

CC

+

U1



V

EE

R

+

U2



R

+

U2



R

+

U2



R

22 W

+

U2



V

.01 µF

EE

2.2 µF

100116Convert

V

Clock
Buffer

2.2 µF

.01 µF

AGND

.01 µF

EEAGNDDGND

5.2 V

256 to

8-Bit

Encoder

V

EE AGND

.01 µF

5.2 V

V

EE

L

LINV MINV

ECL

Latches

And

Buffers

Overrange
D8

MSB
D7

D6

D5

D4

D3

D2

D1

LSB
D0

DRINV

DREAD

50 W

2 V

2 V (Digital)

50 W

.01 µF

double-sided PC board with a ground plane on the compo­nent side separated into digital and analog sections will
give the best performance. The conv erter is bonded-out to
place the digital pins on the left side of the package and
the analog pins on the right side. Additionally, an RF bead
connection through a single point from the analog to digi­tal ground planes will reduce ground noise pickup .

The circuit in figure 2 (PGA and cerquad packages only) is
intended to show the most elaborate method of achieving
the least error by correcting for integral nonlinearity, input
induced distortion, and power supply/ground noise. This is
achieved by the use of external reference ladder tap con­nections, an input buff er, and supply decoupling. The func­tion of each pin and external connections to other compo­nents is as follows:

VEE, AGND, DGND

VEE is the supply pin with AGND as ground f or the de vice.
The power supply pins should be bypassed as close to the
device as possible with at least a .01 µF ceramic capaci­tor. A 1 µF tantalum should also be used f or low frequency
suppression. DGND is the g round for the ECL outputs and
is to be referenced to the output pulldown voltage and
appropriately bypassed as shown in figure 1.

VIN (ANALOG INPUT)

There are two analog input pins that are tied to the same
point internally . Either one may be used as an analog input

sense

and the other for input

force

. This is convenient for
testing the source signal to see if there is sufficient drive
capability . The pins can also be tied together and driven by

SPT7725

6 8/17/01

Table I – Output Coding

BINARY TWOs COMPLEMENT

TRUE INVERTED TRUE INVERTED

MINV=LINV=0 MINV=LINV=1 MINV=1; LINV=0 MINV=0; LINV=1

ANALOG INPUT VOLTAGE D8 D7_____D0 D7_____D0 D7_____D0 D7_____D0

–2 V + 1/2 LSB 0 00000000 11111111 10000000 01111111

00000001 11111110 10000001 01111110

–1.0 V 0 01111111 10000000 11111111 00000000

10000000 01111111 00000000 11111111

0 V – 1/2 LSB 0 11111111 00000000 01111111 10000000

11111110 00000001 01111110 10000001

≥0 V 1 11111111 00000000 01111111 10000000

the same source. The SPT7725 is superior to similar de­vices, due to a preamplifier stage before the comparators .
This makes the device easier to drive because it has con­stant capacitance and induces less slew rate distortion.
An optional input buffer may be used.

CLK, CLK (CLOCK INPUTS)

The clock inputs are designed to be driven differentially
with ECL levels. The clock may be driven single-ended
since CLK is internally biased to –1.3 V. (See clock input
circuit.) CLK ma y be left open, but a .01 µF b ypass capaci­tor from CLK to AGND is recommended. NOTE: System
performance may be degraded due to increased clock
noise or jitter.

MINV, LINV (OUTPUT LOGIC CONTROL)

These are ECL-compatible digital controls for changing
the output code from straight binary to two’s complement,
etc. For more information, see table I. Both MINV and
LINV are in the logic low (0) state when they are left open.
The high state can be obtained by tying to AGND through
a diode or 3.9 kΩ resistor.

D0 TO D7 (DIGITAL OUTPUTS)

The digital outputs can drive ECL levels into 50 Ω when
pulled down to –2 V. When pulled down to –5.2 V, the out­puts can drive 150 Ω to 1 kΩ loads.

V

RBF

, VR2, V

(REFERENCE INPUTS)

RTF

There are two reference inputs and one e xternal reference
voltage tap. These are –2 V (V
AGND (V

). The reference pins can be driven as shown

RTF

), mid-tap (VR2), and

RBF

in figure 1. VR2 should be bypassed to AGND for further
noise suppression.

V

, V

RBF

INPUTS

, VR1, VR2, VR3, V

RBS

(PGA AND CERQUAD PACKAGES ONLY)

RTF

, V

REFERENCE

RTS

These are five external reference voltage taps from –2 V
(V

) to AGND (V

RBF

) that can be used to control integral

RTF

linearity over temperature. The taps can be driven by op
amps as shown in figure 2. These voltage level inputs can
be bypassed to AGND for further noise suppression if so
desired. VRB and V

have force and sense pins for moni-

RT

toring the top and bottom voltage references.

N/C

All

Not Connected

pins should be tied to DGND on the left
side of the package and to AGND on the right side of the
package.

DREAD – DATA READY; DRINV – DATA READY
INVERSE

(PGA AND CERQUAD PACKAGES ONLY)

The data ready pin is a flag that goes high or low at the
output when data is valid or ready to be received. It is es­sentially a delay line that accounts for the time neces­sary for information to be clocked through the SPT7725’s
decoders and latches. This function is useful for interfac­ing with high-speed memory. Using the data ready output
to latch the output data ensures minimum set-up and hold
times. DRINV is a data ready in v erse control pin. (See the
timing diagram.)

D8 – OVERRANGE

(PGA AND CERQUAD PACKAGES

ONLY)

This is an overrange function. When the SPT7725 is in an
overrange condition, D8 goes high and all data outputs go
high as well. This makes it possible to include the
SPT7725 into higher resolution systems.

SPT7725

7 8/17/01

OPERATION

The SPT7725 has 256 preamp/comparator pairs that are
each supplied with the voltage from V
equally by the resistive ladder as shown in the block dia­gram. This voltage is applied to the positive input of each
preamplifier/comparator pair. An analog input voltage ap­plied at VIN is connected to the negative inputs of each
preamplifier/comparator pair. The comparators are then
clocked through each comparator’s individual clock buffer .
When CLK pin is in the low state, the master or input stage
of the comparators compares the analog input voltage to
the respective reference voltage. When CLK changes
from low to high, the comparators are latched to the state
prior to the clock transition and output logic codes in

Figure 3 – Timing Diagram

RTF

to V

RBF

divided

sequence from the top comparators, closest to V

RTF

(0 V),
down to the point where the magnitude of the input signal
changes sign (thermometer code). The output of each
comparator is then registered into four 64-to-6 bit decod­ers when CLK is changed from high to low.

At the output of the decoders is a set of four 7-bit latches
that are enabled (

track

) when CLK changes from high to
low. From here, the outputs of the latches are coded into
6 LSBs from 4 columns, and 4 columns are coded into
2 MSBs. Next are the MINV and LINV controls for output
inversions, which consist of a set of eight XOR gates.
Finally , 8 ECL output latches and b uff ers are used to drive
the external loads. The conversion takes one clock cycle
from the input to the data outputs.

Analog Input

Comparator Output

6 Bit Latch Output

8 Bit Latch Output

Clock

Master

Slave

CLK
CLK

N

V

IN

t

PW1

t

PW0

N+1

N+2

Internal Timing

Data Output D0D7

Overrange D8

Data Ready

t

D

Timing for PGA and Cerquad Packages Only

8 8/17/01

N+1NN1

SPT7725

Figure 4 – Subcircuit Schematics

Input Circuit

AGND

V

IN

V

EE

Figure 5 – Clock Input

MINV, LINV Input CircuitOutput Circuit

AGND

V

R

DGND

Data Out

MINV

LINV

10 kW

16 kW

1.3 V

AGND

V

EE

Figure 6 – Burn-In Circuit (42-lead DIP Package only)

V

AGND

EE

1N4736

V

REF

R4

R4

2.0 V

CLK

13 kW

1.3 V

CLK

13 kW

V

EE

EVALUATION BOARDS

The EB7725 evaluation board is av ailable to aid designers
in demonstrating the full performance of the SPT7725.
This board includes a voltage reference circuit, clock
driver circuit, output data latches, and an on-board recon­struction of the digital data. An application note describing
the operation of this board, as well as application tips, is
also available. Contact the factory for price and deliver y.

V

IN

CLK

CLK

R

= 50 W 1/4 Watt CC 5%

1

R

= 1 kW 1/4 Watt CC 5%

2

= 6.5 W 1/4 Watt CC 5%

R

3

= 6.5 W 1/2 Watt CC 5%

R

4

V

REF

V

EE

R2

R2

R2

= 2.0 Volts

= 6.6 Volts

V

CLK

CLK

R3

DGND

AGND

V

RTF

EE

V

MINV

RBF

V

IN

R1 R1 R1 R1 R1 R1 R1R1

D0

D1

D2

D3

D4

D5

D6

D7

LINV

R2

2.0 V

SPT7725

9 8/17/01

PACKAGE OUTLINES

42-Lead Sidebrazed DIP

42

INCHES MILLIMETERS

SYMBOL MIN MAX MIN MAX

A 0.081 0.099 2.06 2.51

1

G

A

B

C

H

D

E

F

B 0.016 0.020 0.41 0.51
C 0.095 0.105 2.41 2.67
D .050 typ 1.27
E .050 typ 1.27
F 0.275 6.99
G 2.080 2.120 52.83 53.85
H 0.585 0.605 14.86 15.37

I 0.008 0.015 0.20 0.38

J 0.600 0.620 15.24 15.75

I

J

46-Lead Pin Grid Array

D

SYMBOL MIN MAX MIN MAX

A

B

Pin 1

E

A 0.890 0.910 22.61 23.11
B 0.100 typ 2.54 typ
C .045 dia .055 dia 1.14 1.40
D 0.084 0.096 2.13 2.44
E 0.169 0.193 4.29 4.90
F .020 dia .030 dia 0.51 0.76
G .050 typ 1.27 typ

INCHES MILLIMETERS

Stand-off Pin

F

C Diameter

G

SPT7725

10 8/17/01

44-Lead Cerquad

INCHES MILLIMETERS

SYMBOL MIN MAX MIN MAX

C

A

D

A
B

B

A 0.550 typ 13.97 typ
B 0.685 0.709 17.40 18.00
C 0.037 0.041 0.94 1.04
D 0.016 typ 0.41 typ
E 0.008 typ 0.20 typ
F 0.027 0.051 0.69 1.30
G 0.006 typ 0.15 typ
H 0.080 0.089 2.03 2.26

05°

H

E

F

G

SPT7725

11 8/17/01

A

A
A

42

PIN ASSIGNMENTS PIN FUNCTIONS

123456789

D8

D5 D4 D3 D2 D1 D0 DGND

D6

AGND D7 AGNDDREAD

VEEDGND N/C V

MINV LINV DRINV

CLK

V

EE

AGND AGND V

V

RBS

V

RBF

N/C AGND V

DGND

GND

V

EE

MINV

CLK
CLK

V

EE

GND
GND
V

RBS

V

RBF

Bottom

CLK VEEAGND

V

EE

V

R1

1

2

3

4

5

6

7

8

9

10

11

View
PGA

AGND VR2AGND VINAGND N/C

IN

D8

D7

D6

44

43

42

D1

D4

D3

D2

D5

38

41

37

40

39

Cerquad

18

15

12

13

14

R1

EE

V

V

AGND

19

16

17

IN

R2

V

V

V

AGND

AGND

AGND

RTS

N/C

V

V

V

R3

D0

DGND

DREADY

35

34

36

21

22

20

IN

R3

V

AGND

RTF

EE

V

1

V

EE

2

N/C

3

LINV

A

4

V

EE

5

AGND

B

6

DGND

C

7

EE

EE

D0 (LSB)

8

D

D1

9

D2

E

10

D3

F

11

D4

12

D5

G

13

D6

H

14

D7 (MSB)

15

DGND

J

16

AGND

17

V

EE

18

MINV

19

N/C

20

CLK

21

CLK

33

AGND

32

V

EE

LINV

31

30

N/C

29

DRINV
N/C

28

V

27

EE

26

AGND

25

AGND
V

24

RTS

23

V

RTF

DIP

V

AGND

AGND

AGND

AGND

V

N/C

41

RTF

Name Function

40

N/C

V

39

EE

LINV D0 through D6 Output Inversion Control Pin

V

EE

38

V

N/C

N/C

V

V

R2

V

IN

N/C

N/C

V

EE

V

EE

N/C

RBF

N/C

EE

37

36

DGND Digital Ground

35

D0 Digital Data Output (LSB)

34

IN

D1–D6 Digital Data Output

33

32

D7 Digital Data Output (MSB)

31

MINV D7 Output Inversion Control Pin

30

29

CLK Inverse ECL Clock Input Pin

28

CLK ECL Clock Input Pin

27

26

AGND Analog Ground

25

V

IN

24

23

22

V

R2

V

RTF

V

RBF

Negative Analog Supply Nominally –5.2 V

Analog Input; Can be Connected to the
Input Signal or Used as a Sense

Reference Voltage Tap 2 (–1.0 V typ)
Reference Voltage Top
Reference Voltage Bottom

The following pins are on PGA and cerquad packages only.
DRINV Data Ready Inverse
DREAD Data Ready Output
Overrange Overrange Output D8
V
V
V
V

R1
R3
RTS
RBS

Reference Voltage Tap 1 (–1.5 V typ)
Reference Voltage Tap 3 (–0.5 V typ)
Reference Voltage Top, Sense
Reference Voltage Bottom, Sense

ORDERING INFORMATION

PART NUMBER LINEARITY TEMPERATURE RANGE PACKAGE TYPE

SPT7725AIJ 0.75 LSB –25 to +85 °C 42L Ceramic S/B
SPT7725BIJ 0.95 LSB –25 to +85 °C 42L Ceramic S/B
SPT7725AIG 0.75 LSB –25 to +85 °C 46L PGA
SPT7725BIG 0.95 LSB –25 to +85 °C 46L PGA
SPT7725AIQ 0.75 LSB –25 to +85 °C 44L Cerquad
SPT7725BIQ 0.95 LSB –25 to +85 °C 44L Cerquad
SPT7725BCU 0.95 LSB +25 °CDie*

*Please see the die specification for guaranteed electrical performance.

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO
IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR
USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR
THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with
instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.

www.fairchildsemi.com © Copyright 2002 Fairchild Semiconductor Corporation

2. A critical component is any component of a life support device or
system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or
effectiveness.

SPT7725

12 8/17/01