Datasheet SPT7722SIT Datasheet (SPT)

FEATURES

SPT7722

8-BIT, 250 MSPS ADC WITH DEMUXED OUTPUTS

PRELIMINARY INFORMATION

JULY 23, 2001

APPLICATIONS

• High conversion rate: 250 MSPS

• Single +5 V pow er supply

• Very low power dissipation: 450 mW

• 350 MHz full power bandwidth

• Po wer-down mode

• +3.0 V/+5.0 V (LVCMOS) digital output logic
compatibility

• Demuxed output ports

GENERAL DESCRIPTION

The SPT7722 is a high-speed, 8-bit analog-to-digital con­verter implemented in an advanced BiCMOS process. It is
a performance-enhanced version of the SPT7721, offer­ing better linearity and dynamic performance with slightly
higher power . An adv anced folding and interpolating archi­tecture provides both a high conversion r ate and very low
power dissipation of only 450 mW. The analog inputs can
be operated in either single-ended or differential input
mode. A 2.5 V common mode reference is provided on

BLOCK DIAGRAM

AGND DGND

AV

• RGB video processing

• Digital communications

• High-speed instrumentation

• Digital sampling oscilloscopes (DSO)

• Projection display systems

chip for the single-ended input mode to minimize e xternal
components.

The SPT7722 digital outputs are demuxed (double-wide)
with both dual-channel and single-channel selectable out­put modes. Demuxed mode supports either parallel
aligned or interleaved data output. The output logic is both
+3.0 V and +5.0 V compatible. The SPT7722 is av ailable in
a 44-lead TQFP surf ace mount package ov er the industrial
temperature range of –40 to +85 °C.

CC

OV

DD

DA0DA

V

+

IN

8-Bit

7

250 MSPS

VIN

Common Mode

Voltage

Reference

+2.5 V

V

CM

PD CLK

ADC

CLK CLK

CLK

Data Output Latches

Data Output

Mode Control

22

Reset

DMODE

&

Reset

1,2

DB0DB

DCLK

OUT

DCLK

OUT

7

Signal Processing Technologies, Inc.

4755 Forge Road, Colorado Springs, Colorado 80907, USA

Phone: [phone] Fax: [phone] Web Site: http://www .spt.com e-mail: [e-mail]

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C

Supply V oltages

AVCC...................................................................... +6 V

OVDD..................................................................... +6 V

Input V oltages

Analog Inputs ............................... –0.5 V to VCC +0.5 V

Digital Inputs ................................ –0.5 V to V

+0.5 V

CC

T emperatures

Operating Temperature........................... –40 to +85 °C

Storage Temperature ............................ –65 to +125 °C

Note: 1. Operation at any Absolute Maximum Rating is not implied.

See Electrical Specifications for nominal applied conditions in
typical applications.

ELECTRICAL SPECIFICATIONS

TA = T

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS
Resolution 8 Bits
DC Performance ƒIN=1 kHz

Analog Input

to T

, AV

MIN

MAX

= +5.0 V, OV

CC

= +5.0 V, ƒ

DD

= 250 MHz, unless otherwise specified.

CLK

TEST TEST SPT7722

Differential Linearity +25 °C I –0.6 ±0.4 +0.6 LSB

–40 °C to +85 °C V ±0.9 LSB

Integral Linearity +25 °C I –1.5 ±1.2 +1.5 LSB

Best Fit –40 °C to +85 °C V ±1.7 LSB

No Missing Codes @250 MSPS V Guaranteed

Input V oltage Range

(with respect to V

–) V ±512 mV

IN

Input Common Mode Voltage V 2.5 V
Input Bias Current V 5 µA
Input Resistance +25 °C V 50 kΩ
Input Capacitance +25 °C V 5 pF
Input Bandwidth +25 °C (–3 dB of FS) V 350 MHz
Gain Error V ±5 %
Offset Error V ±10 mV

P-P

Timing Characteristics

Conversion Rate V 250 MSPS
Output Delay (t

) +25 °C V 8 ns

pd1

Output Delay Tempco V 21 ps/°C
Aperture Delay Time (t

) V 0.5 ns

ap

Aperture Jitter Time V 2 ps rms
Pipeline Delay (Latency)

Single Channel Mode V 2.5 Clocks
Demuxed Interleaved Mode V 2.5 Clocks
Demuxed Parallel Mode

Channel B V 2.5 Clocks
Channel A V 3.5 Clocks

CLK to DCLK

Single Channel Mode (t
Dual Channel Mode (t

Delay Time

OUT

)V6ns

pd2

)V6ns

pd3

Dynamic Performance

Effective Number of Bits (ENOB)

= 70 MHz +25 °C I 6.3 7.0 Bits

ƒ

IN

= 70 MHz –40 °C to +85 °C V 5.9 Bits

ƒ

IN

Signal-to-Noise Ratio (SNR)

= 70 MHz +25 °C I 44 46 dB

ƒ

IN

ƒIN = 70 MHz –40 °C to +85 °C V 39 dB

SPT

SPT7722

2 7/23/01

ELECTRICAL SPECIFICATIONS

TA = T

MIN

to T

MAX

, AV

= +5.0 V, OVDD = +5.0 V, ƒ

CC

= 250 MHz, unless otherwise specified.

CLK

TEST TEST SPT7722

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS
Dynamic Performance

Total Harmonic Distortion (THD)

= 70 MHz +25 °C I –47 –43 dB

ƒ

IN

= 70 MHz –40 °C to +85 °C V –45 dB

ƒ

IN

Signal-to-Noise and Distortion (SINAD)

= 70 MHz +25 °C I 41 43 dB

ƒ

IN

= 70 MHz –40 °C to +85 °C V 41 dB

ƒ

IN

Power Supply Requirements

Voltage (Analog Supply) V 4.75 5.0 5.25 V

AV

CC

OVDD Voltage (Digital Supply) V 2.75 5.25 V

Current V 90 110 mA

AV

CC

Current Powerdown V 2.7 5 mA

AV

CC

Power Dissipation with Internal Voltage Reference V 450 5 50 mW
Power Supply Rejection Ratio V 35 mV/V

Common Mode Reference Output

Voltage V 2.45 2.5 2.55 V
Voltage Tempco V 119 ppm/°C
Output Impedance V 1 kΩ
Current Capability V 50 µA
Power Supply Rejection Ratio V 34 mV/V

Clock and Reset Inputs (Differential and Single-Ended)

Differential Signal Amplitude V
Differential High Input Voltage V
Differential Low Input Voltage V

DIFF

IHD

ILD

Differential Common-Mode Input V
Single-Ended High Input Voltage V
Single-Ended Low Input Voltage V
High Current Level V
Low Current Level V

<2.5 V V –100 20 +100 µA

ID

ID

CMD

IH

IL

V 400 mV
V 1.7 AV
V0 AV

CC

CC

–0.4 V

V

V 1.5 V
V 1.8 V
V 0 1.2 V

V –100 20 +100 µA

P-P

Power Down and Mode Control Inputs (Single-Ended)

High Input Voltage V 2 .0 AV

CC

V
Low Input Voltage V 0 1.0 V
Maximum Input Current Low V –100 10 +100 µA
Maximum Input Current High <4.0 V V –100 10 +100 µA

Digital Outputs

Logic "1" Voltage (I
Logic "0" Voltage (I

= –100 µA) V OVDD – 0.2 V

OH

= +100 µA) V 0.2 V

OL

TR/TF Data (10 pF load) V 3 ns
TR/TF DCLK = (10 pF load) V 1.5 ns

TEST LEVEL CODES

All electrical characteristics are subject to the
following conditions:

All parameters having min/max specifications
are guaranteed. The Test Level column indi­cates the specific device testing actually per­formed during production and Quality Assur­ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.

LEVEL TEST PROCEDURE

I 100% production tested at the specified temperature.

II 100% production tested at TA = +25 °C, and sample tested at the

specified temperatures.
III QA sample tested only at the specified temperatures.
IV Parameter is guaranteed (but not tested) by design and characteri-

zation data.

V Parameter is a typical value for information purposes only.

VI 100% production tested at TA = +25 °C. Parameter is guaranteed

over specified temperature range.

SPT

3 7/23/01

SPT7722

THEORY OF OPERATION

The SPT7722 is a three-step subranger. It consists of two
THAs in series at the input, followed by three ADC b locks .
The first block is a three-bit folder with over/under range
detection. The second b lock consists of two single-bit f old­ing interpolator stages. There are pipelining THAs between
each ADC block.

The analog decode functions are the input buffer, input
THAs, three-bit folder , f olding interpolators, and pipelining
THAs. The input buffer enables the part to withstand rail­to-rail input signals without latchup or excessive currents
and also performs single-ended to differential conv ersion.
All of the THAs have the same basic architecture. Each
has a differential pair buffer followed by switched emitter
followers driving the hold capacitors. The input THA also
has hold mode feedthrough cancellation de vices.

The three MSBs of the ADC are generated in the first
three-bit folder block, the output of which driv es a differen­tial reference ladder which also sets the full-scale input
range. Differential pairs at the ladder taps generate
midscale, quarter and three-quarter scale , overr ange, and
underrange. Every other differential pair collector is cross­coupled to generate the eighth scale zero crossings. The
middle ADC block generates two bits from the folded sig­nals of the previous stages after pipeline THAs. Its outputs
drive more pipeline THAs to push the decoding of the three
LSBs to the next half clock cycle . The three LSBs are gen­erated in interpolators that are latched one full clock cycle
after the MSBs.

The digital decode consists of comparators, exclusive of
cells for gray to binary decoding, and/or cells used for
mostly over/under range logic. There is a total of 2.5 cloc k
cycles latency before the output bank selection. In order to
reduce sparkle codes and maintain sample rate, no more
than three bits at a time are decoded in any half clock
cycle.

The output data mode is controlled by the state of the
demux mode inputs. There are three output modes .

• All data on bank A with clock r ate limited to one-half
maximum

• Interleav ed mode with data alternately on banks A and
B on alternate clock cycles

• Parallel mode with bank A delayed one cycle to be
synchronous with bank B every other clock cycle

If necessary , the input clock is divided b y tw o. The divided
clock selects the correct output bank. The user can syn­chronize with the divided clock to select the desired output
bank via the differential RESET input.

The output logic family is L VCMOS with output VDD supply
adjustable from 2.75 volts to 5.25 v olts. There are also dif­ferential clock output pins that can be used to latch the
output data in single bank mode or to indicate the current
output bank in demux mode.

Finally , a pow er-down mode is availab le, which causes the
outputs to become tri-state, and overall power is reduced
to about 10 mW . There is a 2.5 V reference to supply com­mon mode for single-ended inputs that is not shut down in
power-down mode .

Figure 1 – Single Mode Timing Diagram

2.5 CLK Cycles of Latency

N+1

t

pd2

V

IN

CLK

/CLK

D0D7

(Port A)

DCLKOUT

/DCLKOUT

t

N

pd2

t

ap

NOTES

Typically:

= Aperture Delay = 0.5 ns

1) t

ap

2) t

= Clock to output delay = 8 ns

pd1

3) t

= CLK to DCLKout delay = 6 ns

pd2

4) DCLKout rate is same as the rate of CLK input

SPT

t

pd1

N+2

N1N2N3 N

4 7/23/01

N+3

N+4

N+1

N+5

N+2

SPT7722

Figure 2 – Dual Mode Timing Diagram

U6-Reset

Refer to AN7722

DCLKOUT

/DCLKOUT

U6-Reset

Refer to AN7722

Vin

/CLK

CLK

/Reset

Reset

Port A

Port B

Port A

Port B

Vin

/CLK

CLK

/Reset

Reset

tpd2

N-6

N-7

N-6

N-2

N-2

tap

tap

N-5

N-1

550ps

N-1

550ps

tpd3

2.5 CLK Cycles of Latency

N

550ps

treset

ts

tpd1

INTERLEAVED DATA OUTPUT

N-4

PARALLEL DATA OUTPUT

N-5

N-4

tpd2

N

550ps

treset

ts

tpd1

N+1

Invalid Data

N+2

N-2

N-2

2.5 CLK Cycles of Latency

N+1

N+2

tpd1

tpd1

N-1

N+3

N+3

N+4

tpd1

N+1

N

N-1Invalid Data

N

N+4

tpd1

Port A

Port B

Port A

Port B

/DCLKOUT
DCLKOUT

SPT

N-6

N-4

N-5

tpd2

N-6

N-5

Data Output Possibilities w/o Reset

INTERLEAVED DATA OUTPUT

Invalid Data

PARALLEL DATA OUTPUT

Invalid Data

tpd1

5 7/23/01

N-2

N-2

N-1

N+1

N

N-1

N

SPT7722

Figure 3 – Typical Interface Cir cuit

T1

A

IN

Mini-Circuit

T1-6T

.01

Mode

Select

OUT

1 (2)

CC

AV

DMode1

2 (2)

CC

AV

VCM

VIN+

50



V

IN

Reset
Diff In

Reset

DMode2

SPT7722

AGND1 (4)

AGND2 (2)

Reset

Clock

Diff In

CLK

DGND (3)

CLK

DA0DA

DCLK

DCLK

DB0DB

(3)

OV

OUT

OUT

DD

7

Interfacing

Logics

7

Notes:

1) FB = Ferrite bead. It must placed as close to the ADC as possible.

2) All inputs are internally biased:
a) DMode1 to GND through 100K

b) DMode2 to VCC through 50K
c) CLK, PD and Rest pins to GND through 100K
d) /CLK and /Reset pins to 1.5 V through 5K

+ and VIN to +2.5 V through 50K

e) V

IN

3) All 0.01microfarad capacitors are surface mount caps. They must be
placed as close to the respective pin as possible

Default = interleave dual

}

channel output

.01(2x)

TYPICAL INTERFACE CIRCUIT

V ery few e xternal components are required to achiev e the
stated device performance. Figure 3 shows the typical
interface requirements when using the SPT7722 in nor­mal circuit operation. The following sections provide de­scriptions of the major functions and outline performance
criteria to consider for achieving the optimal device
performance.

ANALOG INPUT

The input of the SPT7722 can be configured in various
ways depending on whether a single-ended or differential
input is desired.

The AC-coupled input is most conveniently implemented
using a transformer with a center-tapped secondary wind­ing. The center tap is connected to the VCM pin as shown in
figure 3. To obtain low distor tion, it is important that the
selected transformer does not exhibit core saturation at
the full-scale voltage. Proper termination of the input is im­portant for input signal purity. A small capacitor across the
input attenuates kickback noise from the internal track­and-hold.

Figure 4 illustrates a solution (based on operational ampli­fiers) that can be used if a DC-coupled single-ended input
is desired. It is v ery important to select op amps with a high
open-loop gain, a bandwidth high enough so as not to im­pair the performance of the ADC, low THD , and high SNR.

.01(3x)

+A5

.01(3x)

+

10

FB

+

10

+D3/5

+D3/5

Figure 4 – DC-Coupled Single-Ended to Differential

Conversion (power supplies and bypassing

are not shown)

V

CM

Input
Voltage
(±0.5 V)

R3

(R3)/2

R3



+

R

R2

R2

51 W

R

RR

R



+

+



51 W

15 pF

51 W

ADC

V

V

INPUT PROTECTION

All I/O pads are protected with an on-chip protection
circuit. This circuit provides ESD robustness and prevents
latchup under severe discharge conditions without
degrading analog transmission times.

POWER SUPPLIES AND GR OUNDING

The SPT7722 is operated from a single power supply in
the range of 4.75 to 5.25 volts. Normal operation is sug­gested to be 5.0 volts. All po wer supply pins should be b y­passed as close to the package as possible. The analog
and digital grounds should be connected together with a
ferrite bead as shown in the typical interface circuit and as
close to the ADC as possible.

+

IN



IN

SPT

SPT7722

6 7/23/01

POWER DOWN MODE

To save on power, the SPT7722 incorporates a power­down function. This function is controlled by the signal on
pin PD. When pin PD is set high, the SPT7722 enters the
power-down mode . All outputs are set to high impedance.
In the power-down mode the SPT7722 dissipates 10 mW
typically.

REFERENCES

To save on parts count, design time, and PC board real
estate, the SPT7722 utilizes an internal reference. Only
a 0.01 µF bypass capacitor is required to implement this
feature.

COMMON MODE VOLTAGE REFERENCE CIRCUIT

The SPT7722 has an on-board common-mode voltage
reference circuit (VCM). It is 2.5 v olts and is capable of driv­ing 50 µA loads typically. The circuit is commonly used to
drive the center tap of the RF transformer in fully differen­tial applications. For single-ended applications, this output
can be used to provide the level shifting required for the
single-to-differential conv erter conversion circuit.

CLOCK INPUT

mode is not demuxed and can support direct output at
speeds up to 125 MSPS. The output format is straight
binary (table I).

Table I – Output Data Format

Analog Input Output Code

+FS 1111 1111
+FS – 1/2 LSB 1111 111Ø
0 ØØØØ ØØØØ
–FS + 1/2 LSB 0000 000Ø
–FS 0000 0000

Ø indicates the flickering bit between logic 0 and 1

The data output mode is set using the DMODE1 and
DMODE2 inputs (pins 32 & 31 respectively). Table II
describes the mode switching options.

Table II – Output Data Modes

Output Mode DMODE1DMODE

Parallel Dual Channel Output 0 0
Interleaved Dual Channel Output 0 1
Single Channel Data Output

(Bank A only 125 MSPS max) 1 X

D7–D0

2

The clock input on the SPT7722 can be driven by either a
single-ended or double-ended clock circuit and can handle
TTL, PECL, and CMOS signals. When operating at high
sample rates it is important to keep the pulse width of the
clock signal as close to 50% as possible. For TTL/CMOS
single-ended clock inputs, the rise time of the signal also
becomes an important consideration.

DIGITAL OUTPUTS

The output circuitry of the SPT7722 has been designed to
be able to support three separate output modes. The
demuxed (double-wide) mode supports either parallel
aligned or interleaved data output. The single-channel

EVALUATION BOARD

The EB7721/22 evaluation board is available to aid
designers in demonstrating the full performance of the
SPT7722. This board includes a clock driver and reset
circuit, adjustable references and common mode, a
single-ended to differential input buff er and a single-ended
to differential transformer (1:1). An application note
(AN7721/22) describing the operation of this board, as
well as information on the testing of the SPT7722, is also
available. Contact the factory for price and availability of
the EB7721/22.

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SPT7722

7 7/23/01

PACKAGE OUTLINE

44-Lead TQFP

A
B

INCHES MILLIMETERS

SYMBOL MIN MAX MIN MAX

A 0.472 Typ 12.00 Typ

Pin 1

Index

B 0.394 Typ 10.00 Typ
C 0.394 Typ 10.00 Typ
D 0.472 Typ 12.00 Typ
E 0.031 Typ 0.80 Typ

C

D

F 0.012 0.018 0.300 0.45

G 0.053 0.057 1.35 1.45

H 0.002 0.006 0.05 0.15

I 0.018 0.030 0.450 0.750
J 0.039 Typ 1.00 Typ
K 0-7° 0-7°

E F

G

K

H

I

J

SPT

SPT7722

8 7/23/01

PIN ASSIGNMENTS

AV

CCAVCC

43

3

AGND

41

42

SPT7722

TOP VIEW

44L TQFP

DA2DA

1

DA

AGND

CLK

CLK

RESET
RESET

OV

DGND

7

(MSB)

DA
DA

PD

AGND

44

1
2
3
4
5
6

DD

6

5

7
8

9
10
11

1213141516

DA4DA

V

IN

+

40

DA

0

(LSB)

V

IN

39

171918

OV

DD

AGND

38

DGND

V

CM

37

DB

0

(LSB)

AV

AV

CC

CC

35

36

202221

DB

1DB2DB3

AGND

34

33
32
31
30
29
28
27
26
25
24
23

AGND
DMODE
DMODE
OV

DD

DGND
DCLK
DCLK

(MSB)

DB

7

DB

6

DB

5

DB

4

PIN FUNCTIONS

Pin Name Description

VIN+ Non-Inverted Analog Input; nominally 1 V

100k pullup to VCC and 100k pulldown to AGND,
internally

V

– Inverted Analog Input; nominally 1 V

IN

1

2

DA

–DA

0

pullup to V
internally

Data output; Bank A. 3 V / 5 V LVCMOS

7

compatible.

DB

OUT

OUT

0

DCLK

–DB

OUT

Data output; Bank B. 3 V / 5 V LVCMOS

7

compatible.
Non-Inverted data output clock. 3 V / 5 V

LVCMOS compatible.

DCLK

OUT

Inverted data output clock. 3 V / 5 V LVCMOS
compatible.

CLK Non-Inverted clock input pin; 100k pulldown to

AGND, internally

CLK Inverted clock input pin; 17.5k pullup to V

7.5k pulldown to AGND, internally

RESET RESET synchronizes the data sampling and data

output bank relationship when in Dual Channel
Mode (DMODE
internally

RESET Inverted RESET input pin; 17.5k pullup to V

and 7.5k pulldown to AGND, internally

DMODE

1,2

Internally:

100k pulldown to AGND on DMODE1
50k pullup to V

Data Output Mode pins:

DMODE
Channel Output
DMODE
Channel Output
DMODE
Data Output on Bank A (125 MSPS max)

PD Power Down pin; PD = 1 for power-down mode.

Outputs set to high impedance in power-down

mode; 100k pulldown to AGND, internally
V
AV
OV

CM

CC

DD

2.5 V Common Mode Voltage Reference Output

+5 V Analog Supply

+3 V / +5 V Digital Output Supply
AGND Analog Ground
DGND Digital Ground

and 100k pulldown to AGND,

CC

= 0); 100k pulldown to AGND,

1

on DMODE2

CC

= 0, DMODE2 = 0: Parallel Dual

1

= 0, DMODE2 = 1: Interleaved Dual

1

= 1, DMODE2 = X: Single Channel

1

P-P

P-P

; 100k

CC

;

and

CC

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE

SPT7722SIT –40 to +85 °C 44L TQFP

Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby
expressly granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited.

WARNING – LIFE SUPPORT APPLICATIONS POLICY – SPT products should not be used within Life Support Systems without the
specific written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can
be reasonably expected to result in significant personal injury or death.

Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to
device failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.

SPT7722

SPT

9 7/23/01