Page 1
SPT
SIGNAL PROCESSING TECHNOLOGIES
SPT5400
13-BIT, OCTAL VOLTAGE-OUTPUT DAC
WITH PARALLEL INTERFACE
FEATURES
• Full 13-bit performance without external adjustments
• Eight DACs in one package
• Buffered voltage outputs
• Guaranteed monotonic to 13 bits
• Unipolar or bipolar output swing to ±4.5 V
• Output settling time of 7 µs to ±1/2 LSB
• Double-buffered digital inputs
DESCRIPTION
The SPT5400 has eight 13-bit voltage output digital-toanalog converters on one chip. It operates from ±5 V
power supplies and has maximum voltage output swings
of up to ±4.5 V without the addition of external components. Novel circuit topology allows for a guaranteed
monotonicity of 13 bits without the need for additional
circuitry. The SPT5400 has four separate reference voltage inputs, one for each pair of DACs. Four separate
BLOCK DIAGRAM
V
DD
INPUT
LATCH A
INPUT
LATCH B
REFAB REFCD
DAC
LATCH A
DAC
LATCH B
APPLICATIONS
• Automatic test equipment
• Flat-panel displays
• Arbitrary function generators
• Instrumentation
• Process control
analog ground pins allow for separate offset voltages for
each DAC pair. Each DAC can be asynchronously loaded
through a common 13-bit bus into a double-buffered set
of latches. All logic inputs are TTL/CMOS compatible.
The SPT5400 is available in a 44-lead PLCC package
over the commercial temperature range of 0 °C to
+70 °C.
REFEF REFGH
DAC A
DAC B
–
+
–
+
V
A
OUT
AGNDAB
B
V
OUT
D12–D0
CS
WR
DATA BUS
INPUT
LATCH C
INPUT
LATCH D
INPUT
LATCH E
INPUT
LATCH F
INPUT
LATCH G
INPUT
LATCH H
A0–A2 LDAB
CONTROL
LOGIC
LATCH C
LATCH D
LATCH E
LATCH F
LATCH G
LATCH H
LDCD
LDEF
LDGH
DAC
DAC
DAC
DAC
DAC
DAC
CLR
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
–
+
–
+
–
+
–
+
–
+
–
+
V
SS
GND
C
V
OUT
AGNDCD
D
V
OUT
E
V
OUT
AGNDEF
F
V
OUT
G
V
OUT
AGNDGH
H
V
OUT
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: sales@spt.com
Page 2
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
VDD to GND............................................. –0.3 to +6 V
VSS to GND............................................. –6 to +0.3 V
AGNDxx..................... (GND – 0.3 V) to (VDD + 0.3 V)
Input Voltages
Digital Input Voltage to GND.. –0.3 V to (VDD + 0.3 V)
REFxx ..................(AGNDxx – 0.3 V) to (VDD + 0.3 V)
Maximum Current into REFxx Pin ................. ±10 mA
Note 1: Operation at any Absolute Maximum Rating is not implied. Operation beyond the ratings may cause damage to the
device. See Electrical Specifications for proper nominal applied conditions in typical applications.
Output
V
xx ...................................................... VDD to V
OUT
Temperature
Operating Temperature, Ambient..............0 to +70 °C
Junction Temperature ....................................+165 °C
Lead Temperature, (soldering 10 seconds) ...+300 °C
Storage Temperature ..........................–65 to +150 °C
Power Dissipation ....................................... 1000 mW
ELECTRICAL SPECIFICATIONS
VDD = +5 V, VSS = –5 V, REFxx = 4.096 V, AGNDxx = GND = 0 V, RL = 10 kΩ, CL = 50 pF, TA = T
specified. Typical values are at TA = +25 °C.
TEST TEST SPT5400
PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS
DC Performance
Resolution 13 Bits
Integral Linearity VI ±0.5 ±4.0 LSB
Differential Linearity Guaranteed Monotonic VI ±1.0 LSB
Zero Code Error
Gain Error
Power Supply Rejection Ratio
∆Gain/∆V
∆Gain/∆V
1
2
3
DD
SS
Load Regulation R
= ∞ to 10 kΩ V ±0.4 LSB
L
VI ±10.0 ±20 LSB
VI ±1.0 ±15 LSB
VI ±0.0025 %/%
VI ±0.0025 %/%
Reference Input
Ref Input Range
4,5
Ref Input Resistance
5
IV AGND V
VI 5 kΩ
MIN
to T
, unless otherwise
MAX
DD
V
SS
Analog Output
Maximum Output Voltage V V
– 0.5 V
DD
Minimum Output Voltage V VSS + 0.5 V
Output Slew Rate V 2.4 V/µs
Output Settling Time
6
To ±1/2 LSB of Full Scale V 7.0 µs
Digital Feedthrough V 5 nV-s
Digital Crosstalk V 50 nV-s
Digital Inputs (VDD = 5 V ±5%)
Input Voltage High VI 2.4 V
Input Voltage Low VI 0.8 V
Input Current (V
= 0 V or VDD) VI 10.0 µA
IN
Input Capacitance IV 10 pF
Power Supplies
Positive Supply Range (V
Negative Supply Range (V
) VI 4.75 5.25 V
DD
) VI –5.25 –4.75 V
SS
Positive Supply Current VI 15 25 mA
Negative Supply Current VI 16 25 mA
Power Dissipation
1
Deviation of actual DAC output when all 0s are loaded to the DAC from the ideal output of –4.096 V.
2
Deviation of actual DAC output span from the ideal span of 8.191 V.
3
PSSR is tested by changing the respective supply voltage by ±5%.
4
For best performance, REF should be greater than AGND + 2 V and less than VDD – 0.6 V. The device operates
7
VI 155 250 mW
with reference inputs outside this range, but performance may degrade.
5
Reference input resistance is code dependent.
6
Typical settling time with 1000 pF capacitive load is 8 µs.
7
Does not include reference power.
SPT
2 5/15/00
SPT5400
Page 3
TEST LEVEL CODES
All electrical characteristics are subject
to the following conditions:
All parameters having min/max specifications are guaranteed. The Test Level
column indicates the specific device
testing actually performed during production and Quality Assurance inspection. Any blank section in the data
column indicates that the specification
is not tested at the specified condition.
Figure 1 – Timing Diagram
CS
TEST LEVEL TEST PROCEDURE
I 100% production tested at the specified temperature.
II 100% production tested at TA = +25 °C, and sample tested at the
specified temperatures.
III QA sample tested only at the specified temperatures.
IV Parameter is guaranteed (but not tested) by design and characteriza-
tion data.
V Parameter is a typical value for information purposes only.
VI 100% production tested at T
specified temperature range.
t
1
= +25 °C. Parameter is guaranteed over
A
t
5
t
WR
t
9
2
A0–A2
t
7
D0–D12
LD
Table I – Timing Parameters
PARAMETER SYMBOL MIN TYP MAX UNIT
CS Pulse Width Low t
WR Pulse Width Low t
LD Pulse Width Low t
CLR Pulse Width Low t
CS to WR Low t
CS High to WR High t
Data Valid to WR Setup t
Data Valid to WR Hold t
Address Valid to WR Setup t
Address Valid to WR Hold t
1
2
3
4
5
6
7
8
9
10
50 ns
50 ns
50 ns
100 ns
0ns
0ns
20 ns
0ns
10 ns
0ns
t
6
t
10
t
8
NOTES:
1. All input rise and fall times
are measured from 10% to
90% of +5 V. tR = tF = 5 ns.
2. If LD is activated while WR is
low, LD must stay low for t3 or
t
4
t
3
longer after WR goes high.
SPT
SPT5400
3 5/15/00
Page 4
GENERAL CIRCUIT DESCRIPTION
The SPT5400 contains eight 13-bit, voltage-output
DACs. It uses a novel circuit topology to convert the
13-bit digital inputs into equivalent output voltages that
are proportionate to the applied reference voltages. The
SPT5400 has four separate reference voltage (REFxx)
and analog ground (AGNDxx) inputs for each DAC pair.
The REFxx inputs allow for separate full-scale output
voltages for each DAC pair. The AGNDxx inputs allow for
separate offset voltages for each DAC pair.
Table II – DAC Addressing
A2 A1 A0 Function
0 0 0 DAC A input latch
0 0 1 DAC B input latch
0 1 0 DAC C input latch
0 1 1 DAC D input latch
1 0 0 DAC E input latch
1 0 1 DAC F input latch
1 1 0 DAC G input latch
1 1 1 DAC H input latch
VOLTAGE REFERENCE AND ANALOG
GROUND INPUTS
The REFxx and AGNDxx inputs set the output range of
the corresponding DAC pair. For a detailed description of
the relationship between the DAC output range and the
REFxx and AGNDxx input voltages, see the Analog Outputs section of this datasheet.
The reference input impedance is code dependent. It is at
its highest value when the input code of the corresponding DAC pair is all 1s. It is at its lowest value when the
input code is all 0s. Because the input impedance is code
dependent, load regulation of the reference is critical.
MULTIPLYING OPERATION
Because the reference of the SPT5400 accepts both AC
and DC signals, it can be used for multiplying applications. The REFxx inputs (which set the full-scale output
voltage for the respective DACs) only accept positive
voltages, so the multiplying operation is limited to two
quadrants. Note that when applying AC signals to the reference, do not bypass the inputs.
DIGITAL INPUTS AND
MICROPROCESSOR INTERFACE
All digital inputs are TTL/CMOS compatible. The
SPT5400 is compatible with microprocessors having a
minimum 13-bit-wide data bus. The microprocessor interface is double-buffered to allow all the DACs to be simultaneously updated.
The control inputs of the SPT5400 are level triggered,
and are shown in table III. The input latch is controlled by
CS and WR, and the transfer of data to the DAC latch is
controlled by LDxx. When CS and WR are low, the input
latch is transparent. When LDxx is low the DAC latch is
transparent. To avoid transferring data to the wrong DAC,
the address lines (A0–A2) must be valid through the time
CS and WR are low. See the timing diagram for specific
timing values. When CS and WR are high, the data is
latched into the input latch. When LDxx is high, the data is
latched into the DAC latch. If LDxx is low when CS and WR
are low, then it must be held low for t3 or longer after CS or
WR goes high.
When CLR is low, all DAC outputs are set to their corresponding AGNDxx. When CLR toggles from low to high,
1000hex is latched into all input and DAC latches.
Table III – Interface Truth Table
CLR LDxx WR CS Function
1 0 0 0 Both latches transparent
1 1 1 x Both latches latched
1 1 x 1 Both latches latched
1 x 0 0 Input latch transparent
1 x 1 x Input latch latched
1 x x 1 Input latch latched
1 0 x x DAC latch transparent
0 x x x All input and DAC latches at
1000hex, outputs at AGNDxx
DAC ADDRESSING AND LATCHING
Each DAC has an input latch that receives data from the
data bus, and a DAC latch that receives data from the
input latch. The address lines (A0–A2) for each DAC input latch are shown in table II. Data is transferred from
the input latch to the DAC latch when LDxx is asserted.
The analog output of each DAC reflects the data held in
its corresponding DAC latch. In addition to being latched,
data can be transferred to the DAC directly through
transparent latches.
SPT
DIGITAL CODE
The SPT5400 uses offset binary coding. Conversion to a
13-bit offset binary code from a 13-bit twos-complement
code can be achieved by adding 212 = 4096.
SPT5400
4 5/15/00
Page 5
POWER SUPPLY SEQUENCING
The required power-up sequence is as follows: VSS (or
VDD) first, VDD (or VSS) second, and then REF_. The
sequence in which VDD and VSS come up is not critical.
However, REF_ must come up after VDD and VSS are
established.
SPT strongly recommends that the digital input pins be
driven only after VDD and VSS are established. Driving a
digital input prior to establishing supplies will violate a
condition outlined in the Input Voltages section (see the
Absolute Maximum Ratings on page 2 of this data sheet)
and cause damage to the part. If either REF_ or the digital inputs must come up before VDD and VSS, due to system constraints, limit the current to the REF_ or digital
input pins to less than 1 mA.
This recommended power-up sequence must be
executed in reversed order for power-down. It should be
noted that none of the Absolute Maximum Rating conditions are violated during power-up and power-down.
Replacing VDAC in the equation gives the output
voltage.
D
REFxx REFxx REFxx
V
xx=2
OUT
()
13 12
2
−= −
1 LSB = REFxx
D
REFxx
=−
11
2
1
4096
4096
D
D ranges from 0 to 8191 (213 –1).
Table IV – Input Code/Output Tables
Bipolar (AGNDxx = 0 V)
Input Output
1 1111 1111 1111 +REFxx (4095/4096)
1 0000 0000 0001 +REFxx (1/4096)
1 0000 0000 0000 0 V
0 1111 1111 1111 –REFxx (1/4096)
0 0000 0000 0001 –REFxx (4095/4096)
0 0000 0000 0000 –REFxx
ANALOG OUTPUTS
The voltage outputs to the SPT5400 are buffered internally by precision amplifiers with a 2.4 V/µs typical slew
rate. The typical settling time to ±1/2 LSB, with a fullscale transition at the outputs, is 7 µs. Each DAC output
is protected against a short to GND or AGNDxx. The typical short-circuit currents are 25 mA when the DAC is
at positive full scale, and 2.5 mA when the DAC is at
negative full scale.
BIPOLAR OUTPUT VOLTAGE RANGE
(AGNDxx = 0 V)
For symmetrical bipolar operation, AGNDxx should be
tied to the system ground. The relationship between the
output voltage and the digital code is shown in table IV.
The output voltage of the DAC ladder (VDAC) is multiplied by 2 and level-shifted by the reference voltage. The
output voltage of the amplifier is given by the following
equation:
V
= 2(VDAC) – REFxx
OUT
Where VDAC is the voltage at the noninverting input of
the amplifier and REFxx is the voltage at the reference
input of the DAC.
With AGNDxx connected to the system ground, the output voltage of the DAC ladder is:
VDAC = (D/2
Where D is the numeric value of the DAC’s binary input
code.
13)
REFxx
Positive Unipolar (AGNDxx = REFxx/2)
Input Output
1 1111 1111 1111 +REFxx (8191/8192)
1 0000 0000 0000 +REFxx/2
0 0000 0000 0000 0 V
POSITIVE UNIPOLAR OUTPUT VOLTAGE RANGE
(AGNDxx = REFxx/2)
For positive unipolar operation, AGNDxx should be set to
REFxx/2. The relationship between the output voltage
and the digital code is shown in table IV . For example, if a
4.096 V reference is used, AGNDxx should be offset by
2.048 V. This results in a unipolar output voltage of 0 to
4.0955 V, where 1 LSB = 500 µV. the maximum current
out of any AGNDxx pin is:
I
AGNDXX
REFxx AGNDxx
=
−
5 k
Ω
CUSTOM OUTPUT VOLTAGE RANGE
If the voltage at the REFxx input is higher than the voltage at the AGNDxx input, the AGNDxx inputs can be offset by any voltage within the supply rails. One way to
achieve this is to add positive offset to AGNDxx by selecting the reference voltage and the voltage at AGNDxx
such that the resulting output voltages do not come within
±0.5 V of the supply rails. Another way is to digitally of fset
AGNDxx by connecting one DAC output to one or more
AGNDxx inputs. Note that a DAC output should not be
connected to its own AGNDxx input.
SPT
SPT5400
5 5/15/00
Page 6
The relationship between the reference, AGNDxx and
output voltage is shown in table V.
Table V – Relationship between Reference, AGNDxx and Output
POSITIVE
BIPOLAR OPERATION UNIPOLAR OPERATION
PARAMETER (AGNDxx = 0 V) (AGND = REFxx/2) CUSTOM OPERATION
Bipolar Zero Level or Unipolar Mid-Scale AGNDxx = 0 V AGNDxx = REFxx/2 AGNDxx
(Code = 1000000000000)
Differential Reference Voltage (VDR) REFxx REFxx/2 REF – AGNDxx
Negative Full-Scale Output (Code = All 0s) –REFxx 0 V AGNDxx – VDR
Positive Full-Scale Output (Code = All 1s) (4095/4096)(REFxx) (8191/8192)(REFxx) AGNDxx + (4095/4096)(VDR)
LSB Weight (REFxx/4096) (REFxx/8192) (VDR/4096)
xx as a Function of Digital Code ((D/4096)–1)(REFxx) (D/8192)(REFxx) AGNDxx + ((D/4096)–1)(VDR)
V
OUT
(D, 0 to 8191)
Figure 2 – Typical Interface Circuit (shown for unipolar operation)
FB
CMOS/TTL Data Source
C1
+A5 V
C1
-A5 V
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
V
DD
V
DD
V
SS
V
SS
GND
+
–
A0
CMOS/TTL Control Source
A2
A1
WR
SPT5400
REFxx
R
C2
CS
CLR
LDAB
LDED
LDEF
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
AGNDxx
C2
LDGH
A
B
C
D
E
F
G
H
C2
Notes
R = 22 Ω
C1 = 1.0 µF
C2 = 0.1 µF
REF = 0 – V
FB = Ferrite Bead
R
Analog Buffer
R
For Bipolar Operation
AGNDxx
R
–
+
DD
V
SPT
REF
+
1 kΩ 1 kΩ
SPT5400
6 5/15/00
Page 7
PACKAGE OUTLINE
44L PLCC
SYMBOL MIN MAX MIN MAX
A 0.5 typ 12.70 typ
B 0.650 0.655 16.51 16.64
C 0.685 0.695 17.40 17.65
D 0.165 0.180 4.19 4.57
E 0.100 0.110 2.54 2.79
F 0.020 0.51
G 0.05 typ 1.27 typ
H 0.026 0.032 0.66 0.81
I 0.013 0.021 0.33 0.53
J 0.590 0.630 14.99 16.00
K 0.145 0.156 3.68 3.96
L 0.009 0.011 0.23 0.28
K
L
INCHES MILLIMETERS
Pin 1
TOP
VIEW
A
B
C
B C
G
H
I
J
F
E
D
SPT
SPT5400
7 5/15/00
Page 8
PIN ASSIGNMENTS
AGNDCD
AGNDEF
CLR
441
Top View
D7
D8
D9
REFEF
SS
D6
D5
V
V
OUT
OUT
V
E
F
40
D4
39
29
D3
G
V
OUT
V
H
OUT
V
DD
REFGH
AGNDGH
GND
LDGH
LDEF
D0
D1
D2
V
OUT
V
OUT
V
DD
REFAB
AGNDAB
LDAB
LDCD
CS
WR
A2
A1
V
OUT
D
D12
V
SS
D11
REFCD
D10
V
OUT
C
6
B
7
A
17
18 28
A0
PIN FUNCTIONS
Name Function
CLR Clear input (active low). Driving this asynchronous
AGNDCD Analog ground for DAC C and DAC D.
REFCD Reference voltage input for DAC C and DAC C.
V
SS
V
OUT
V
OUT
V
OUT
V
OUT
input low sets the content of all latches to 1000hex.
All DAC outputs are reset to AGNDxx.
Bypass to AGNDCD with a 0.1 to 1 µF capacitor.
Negative power supply, –5 V (two pins). Connect
both pins to the supply voltage. Bypass each pin to
the system analog ground with a 0.1 µF capacitor.
D DAC D output voltage.
C DAC C output voltage.
B DAC B output voltage.
A DAC A output voltage.
Name Function
V
DD
Positive power supply, +5 V (two pins). Connect
both pins to the supply voltage. Bypass each pin to
the system analog ground with a 0.1 µF capacitor.
REFAB Reference voltage input for DAC A and DAC B.
Bypass to AGNDAB with a 0.1 to 1 µF capacitor.
AGNDAB Analog ground for DAC A and DAC B.
LDAB Load input (active low). Driving this asynchronous
input low transfers the contents of the input latches
A and B to the respective DAC latches.
LDCD Load input (active low). Driving this asynchronous
input low transfers the contents of the input latches
C and D to the respective DAC latches.
CS Chip select (active low).
WR Write input (active low). WR along with CS load data
into the DAC input latch selected by A0–A2.
A2 Address bit 2.
A1 Address bit 1.
A0 Address bit 0.
D12–D0 Data bits 12–0. (D0 = LSB)
LDEF Load input (active low). Driving this asynchronous
input low transfers the contents of the input latches
E and F to the respective DAC latches.
LDGH Load input (active low). Driving this asynchronous
input low transfers the contents of the input latches
G and H to the respective DAC latches.
GND Digital ground.
AGNDGH Analog ground for DAC G and DAC H.
REFGH Reference voltage input for DAC G and DAC H.
Bypass to AGNDGH with a 0.1 to 1 µF capacitor.
V
H DAC H output voltage.
OUT
V
G DAC G output voltage.
OUT
V
F DAC F output voltage.
OUT
V
E DAC E output voltage.
OUT
REFEF Reference voltage input for DAC E and DAC F.
Bypass to AGNDEF with a 0.1 to 1 µF capacitor.
AGNDEF Analog ground for DAC E and DAC F.
ORDERING INFORMATION
PART NUMBER TEMPERATURE RANGE PACKAGE
SPT5400SCP 0 to +70 °C 44L PLCC
Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby
expressly granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited.
WARNING – LIFE SUPPORT APPLICATIONS POLICY – SPT products should not be used within Life Support Systems without the
specific written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can
be reasonably expected to result in significant personal injury or death.
Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device
failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.
SPT
8 5/15/00
SPT5400
Loading...