Datasheet SPT5310SIN, SPT5310SIP Datasheet (SPT)

SPT5310

12-BIT, 250 MWPS ECL D/A CONVERTER

FEATURES

• 12-Bit, 250 MWPS Digital-to-Analog Converter

• ECL Compatibility

• Low Glitch Energy: 15 pV-s

• Low Power: 600 mW

• 40 MHz Multiplying Bandwidth

• Master-Slave Latches

• Industrial Temperature Range

GENERAL DESCRIPTION

The SPT5310 is a 12-bit, 250 MWPS digital-to-analog con­verter designed for direct digital synthesis, high resolution
imaging and arbitrary waveform generation applications. The
SPT5310 is an ECL-compatible device. It features a low glitch

BLOCK DIAGRAM

APPLICATIONS

• Fast Frequency Hopping Spread Spectrum Radios

• Direct Sequence Spread Spectrum Radios

• Microwave and Satellite Modems

• Test & Measurement Instrumentation

• Military Applications

impulse energy of 15 pV-s that results in excellent spurious
free dynamic range characteristics.

The SPT5310 is available in 28-lead plastic DIPs and 28-lead
PLCCs in the industrial temperature range (-40 to +85 °C).

R

Set

Control Amp In

Ref Out

Latch Enable

Digital
Inputs

D1

through

D12

+

Control

Amp

-

(MSB)

Decoders

and

Drivers

(LSB)

Internal
Voltage

Reference

Network

Latches

Switch

Control
Amp Out

Ref In

I

Out

I

Out

Signal Processing Technologies, Inc.

4755 Forge Road, Colorado Springs, Colorado 80907, USA

Phone: [phone] FAX: [phone]

ABSOLUTE MAXIMUM RATING (Beyond which damage may occur)

1

Supply Voltages

Negative Supply Voltage (VEE)................................ -7 V

A/D Ground Voltage Differential..............................0.5 V

Input Voltages

Digital Input Voltage (D1-D12, Latch Enable) .................

....................................................................... 0 V to V

Control Amp Input Voltage Range ................. 0 V to -4 V

Reference Input Voltage Range (V

)..... -3.7 V to V

REF

Output Currents

Temperature

Operating Temperature .............................-40 to + 85 °C

EE

Junction Temperature ........................................ + 150 °C

Lead, Soldering (10 seconds)............................ + 300 °C

EE

Storage ....................................................-65 to + 150 °C

Internal Reference Output Current.......................500 µA

Control Amplifier Output Current........................ ±2.5 mA

Note: 1. Operation at any Absolute Maximum Ratings is not implied. See Electrical Specifications for proper nominal applied

conditions in typical applications.

ELECTRICAL SPECIFICATIONS

TA = T

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS
DC Performance

- T

, V

1

= -5.2 V, R

EE

min

max

Resolution 12 Bits
Differential Linearity I ±1.0 ±1.25 LSB
Differential Linearity Max at Full Temp. VI ±2.0 LSB
Integral Linearity Best Fit I ±1.0 ±1.5 LSB
Integral Linearity Max at Full Temp. VI ±2.0 LSB
Output Capacitance +25 °C10pF
Gain Error

Gain Error Tempco Full Temp. V 150 PPM/°C
Zero-Scale Offset Error +25 °C I 0.5 2.5 µA

Offset Drift Coefficient Full Temp. V 0.01 µA/°C
Output Compliance Voltage +25 °C IV -1.2 +2.0 V
Equivalent Output Resistance +25 °C IV 0.8 1.0 1.2 kΩ

= 7.5 kΩ, Control Amp In = Ref Out, V

SET

TEST TEST SPT5310

+25 °C I 1.0 5.0 % FS
Full Temp. VI 8.0 % FS

Full Temp. VI 5.0 µA

= 0 V, unless otherwise specified.

OUT

Dynamic Performance

Conversion Rate +25 °C IV 250 MWPS
Settling Time t
Output Propagation Delay t
Glitch Energy
Full Scale Output Current

1

Gain is measured as a ratio of the full-scale current to I

2

Measured as voltage at mid-scale transition to ±0.024%; RL=50 Ω.

3

Measured from the rising edge of Latch Enable to where the output signal has left a 1 LSB error band.

4

Glitch is measured as the largest single transient.

5

Calculated using

6

SFDR is defined as the difference in signal energy between the fundamental and worst case spurious frequencies in the output

2

ST

4

I

FS

D

5

=128 x

+25 °C V 13 ns

3

+25 °CV 1 ns
+25 °C V 15 pV-s
+25 °C V 20.48 mA

. The ratio is nominally 128.

SET

Control Amp In

R

SET

spectrum window, which is centered at the fundamental frequency and covers the indicated span.

SPT5310

SPT

2 4/1/97

ELECTRICAL SPECIFICATIONS

TA = T

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS

Dyanmic Performance

Power Supply Requirements

Voltage Input and Control

Digital Inputs

- T

, V

min

max

Spurious-Free Dynamic Range

5.055 MHz; 20 MWPS 2 MHz Span V 63 dBc

10.055 MHz; 40 MWPS 2 MHz Span V 58 dBc

20.055 MHz; 80 MWPS 2 MHz Span V 56 dBc

40.055 MHz; 160 MWPS 2 MHz Span V 54 dBc

60.055 MHz; 240 MWPS 2 MHz Span V 46 dBc

Rise Time / Fall Time RL = 50 Ω V2ns

Negative Supply Voltage IV -5.46 -5.2 -4.94 V
Negative Supply Current (-5.2 V) +25 °C I 115 140 mA

Nominal Power Dissipation V 600 mW
Power Supply Rejection Ratio ±5% of V

Reference Input Impedance +25 °CV 3kΩ
Ref. Multiplying Bandwidth +25 °C V 40 MHz
Internal Reference Voltage VI -1.15 -1.20 -1.25 V
Internal Reference Voltage Drift V 50 ppm/°C
Amplifier Input Impedance +25 °CV 3MΩ
Amplifier Input Bandwidth +25 °C V 1 MHz

Logic 1 Voltage Full Temp. VI -1.0 -0.8 V
Logic 0 Voltage Full Temp. VI -1.7 -1.5 V
Logic 1 Current Full Temp. VI 20 µA
Logic 0 Current Full Temp. VI 10 µA
Input Capacitance +25 °CV 3pF
Input Setup Time - t
Input Setup Time - t
Input Hold Time - t
Input Hold Time - t
Latch Pulse Width - t

= -5.2 V, R

EE

H
H

S
S

PWL, tPWH

= 7.5 kΩ, Control Amp In = Ref Out, V

SET

TEST TEST SPT5310

6

+25 °C

Full Temp VI 148 mA

EE

External Ref, +25 °C

+25 °CIV32ns
Full Temp. IV 3.5 ns
+25 °C IV 0.5 0 ns
Full Temp. IV 0.5 ns
+25 °C IV 4.0 3.3 ns

= 0 V, unless otherwise specified.

OUT

I 30 100 µA/V

TEST LEVEL CODES

All electrical characteristics are subject to the
following conditions: All parameters having min/
max specifications are guaranteed. The Test
Level column indicates the specific device test­ing actually performed during production and
Quality Assurance inspection. Any blank sec­tion in the data column indicates that the speci­fication is not tested at the specified condition.

SPT

TEST LEVEL

I

II

III
IV

V

VI

3 4/1/97

TEST PROCEDURE

100% production tested at the specified temperature.
100% production tested at TA=25 °C, and sample

tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design

and characterization data.
Parameter is a typical value for information purposes

only.
100% production tested at TA = 25 °C. Parameter is

guaranteed over specified temperature range.

SPT5310

THEORY OF OPERATION

The SPT5310 uses a segmented architecture incorporating
most significant bit (MSB) decoding. The four MSBs (D1-D4)
are decoded to thermometer code lines to drive 15 discrete
current sinks. For the eight least significant bits (LSBs), D5
and D6 are binary weighted and D7-D12 are applied to the
R-2R network. The 12-bit decoded data is input to internal
master/slave latches. The latched data is input to the switch­ing network and is presented on the output pins as comple­mentary current outputs.

TYPICAL INTERFACE CIRCUIT

The SPT5310 requires few external components to achieve
the stated operation and performance. Figure 2 shows the
typical interface requirements when using the SPT5310 in
normal circuit operation. The following sections provide de­scriptions of the pin functions and outlines critical perfor­mance criteria to consider for achieving optimal device per­formance.

Referring to figure 1, data is latched into the DAC on the rising
edge of the latch enable clock with the associated setup and
hold times. The output transition occurs after a typical 1 ns
propagation delay and settles to within ±1 LSB in typically
13 ns. Because of the SPT5310’s rising edge-triggering, no
timing changes are required when replacing an AD5310
operating in nontransparent mode.

VOLTAGE REFERENCE

When using the internal reference, Ref Out should be con­nected to Control Amp In and decoupled with a 0.1 µF
capacitor. Control Amp Out should be connected to Ref In
and decoupled to the analog supply. (See figure 2.)

Full-scale output current is determined by Control Amp In and
R

using the following formula:

Set

I

(FS) = (Control Amp In / R

Out

(Current out is a constant 128 factor of the
reference current)

Set

) x 128

POWER SUPPLIES AND GROUNDING

The SPT5310 requires the use of a single -5.2 V supply. All
supplies should be treated as analog supply sources. This
means the ground returns of the device should be connected
to the analog ground plane. All supply pins should be by­passed with .01 µF and 10 µF decoupling capacitors as close
to the device as possible.

The two grounds available on the SPT5310 are DGND and
AGND. These grounds are not tied together internal to the
device. The use of ground planes is recommended to achieve
the best performance of the SPT5310. All ground, reference
and analog output pins should be tied to directly to the DAC
ground plane. The DAC and system ground planes should be
separate from each other and only connected at a single point
through a ferrite bead to reduce ground noise pickup.

DIGITAL INPUTS AND TIMING

The SPT5310 uses single-ended, 10K ECL-compatible in­puts for data inputs D1-D12 and Latch Enable. It also em­ploys master/slave latches to simplify digital interface timing
requirements and reduce glitch energy by synchronizing the
current switches. This is an improvement over the AD5310,
which typically requires external latches for digital input
synchronization.

The internal reference is typically -1.20 V with a tolerance of
±0.05 V and a typical drift of 50 ppm/°C. If greater accuracy
or temperature stability is required, an external reference can
be utilized.

OUTPUTS

The output of the SPT5310 is comprised of complementary
current sinks, I
I

of the two is always equal to the full-scale output current
minus one LSB.

By terminating the output current through a resistive load to
ground, an associated voltage develops. The effective resis­tive load (R
parallel with the resistive load (RL). The voltage which devel­ops can be determined using the following formulas:

The resistive load of the SPT5310 can be modified to incor­porate a wide variety of signal levels. However, optimal
device performance is achieved when the outputs are equiva­lently loaded.

I

or

Out

Control Amp Out = -1.2 V, and R
I

Out

RL = 51 Ω
R

Out

R

Eff

V

Out

Out

are based upon the digital input code. The sum

Out

) is the output resistance of the device (R

Eff

(FS) = (-1.2 V / 7.5 kΩ) x 128 = -20.48 mA

= 1.0 kΩ

= 51 Ω || 1.0 kΩ = 48.52 Ω

= R

Eff

I

x I

and

Out

. The output current levels at either

Out

(FS) = 48.52 Ω x -20.48 mA

= -0.994 V

= 7.5 kΩ

Set

Out

) in

SPT

SPT5310

4 4/1/97

Figure 1 - Timing Diagram

Latch

Enable

-1.3 V

t

PWL

t

PWH

-1.3 V

OUT -

OUT +

Figure 2 - Typical Interface Circuit

-5.2 V

Digital Inputs

Clock
Input

System

GND

ECL Logic Drivers

t

S

10 µF

Data Inputs

23

N/C

28

D1 (MSB)

1

D2

2

D3

3

D4

4

D5

5

D6

6

D7

7

D8

8

D9

9

D10

10

D11

11

D12 (LSB)

26

LE

27 13 22

t

H

t

D

t

ST

1/2 LSB

0.1 µF

0.001 µF
15,2512,21

DV

EE

SPT5310

DGND AGND Ref GND

AV

EE

Ref In

Control

Amp Out

Ref Out

Control
Amp In

R

Set

I

Out

I

Out

0.1 µF

0.001 µF

17

18

20

19

24

R

Set

16

R

L

R

L

14

1 LSB

0.1 µF

20 Ω

0.1 µF

V

Out

SPT

SPT5310

5 4/1/97

PACKAGE OUTLINES

INCHES MILLIMETERS

SYMBOL MIN MAX MIN MAX

A 0.200 5.08

B 0.120 0.135 3.05 3.43
C 0.020 0.51
D 0.100 2.54

E 0.067 1.70

F 0.013 0.33
G 0.170 0.180 4.32 4.57
H 0.622 15.80

I 0.555 14.10
J 1.460 37.08

K 0.085 2.16

28L Plastic DIP

K

28

I

1

J

A

B

C

D

E

F

H

G

SPT

SPT5310

6 4/1/97

PACKAGE OUTLINES

28L PLCC

C

Pin 1

TOP

VIEW

A
B

H

G

I

F

E

D

INCHES MILLIMETERS

SYMBOL MIN MAX MIN MAX

A 0.450 0.456 11.43 11.58

B 0.485 0.495 12.32 12.57
C 45° 45°
D 0.165 0.175 4.19 4.45

E 0.010 0.25
F 0.022 typ .56 typ
G 0.18 typ 4.57 typ
H 0.05 typ 1.27 typ

I 0.039 0.430 0.99 10.92

Pin 1

BOTTOM

VIEW

SPT

SPT5310

7 4/1/97

PIN ASSIGNMENTS PIN FUNCTIONS

D2
D3
D4
D5
D6
D7
D8
D9

D10

D11

(LSB) D12

Digital V

EE

Analog Return

I

Out

5

D6

6

D7

7

D8

8

D9

D10

9

D11

10

(LSB) D12

11

1

2

3

4

5

6

7

8

9

10

11

12

13

14

D5

4

12

Digital V

28

PDIP

D1 (MSB)

27

DGND

26

Latch Enable
Analog V

25

R

24

Set

N/C

23

22

Ref GND
Digital V

21

20

Ref Out

19

Control Amp In

18

Control Amp Out

17

Ref In
I

16

Out

Analog V

15

EE

EE

EE

Name Function

Out+ Analog Current Output
Out- Complementary Analog Current Output
D1-D

12

Latch Enable Latch Control Line
Ref In Voltage Reference Input
Ref Out Internal Voltage Reference Output

Ref GND Ground Return For Internal Voltage

Control Amp In Normally Connected to Ref Out If Not

Control Amp Out Output of Internal Control Amplifier

1

R

Set

Digital Input Bits (D12 is the LSB)

Normally Connected to Control Amp In

Reference and Amplifier

Connected to External Reference

Normally Connected to Ref In
Connection for External Resistance
Reference When Using Internal Amplifier

Latch Enable

(MSB) D1

D4

D3

2

3

DGND

D2

26

27

28

1

Analog Return Analog Return Ground
Analog V
Digital V

EE

EE

Nominally 7.5 kΩ

Analog Negative Supply (-5.2 V)
Digital Negative Supply (-5.2 V)

DGND Digital Ground Return

25

Analog V

24

23

PLCC

17

16

15

14

13

Analog V

Ref In

Out

I

I

Out

Analog Return

22

21

20

19

18

Control Amp Out

EE

R

Set

N/C

Ref GND

Digital V

EE

Ref Out

Control Amp In

N/C Not Connected

1

Full-Scale Current Out=128 (Control Amp In/R

Set

)

EE

EE

ORDERING INFORMATION

PART NUMBER DNL/INL PACKAGE

SPT5310 SIN ±1.25/±1.5 28L PDIP
SPT5310 SIP ±1.25/±1.5 28L PLCC

Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby expressly
granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited.

WARNING - LIFE SUPPORT APPLICATIONS POLICY - SPT products should not be used within Life Support Systems without the specific
written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably
expected to result in significant personal injury or death.

Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device
failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.

SPT5310

SPT

8 4/1/97