Datasheet SPT5100SCT Datasheet (SPT)

SPT5100

8-BIT, 20 MWPS DUAL CHANNEL VIDEO DAC

Signal Processing Technologies, Inc.

4755 Forge Road, Colorado Springs, Colorado 80907, USA

Phone: [phone] FAX: [phone]

BLOCK DIAGRAM

FEATURES

• 8-Bit Dual Channel Video Digital-to-Analog Converter

• 20 MWPS Operation

• Low Power: 70 mW

• Internal Voltage Reference

• 5 V Monolithic CMOS

• 32-Lead QFP Package (7 mm by 7 mm, 0.8 mm Pitch)

APPLICATIONS

• High-speed Digital-to-Analog Conversion

• Y/ C, S-Video Processing

• Desktop Video Processing

• Digital TV

• Satellite TV Decoders

• Digital VCRs

current. The differential linearity errors of the DACs are
guaranteed to be a maximum of ±0.5 LSB over the full
temperature range. The device is available in a 32-lead QFP
package in the commercial temperature range.

GENERAL DESCRIPTION

The SPT5100 is an 8-bit, 20 MWPS, dual channel video digital­to-analog converter specifically designed for video process­ing applications including digital TV decoders and digital
VCRs. A single external resistor controls the full-scale output

Current

Swit ch Cell

Arr ay ( Ce ll 4)

V

CS

V

REF

C urr en t

Swit ch Cell

Arr ay ( Ce ll 4)

Current

Switch Cel l

Arr a y ( Cell 63)

Lat c h

Dec o der

Lat c h

Y

OU T

AV

DD

I

OY

(LSB) YØ

Y1

Y2

Y3

Y4

Y5

Y6

(MSB) Y7

CLKY

V

CS

V

REF

Current

Switch Cel l

Arr a y ( Cell 63)

Lat c h

Dec o der

Lat c h

C

OUT

AV

DD

I

OC

(LSB ) CØ

C1

C2

C3

C4

C5

C6

(MSB ) C7

CLKC

AV

SS

AV

SS

AV

DD

AV

DD

SPT

2 3/14/97

SPT5100

ELECTRICAL SPECIFICATIONS

f

CLK

= 20 MWPS, AVDD = 5.0 V, Output Pull-Up Load = 240 Ω, TA = 25 °C, AVSS = 0.0 V

TEST TEST

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS

DC ELECTRICAL CHARACTERISTICS

DC Performance

Resolution 8.0 Bits
Differential Linearity T

A

= T

MIN

to T

MAX

I ±0.25 ±0.5 LSB

Integral Linearity I ±0.5 ±1.0 LSB

Analog Outputs

Output Voltage Range VCS = +1.25 V I 4.0 5.0 V
Conversion Rate I 20 MWPS
Output Offset Voltage I 14 25 mV
Signal-to-Noise Ratio I 41 45 dB
Differential Phase V 1.2 Degrees
Differential Gain V 2 %
Glitch Energy V 80 pV-s
Settling Time I 31 26 ns
Propagation Delay (t

pd

) V 10 12 ns
Crosstalk I -47 dB
FS Control Voltage (VCS) IV 1.0 1.4 V

Digital Inputs and Timing

Input Current, Logic High VIH = 5 V I 5 µA

Logic Low V

IL

= 0 V I -5 µA

Set-Up Time, Data and Controls (t

S

)I5 ns

Hold Time, Data and Controls (t

h

) I 10 ns
Clock Pulse Width (Low) I 25 ns
Clock Pulse Width (High) I 25 ns

Power Supply Requirements

Supply Voltage I 4.75 5.25 V
Supply Current I 14 mA
Power Dissipation I 70 mW

ABSOLUTE MAXIMUM RATING (Beyond which damage may occur)

1

Supply Voltages

AV

DD

(measured to AVSS)........................... -0.3 to 7.0 V

Input Voltage

Clock and Data .........................................AVSS to AV

DD

Output Current

I

OUT

.............................................................................

0 to 8 mA

Temperature

Operating, ambient ........................................0 to +70 °C

Storage ....................................................-55 to + 125 °C

Note: 1. Operation at any Absolute Maximum Ratings is not implied. See Electrical Specifications for proper nominal applied

conditions in typical applications.

SPT

3 3/14/97

SPT5100

INTERFACE CONSIDERATIONS

Figure 1 shows a typical interface circuit of the SPT5100 in
normal circuit operation.

SUPPLY AND GROUND CONSIDERATIONS

SPT suggests that all power supply pins (AVDD) be tied
together and decoupled using a 0.1 µF ceramic capacitor in
parallel with a 10 µF tantalum capacitor.

INTERNAL REFERENCE VOLTAGE (V

REF

)

Voltage reference is internally generated. Connect a 0.1 µF
bypass capacitor as close to the pin as possible.

FULL-SCALE ADJUST CONTROL (VCS)

Connect a 0.1 µF bypass capacitor with the shortest possible
lead length between VCS and AVSS. A resistor connected
between this pin and AVDD controls the magnitude of the full­scale video signal.

The output voltage range of the SPT5100 can be kept
constant and stable by keeping the value of VCS to ground
constant. The full-scale voltage changes according to V

CS.

(See figure 2.)

CURRENT OUTPUTS

The Y channel and C channel current outputs should have a
load resistor connected to AVDD. The resistors are typically
240 Ω and should be kept in the 150 Ω to 250 Ω range.

LATCH-UP CONSIDERATIONS

In order to prevent a possible latch-up condition, SPT sug­gests that a 100 Ω resistor be placed in series with each clock
input pin.

Table I - Binary Codes

1 LSB = 3.91 mV, VCS = 1.25 V

Digital Input Analog

Step A7 A6 A5 A4 A3 A2 A1 A0 Out (V)

(MSB) (LSB)

0 000000004.0000
1 000000014.0039
2 000000104.0078
3 000000114.0117

. . .
. . .

. . .
254 111111104.9922
255 111111114.9961

TEST LEVEL CODES

All electrical characteristics are subject to the
following conditions: All parameters having min/
max specifications are guaranteed. The Test
Level column indicates the specific device test­ing actually performed during production and
Quality Assurance inspection. Any blank sec­tion in the data column indicates that the speci­fication is not tested at the specified condition.

TEST LEVEL

I

II

III
IV

V

VI

TEST PROCEDURE

100% production tested at the specified temperature.
100% production tested at TA=25 °C, and sample

tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design

and characterization data.
Parameter is a typical value for information purposes

only.
100% production tested at TA = 25 °C. Parameter is

guaranteed over specified temperature range.

SPT

4 3/14/97

SPT5100

Figure 1 - Typical Interface Circuit

Figure 3 - Timing DiagramFigure 2 - Typical Performance Characteristics

t

h

N-Data

t

s

1/2 LSB

t

pd

N-Output Level

1/2 LSB

Full Scale Output Voltage

VCS (V)

1.41.31.21.11.00.9

2.5

3.0

3.5

4.0

4.5

5.0

Full Scale Output Voltage

Versus VCS

Load Resistors = 240 Ω
Ta = +25 °C
Digital Inputs = All Ø

240 Ω

AV

DD

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

CØ (LSB)

C1

C2

C3

C4

C5

C6

C7 (MSB)

V

REF

V

CS

AV

SS

AV

DD

AV

DD

AV

SS

CLKC

CLKY

(MSB) Y7

Y6

Y5

Y4

Y3

Y2

Y1

(LSB) YØ

AV

DD

AV

DD

AV

SS

COUT

AV

SS

YOUT

AV

DD

AV

SS

16

15

14

13

12

11

10

9

25

26

27

28

29

30

31

32

240 Ω

AV

DD

10 kΩ

5 kΩ

2 kΩ

0.1 kΩ

0.1 kΩ

0.1 µF

0.1 µF

0.1 µF

AV

DD

0.1 µF

0.1 µF

SPT5100

10 µF

+

-

SPT

5 3/14/97

SPT5100

PACKAGE OUTLINE

32-Lead QFP

INCHES MILLIMETERS

SYMBOL MIN MAX MIN MAX

A 0.339 0.363 8.70 9.30
B 0.261 0.285 6.70 7.30
C 0.339 0.363 8.70 9.30
D 0.261 0.285 6.70 7.30
E 0.023 0.039 0.60 1.00
F 0.012 0.020 0.30 0.50
G 0.056 0.057 1.44 1.46
H 0.002 0.006 0.05 0.15

I 0.039 typ 1.00 typ
J 0.004 0.008 0.09 0.20
K0°7°0°7°
L 0.016 typ 0.4 typ

A
B

C D

E F

G H

I

J

K

L

SPT

6 3/14/97

SPT5100

PIN ASSIGNMENTS PIN FUNCTIONS

Name Function

C

OUT

C Channel Analog Current Output

Y

OUT

Y Channel Analog Current Output
C7 - C0 C Channel Data Inputs
Y7 - Y0 Y Channel Data Inputs
CLKY Y Channel Clock Input
CLKC C Channel Clock Input
V

REF

Voltage Reference

(A 0.1 µF ceramic capacitor should be used)
V

CS

Full-Scale Adjust Control Voltage 1 to 1.4 V
AV

SS

Ground
AV

DD

Power Supply Voltage

V

REF

V

CS

AV

SS

AV

DD

AV

DD

AV

SS

CLKC

CLKY

(MSB) Y7

Y6
Y5
Y4
Y3
Y2
Y1

(LSB) Y0

AV

DD

AV

DD

AV

SS

C

OUT

AV

SS

Y

OUT

AV

DD

AV

SS

C7 (MSB)

C6

C5

C4

C3

C2

C1

C0 (LSB)

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

17

18

19

20

21

22

23

24

8

7

6

5

4

3

2

1

SPT5100

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE

SPT5100SCT 0 to +70 °C 32L QFP

Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby expressly
granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited.

WARNING - LIFE SUPPORT APPLICATIONS POLICY - SPT products should not be used within Life Support Systems without the specific
written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably
expected to result in significant personal injury or death.

Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device
failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.