Datasheet SPC560P44L3, SPC560P44L5, SPC560P50L3, SPC560P50L5 Datasheet (ST)

SPC560P44L3, SPC560P44L5

LQFP100 (14 x 14 x 1.4 mm)

LQFP144 (20 x 20 x 1.4 mm)

SPC560P50L3, SPC560P50L5

32-bit Power Architecture® based MCU with 576 KB Flash memory

and 40 KB SRAM for automotive chassis and safety applications

Datasheet  production data

Features

■ 64 MHz, single issue, 32-bit CPU core complex

(e200z0h)
– Compliant with Power Architecture

embedded category

– Variable Length Encoding (VLE)

■ Memory organization

– Up to 512 KB on-chip code flash memory

with ECC and erase/program controller

– Additional 64 (4 × 16) KB on-chip data flash

memory with ECC for EEPROM emulation

– Up to 40 KB on-chip SRAM with ECC

■ Fail safe protection

– Programmable watchdog timer
– Non-maskable interrupt
– Fault collection unit

■ Nexus L2+ interface

■ Interrupts

– 16-channel eDMA controller
– 16 priority level controller

■ General purpose I/Os individually

programmable as input, output or special
function

■ 2 general purpose eTimer units

– 6 timers each with up/down count

capabilities
– 16-bit resolution, cascadable counters
– Quadrature decode with rotation direction

flag
– Double buffer input capture and output

compare

■ Communications interfaces

– 2 LINFlex channels (LIN 2.1)
– 4 DSPI channels with automatic chip select

generation
– 1 FlexCAN interface (2.0B Active) with 32

message objects

®

– 1 safety port based on FlexCAN with 32

message objects and up to 7.5 Mbit/s
capability; usable as second CAN when not
used as safety port

– 1 FlexRay™ module (V2.1) with selectable

dual or single channel support, 32
message objects and up to 10 Mbit/s
(512 KB device only)

■ Two 10-bit analog-to-digital converters (ADC)

– 2 × 11 input channels, + 4 shared channels
– Conversion time < 1 µs including sampling

time at full precision

– Programmable ADC Cross Triggering Unit

(CTU)

– 4 analog watchdogs with interrupt

capability

■ On-chip CAN/UART bootstrap loader with Boot

Assist Module (BAM)

■ 1 FlexPWM unit: 8 complementary or

independent outputs with ADC synchronization
signals

Table 1. Device summary

Package

448 KB Flash 576 KB Flash

LQFP144 SPC560P44L5 SPC560P50L5

LQFP100 SPC560P44L3 SPC560P50L3

Part number

July 2012 Doc ID 14723 Rev 8 1/115

This is information on a product in full production.

www.st.com

1

Contents SPC560P44Lx, SPC560P50Lx

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.5 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.5.1 High performance e200z0 core processor . . . . . . . . . . . . . . . . . . . . . . . 13

1.5.2 Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.5.3 Enhanced direct memory access (eDMA) . . . . . . . . . . . . . . . . . . . . . . . 14

1.5.4 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.5.5 Static random access memory (SRAM) . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.5.6 Interrupt controller (INTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.5.7 System status and configuration module (SSCM) . . . . . . . . . . . . . . . . . 16

1.5.8 System clocks and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.5.9 Frequency-modulated phase-locked loop (FMPLL) . . . . . . . . . . . . . . . . 17

1.5.10 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.5.11 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.5.12 Periodic interrupt timer (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.5.13 System timer module (STM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.5.14 Software watchdog timer (SWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.5.15 Fault collection unit (FCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.5.16 System integration unit – Lite (SIUL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.5.17 Boot and censorship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.5.18 Error correction status module (ECSM) . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.5.19 Peripheral bridge (PBRIDGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.5.20 Controller area network (FlexCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.5.21 Safety port (FlexCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.5.22 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.5.23 Serial communication interface module (LINFlex) . . . . . . . . . . . . . . . . . 22

1.5.24 Deserial serial peripheral interface (DSPI) . . . . . . . . . . . . . . . . . . . . . . 23

1.5.25 Pulse width modulator (FlexPWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.5.26 eTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.5.27 Analog-to-digital converter (ADC) module . . . . . . . . . . . . . . . . . . . . . . . 25

1.5.28 Cross triggering unit (CTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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SPC560P44Lx, SPC560P50Lx Contents

1.5.29 Nexus development interface (NDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

1.5.30 Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.5.31 IEEE 1149.1 JTAG controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.5.32 On-chip voltage regulator (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 29

2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.2.1 Power supply and reference voltage pins . . . . . . . . . . . . . . . . . . . . . . . 31

2.2.2 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.2.3 Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.4 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.5.1 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.5.2 General notes for specifications at maximum junction temperature . . . 57

3.6 Electromagnetic interference (EMI) characteristics . . . . . . . . . . . . . . . . . 59

3.7 Electrostatic discharge (ESD) characteristics . . . . . . . . . . . . . . . . . . . . . 59

3.8 Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 59

3.8.1 Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 59

3.8.2 Voltage monitor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 63

3.9 Power up/down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.10 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.10.1 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.10.2 DC electrical characteristics (5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.10.3 DC electrical characteristics (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.10.4 Input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . 69

3.10.5 I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

3.11 Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 78

3.12 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.13 16 MHz RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . 81

Doc ID 14723 Rev 8 3/115

Contents SPC560P44Lx, SPC560P50Lx

3.14 Analog-to-digital converter (ADC) electrical characteristics . . . . . . . . . . . 81

3.14.1 Input impedance and ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

3.14.2 ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

3.15 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 88

3.16 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

3.16.1 Pad AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

3.17 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

3.17.1 RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

3.17.2 IEEE 1149.1 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

3.17.3 Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

3.17.4 External interrupt timing (IRQ pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

3.17.5 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

4 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

4.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

4.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

4.2.1 LQFP144 mechanical outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . 104

4.2.2 LQFP100 mechanical outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . 106

5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Appendix A Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

4/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. SPC560P44Lx, SPC560P50Lx device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. SPC560P44Lx, SPC560P50Lx device configuration differences . . . . . . . . . . . . . . . . . . . . . 8

Table 4. SPC560P44Lx, SPC560P50Lx series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 5. Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 6. System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 7. Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 8. Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 10. Recommended operating conditions (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 11. Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 12. Thermal characteristics for 144-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 13. Thermal characteristics for 100-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 14. EMI testing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 15. ESD ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 16. Approved NPN ballast components (configuration with resistor on base) . . . . . . . . . . . . . 60

Table 17. Voltage regulator electrical characteristics (configuration with resistor on base) . . . . . . . . 61

Table 18. Voltage regulator electrical characteristics (configuration without resistor on base) . . . . . 62

Table 19. Low voltage monitor electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 20. PAD3V5V field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 21. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0) . . . . . . . . . . . . . . . . . . . . . 66

Table 22. Supply current (5.0 V, NVUSRO[PAD3V5V] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 23. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1) . . . . . . . . . . . . . . . . . . . . . 67

Table 24. Supply current (3.3 V, NVUSRO[PAD3V5V] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 25. I/O supply segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 26. I/O weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 27. I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 28. Main oscillator output electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0) . . . . . . . 78

Table 29. Main oscillator output electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1) . . . . . . . 79

Table 30. Input clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 31. FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 32. 16 MHz RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 33. ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 34. Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 35. Flash memory module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 36. Flash memory read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 37. Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 38. RESET electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 39. JTAG pin AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 40. Nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 41. External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 42. DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 43. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 44. LQFP100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 45. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 46. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Doc ID 14723 Rev 8 5/115

List of figures SPC560P44Lx, SPC560P50Lx

List of figures

Figure 1. SPC560P44Lx, SPC560P50Lx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 2. 144-pin LQFP pinout – Full featured configuration (top view) . . . . . . . . . . . . . . . . . . . . . . 29

Figure 3. 100-pin LQFP pinout – Airbag configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 4. 100-pin LQFP pinout – Full featured configuration (top view) . . . . . . . . . . . . . . . . . . . . . . 31

Figure 5. Power supplies constraints (–0.3 V  V
Figure 6. Independent ADC supply (–0.3 V  V
Figure 7. Power supplies constraints (3.0 V  V
Figure 8. Independent ADC supply (3.0 V  V

DD_HV_IOx

DD_HV_REG

DD_HV_IOx

DD_HV_REG

Figure 9. Configuration with resistor on base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 10. Configuration without resistor on base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 11. Power-up typical sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 12. Power-down typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 13. Brown-out typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 14. Input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 15. ADC characteristics and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 16. Input equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 17. Transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 18. Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 19. Pad output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 20. Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 21. Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 22. JTAG test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 23. JTAG test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 24. JTAG boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 25. Nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 26. Nexus event trigger and test clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 27. Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 28. External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 29. DSPI classic SPI timing – Master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 30. DSPI classic SPI timing – Master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 31. DSPI classic SPI timing – Slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 32. DSPI classic SPI timing – Slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 33. DSPI modified transfer format timing – Master, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 34. DSPI modified transfer format timing – Master, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 35. DSPI modified transfer format timing – Slave, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 36. DSPI modified transfer format timing – Slave, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 37. DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 38. LQFP144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 39. LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 40. Commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

 6.0 V). . . . . . . . . . . . . . . . . . . . . . . . . 52

 6.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . 52

 5.5 V). . . . . . . . . . . . . . . . . . . . . . . . . . 55

 5.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Introduction

1 Introduction

1.1 Document overview

This document provides electrical specifications, pin assignments, and package diagrams
for the SPC560P44/50 series of microcontroller units (MCUs). It also describes the device
features and highlights important electrical and physical characteristics. For functional
characteristics, refer to the device reference manual.

1.2 Description

This 32-bit system-on-chip (SoC) automotive microcontroller family is the latest
achievement in integrated automotive application controllers. It belongs to an expanding
range of automotive-focused products designed to address chassis applications—
specifically, electrical hydraulic power steering (EHPS) and electric power steering (EPS)—
as well as airbag applications.

This family is one of a series of next-generation integrated automotive microcontrollers
based on the Power Architecture technology.

The advanced and cost-efficient host processor core of this automotive controller family
complies with the Power Architecture embedded category. It operates at speeds of up to
64 MHz and offers high performance processing optimized for low power consumption. It
capitalizes on the available development infrastructure of current Power Architecture
devices and is supported with software drivers, operating systems and configuration code to
assist with users implementations.

1.3 Device comparison

Ta bl e 2 provides a summary of different members of the SPC560P44Lx, SPC560P50Lx

family and their features—relative to full-featured version—to enable a comparison among
the family members and an understanding of the range of functionality offered within this
family.

Table 2. SPC560P44Lx, SPC560P50Lx device comparison

Code flash memory (with ECC) 384 KB 512 KB

Data flash memory / EE option (with ECC) 64 KB

SRAM (with ECC) 36 KB 40 KB

Processor core 32-bit e200z0h

Instruction set VLE (variable length encoding)

CPU performance 0–64 MHz

FMPLL (frequency-modulated phase-locked loop)
module

INTC (interrupt controller) channels 147

PIT (periodic interrupt timer) 1 (includes four 32-bit timers)

Feature SPC560P44 SPC560P50

2

Doc ID 14723 Rev 8 7/115

Introduction SPC560P44Lx, SPC560P50Lx

Table 2. SPC560P44Lx, SPC560P50Lx device comparison (continued)

Feature SPC560P44 SPC560P50

eDMA (enhanced direct memory access)
channels

FlexRay Yes

FlexCAN (controller area network) 2

16

(1)

(2),(3)

Safety port Yes (via second FlexCAN module)

FCU (fault collection unit) Yes

CTU (cross triggering unit) Yes

eTimer 2 (16-bit, 6 channels)

FlexPWM (pulse-width modulation) channels 8 (capturing on X-channels)

(4)

ADC (analog-to-digital converter) 2 (10-bit, 15-channel

)

LINFlex 2

DSPI (deserial serial peripheral interface) 4

CRC (cyclic redundancy check) unit Yes

JTAG controller Yes

Nexus port controller (NPC) Yes (Level 2+)

Digital power supply

(5)

3.3 V or 5 V single supply with external transistor

Analog power supply 3.3 V or 5 V

Supply

Internal RC oscillator 16 MHz

External crystal oscillator 4–40 MHz

Packages

LQFP100
LQFP144

Temperature Standard ambient temperature –40 to 125 °C

1. 32 message buffers, selectable single or dual channel support

2. Each FlexCAN module has 32 message buffers.

3. One FlexCAN module can act as a Safety Port with a bit rate as high as 7.5 Mbit/s.

4. Four channels shared between the two ADCs

5. The different supply voltages vary according to the part number ordered.

SPC560P44Lx, SPC560P50Lx is available in two configurations having different features:
full-featured and airbag. Ta bl e 3 shows the main differences between the two versions.

Table 3. SPC560P44Lx, SPC560P50Lx device configuration differences

CTU (cross triggering unit) Yes No

FlexPWM Yes No

Feature Full-featured Airbag

8/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Introduction

Table 3. SPC560P44Lx, SPC560P50Lx device configuration differences (continued)

Feature Full-featured Airbag

FlexRay Yes No

FMPLL (frequency-modulated phase-locked loop) module

1.4 Block diagram

Figure 1 shows a top-level block diagram of the SPC560P44Lx, SPC560P50Lx MCU.

2 (one FMPLL, one for

FlexRay)

1 (only FMPLL)

Doc ID 14723 Rev 8 9/115

Introduction SPC560P44Lx, SPC560P50Lx

e200z0 Core

32-bit

general

purpose

registers

Special

purpose

registers

Integer

execution

unit

Exception

handler

Var ia ble

length

encoded

instructions

Instruction

unit

Load/store

unit

Branch

prediction

unit

JTAG

1.2 V regulator
control

XOSC

16 MHz

RC oscillator

FMPLL_0

(System)

Nexus port

controller

Interrupt

controller

eDMA

16 channels

Master

Master

Instruction

32-bit

Master

Data
32-bit

SRAM

(with ECC)

Slave Slave

Crossbar switch (XBAR, AMBA 2.0 v6 AHB)

Peripheral bridge

FCU

Legend:

ADC Analog-to-digital converter
BAM Boot assist module
CRC Cyclic redundancy check
CTU Cross triggering unit
DSPI Deserial serial peripheral interface
ECSM Error correction status module
eDMA Enhanced direct memory access
eTimer Enhanced timer
FCU Fault collection unit
Flash Flash memory
FlexCAN Controller area network
FlexPWM Flexible pulse width modulation
FMPLL Frequency-modulated phase-locked loop
INTC Interrupt controller
JTAG JTAG controller

LINFlex Serial communication interface (LIN support)
MC_CGM Clock generation module
MC_ME Mode entry module
MC_PCU Power control unit
MC_RGM Reset generation module
PIT Periodic interrupt timer
SIUL System integration unit Lite
SRAM Static random-access memory
SSCM System status and configuration module
STM System timer module
SWT Software watchdog timer
WKPU Wakeup unit
XOSC External oscillator
XBAR Crossbar switch

Slave

External ballast

Code Flash

(with ECC)

Data Flash
(with ECC)

Nexus 2+

eDMA

16 channels

FlexPWM

CTU

4×

2×

DSPI

2×

FlexCAN

LINFlex

Safety port

PIT

STM

SWT

MC_RGM

MC_CGM

MC_ME

BAM

SIUL

eTimer (6 ch)

FMPLL_1

(FlexRay, MotCtrl)

FlexRay

SSCM

1.2 V Rail V

REG

WKPU

CRC

Shared

Channels

Channels

10-bit 10-bit

0–10

0–10

channels

11–14

ADC_1ADC_0

ECSM

10/115 Doc ID 14723 Rev 8

Figure 1. SPC560P44Lx, SPC560P50Lx block diagram

SPC560P44Lx, SPC560P50Lx Introduction

Table 4. SPC560P44Lx, SPC560P50Lx series block summary

Block Function

Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter

Boot assist module (BAM)

Clock generation module
(MC_CGM)

Controller area network
(FlexCAN)

Cross triggering unit (CTU)

Crossbar switch (XBAR)

Block of read-only memory containing VLE code which is executed according to
the boot mode of the device

Provides logic and control required for the generation of system and peripheral
clocks

Supports the standard CAN communications protocol

Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT

Supports simultaneous connections between two master ports and three slave
ports; supports a 32-bit address bus width and a 32-bit data bus width

Cyclic redundancy check (CRC) CRC checksum generator

Deserial serial peripheral
interface (DSPI)

Enhanced direct memory access
(eDMA)

Provides a synchronous serial interface for communication with external
devices

Performs complex data transfers with minimal intervention from a host
processor via “n” programmable channels

Enhanced timer (eTimer) Provides enhanced programmable up/down modulo counting

Provides a myriad of miscellaneous control functions for the device including
Error correction status module
(ECSM)

program-visible information about configuration and revision levels, a reset

status register, wakeup control for exiting sleep modes, and optional features

such as information on memory errors reported by error-correcting codes

External oscillator (XOSC)

Provides an output clock used as input reference for FMPLL_0 or as reference

clock for specific modules depending on system needs

Fault collection unit (FCU) Provides functional safety to the device

Flash memory Provides non-volatile storage for program code, constants and variables

Frequency-modulated phase­locked loop (FMPLL)

Generates high-speed system clocks and supports programmable frequency

modulation

Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requests

JTAG controller

LINFlex controller

Provides the means to test chip functionality and connectivity while remaining

transparent to system logic when not in test mode

Manages a high number of LIN (Local Interconnect Network protocol)

messages efficiently with minimum load on CPU

Provides a mechanism for controlling the device operational mode and mode

Mode entry module (MC_ME)

transition sequences in all functional states; also manages the power control

unit, reset generation module and clock generation module, and holds the

configuration, control and status registers accessible for applications

Periodic interrupt timer (PIT) Produces periodic interrupts and triggers

Peripheral bridge (PBRIDGE) Interface between the system bus and on-chip peripherals

Power control unit (MC_PCU)

Reduces the overall power consumption by disconnecting parts of the device

from the power supply via a power switching device; device components are

grouped into sections called “power domains” which are controlled by the PCU

Doc ID 14723 Rev 8 11/115

Introduction SPC560P44Lx, SPC560P50Lx

Table 4. SPC560P44Lx, SPC560P50Lx series block summary (continued)

Block Function

Pulse width modulator
(FlexPWM)

Reset generation module
(MC_RGM)

Static random-access memory
(SRAM)

Contains four PWM submodules, each of which is capable of controlling a

single half-bridge power stage and two fault input channels

Centralizes reset sources and manages the device reset sequence of the

device

Provides storage for program code, constants, and variables

Provides control over all the electrical pad controls and up 32 ports with 16 bits
System integration unit lite (SIUL)

of bidirectional, general-purpose input and output signals and supports up to 32

external interrupts with trigger event configuration

System status and configuration
module (SSCM)

System timer module (STM)

Provides system configuration and status data (such as memory size and

status, device mode and security status), device identification data, debug

status port enable and selection, and bus and peripheral abort enable/disable

Provides a set of output compare events to support AUTOSAR

system tasks

System watchdog timer (SWT) Provides protection from runaway code

Supports up to 18 external sources that can generate interrupts or wakeup
Wakeup unit (WKPU)

events, 1 of which can cause non-maskable interrupt requests or wakeup

events

1. AUTOSAR: AUTomotive Open System ARchitecture (see www.autosar.org)

(1)

and operating

12/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Introduction

1.5 Feature details

1.5.1 High performance e200z0 core processor

The e200z0 Power Architecture core provides the following features:

● High performance e200z0 core processor for managing peripherals and interrupts

● Single issue 4-stage pipeline in-order execution 32-bit Power Architecture CPU

● Harvard architecture

● Variable length encoding (VLE), allowing mixed 16-bit and 32-bit instructions

– Results in smaller code size footprint

– Minimizes impact on performance

● Branch processing acceleration using lookahead instruction buffer

● Load/store unit

– 1 cycle load latency

– Misaligned access support

– No load-to-use pipeline bubbles

● Thirty-two 32-bit general purpose registers (GPRs)

● Separate instruction bus and load/store bus Harvard architecture

● Hardware vectored interrupt support

● Reservation instructions for implementing read-modify-write constructs

● Long cycle time instructions, except for guarded loads, do not increase interrupt

latency

● Extensive system development support through Nexus debug port

● Non-maskable interrupt support

1.5.2 Crossbar switch (XBAR)

The XBAR multi-port crossbar switch supports simultaneous connections between four
master ports and three slave ports. The crossbar supports a 32-bit address bus width and a
32-bit data bus width.

The crossbar allows for two concurrent transactions to occur from any master port to any
slave port; but one of those transfers must be an instruction fetch from internal flash
memory. If a slave port is simultaneously requested by more than one master port,
arbitration logic will select the higher priority master and grant it ownership of the slave port.
All other masters requesting that slave port will be stalled until the higher priority master
completes its transactions. Requesting masters will be treated with equal priority and will be
granted access to a slave port in round-robin fashion, based upon the ID of the last master
to be granted access.

Doc ID 14723 Rev 8 13/115

Introduction SPC560P44Lx, SPC560P50Lx

The crossbar provides the following features:

● 4 master ports:

– e200z0 core complex Instruction port

– e200z0 core complex Load/Store Data port

–eDMA

–FlexRay

● 3 slave ports:

– Flash memory (code flash and data flash)

–SRAM

– Peripheral bridge

● 32-bit internal address, 32-bit internal data paths

● Fixed Priority Arbitration based on Port Master

● Temporary dynamic priority elevation of masters

1.5.3 Enhanced direct memory access (eDMA)

The enhanced direct memory access (eDMA) controller is a second-generation module
capable of performing complex data movements via 16 programmable channels, with
minimal intervention from the host processor. The hardware micro architecture includes a
DMA engine which performs source and destination address calculations, and the actual
data movement operations, along with an SRAM-based memory containing the transfer
control descriptors (TCD) for the channels. This implementation is utilized to minimize the
overall block size.

The eDMA module provides the following features:

● 16 channels support independent 8, 16 or 32-bit single value or block transfers

● Supports variable sized queues and circular queues

● Source and destination address registers are independently configured to either post-

increment or to remain constant

● Each transfer is initiated by a peripheral, CPU, or eDMA channel request

● Each eDMA channel can optionally send an interrupt request to the CPU on completion

of a single value or block transfer

● DMA transfers possible between system memories, DSPIs, ADC, FlexPWM, eTimer

and CTU

● Programmable DMA channel multiplexer for assignment of any DMA source to any

available DMA channel with as many as 30 request sources

● eDMA abort operation through software

1.5.4 Flash memory

The SPC560P44Lx, SPC560P50Lx provides as much as 576 KB of programmable, non­volatile, flash memory. The non-volatile memory (NVM) can be used for instruction and/or
data storage. The flash memory module interfaces the system bus to a dedicated flash
memory array controller. It supports a 32-bit data bus width at the system bus port, and a
128-bit read data interface to flash memory. The module contains four 128-bit wide prefetch
buffers. Prefetch buffer hits allow no-wait responses. Normal flash memory array accesses
are registered and are forwarded to the system bus on the following cycle, incurring two
wait-states.

14/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Introduction

The flash memory module provides the following features:

● As much as 576 KB flash memory

– 8 blocks (32 KB + 2×16 KB + 32 KB + 32 KB + 3×128 KB) code flash

– 4 blocks (16 KB + 16 KB + 16 KB + 16 KB) data flash

– Full Read While Write (RWW) capability between code and data flash

● Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch

buffers can be configured to prefetch code or data or both)

● Typical flash memory access time: 0 wait states for buffer hits, 2 wait states for page

buffer miss at 64 MHz

● Hardware managed flash memory writes handled by 32-bit RISC Krypton engine

● Hardware and software configurable read and write access protections on a per-master

basis

● Configurable access timing allowing use in a wide range of system frequencies

● Multiple-mapping support and mapping-based block access timing (up to 31 additional

cycles) allowing use for emulation of other memory types.

● Software programmable block program/erase restriction control

● Erase of selected block(s)

● Read page sizes

– Code flash memory: 128 bits (4 words)

– Data flash memory: 32 bits (1 word)

● ECC with single-bit correction, double-bit detection for data integrity

– Code flash memory: 64-bit ECC

– Data flash memory: 64-bit ECC

● Embedded hardware program and erase algorithm

● Erase suspend, program suspend and erase-suspended program

● Censorship protection scheme to prevent flash memory content visibility

● Hardware support for EEPROM emulation

1.5.5 Static random access memory (SRAM)

The SPC560P44Lx, SPC560P50Lx SRAM module provides up to 40 KB of general-purpose
memory.

The SRAM module provides the following features:

● Supports read/write accesses mapped to the SRAM from any master

● Up to 40 KB general purpose SRAM

● Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of

memory

● Typical SRAM access time: 0 wait-state for reads and 32-bit writes; 1 wait state for 8-

and 16-bit writes if back to back with a read to same memory block

1.5.6 Interrupt controller (INTC)

The interrupt controller (INTC) provides priority-based preemptive scheduling of interrupt
requests, suitable for statically scheduled hard real-time systems. The INTC handles 147
selectable-priority interrupt sources.

Doc ID 14723 Rev 8 15/115

Introduction SPC560P44Lx, SPC560P50Lx

For high priority interrupt requests, the time from the assertion of the interrupt request from
the peripheral to when the processor is executing the interrupt service routine (ISR) has
been minimized. The INTC provides a unique vector for each interrupt request source for
quick determination of which ISR has to be executed. It also provides a wide number of
priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To
allow the appropriate priorities for each source of interrupt request, the priority of each
interrupt request is software configurable.

When multiple tasks share a resource, coherent accesses to that resource need to be
supported. The INTC supports the priority ceiling protocol (PCP) for coherent accesses. By
providing a modifiable priority mask, the priority can be raised temporarily so that all tasks
which share the same resource can not preempt each other.

The INTC provides the following features:

● Unique 9-bit vector for each separate interrupt source

● 8 software triggerable interrupt sources

● 16 priority levels with fixed hardware arbitration within priority levels for each interrupt

source

● Ability to modify the ISR or task priority: modifying the priority can be used to implement

the Priority Ceiling Protocol for accessing shared resources.

● 2 external high priority interrupts directly accessing the main core and I/O processor

(IOP) critical interrupt mechanism

1.5.7 System status and configuration module (SSCM)

The system status and configuration module (SSCM) provides central device functionality.

The SSCM includes these features:

● System configuration and status

– Memory sizes/status

– Device mode and security status

– Determine boot vector

– Search code flash for bootable sector

–DMA status

● Debug status port enable and selection

● Bus and peripheral abort enable/disable

1.5.8 System clocks and clock generation

The following list summarizes the system clock and clock generation on the SPC560P44Lx,
SPC560P50Lx:

● Lock detect circuitry continuously monitors lock status

● Loss of clock (LOC) detection for PLL outputs

● Programmable output clock divider (1, 2, 4, 8)

● FlexPWM module and eTimer module can run on an independent clock source

● On-chip oscillator with automatic level control

● Internal 16 MHz RC oscillator for rapid start-up and safe mode: supports frequency

trimming by user application

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SPC560P44Lx, SPC560P50Lx Introduction

1.5.9 Frequency-modulated phase-locked loop (FMPLL)

The FMPLL allows the user to generate high speed system clocks from a 4–40 MHz input
clock. Further, the FMPLL supports programmable frequency modulation of the system
clock. The PLL multiplication factor, output clock divider ratio are all software configurable.

The PLL has the following major features:

● Input clock frequency: 4–40 MHz

● Maximum output frequency: 64 MHz

● Voltage controlled oscillator (VCO)—frequency 256–512 MHz

● Reduced frequency divider (RFD) for reduced frequency operation without forcing the

PLL to relock

● Frequency-modulated PLL

– Modulation enabled/disabled through software

– Triangle wave modulation

● Programmable modulation depth (±0.25% to ±4% deviation from center frequency):

programmable modulation frequency dependent on reference frequency

● Self-clocked mode (SCM) operation

1.5.10 Main oscillator

The main oscillator provides these features:

● Input frequency range: 4–40 MHz

● Crystal input mode or oscillator input mode

● PLL reference

1.5.11 Internal RC oscillator

This device has an RC ladder phase-shift oscillator. The architecture uses constant current
charging of a capacitor. The voltage at the capacitor is compared by the stable bandgap
reference voltage.

The RC oscillator provides these features:

● Nominal frequency 16 MHz

● ±5% variation over voltage and temperature after process trim

● Clock output of the RC oscillator serves as system clock source in case loss of lock or

loss of clock is detected by the PLL

● RC oscillator is used as the default system clock during startup

1.5.12 Periodic interrupt timer (PIT)

The PIT module implements these features:

● 4 general purpose interrupt timers

● 32-bit counter resolution

● Clocked by system clock frequency

● Each channel can be used as trigger for a DMA request

Doc ID 14723 Rev 8 17/115

Introduction SPC560P44Lx, SPC560P50Lx

1.5.13 System timer module (STM)

The STM module implements these features:

● One 32-bit up counter with 8-bit prescaler

● Four 32-bit compare channels

● Independent interrupt source for each channel

● Counter can be stopped in debug mode

1.5.14 Software watchdog timer (SWT)

The SWT has the following features:

● 32-bit time-out register to set the time-out period

● Programmable selection of system or oscillator clock for timer operation

● Programmable selection of window mode or regular servicing

● Programmable selection of reset or interrupt on an initial time-out

● Master access protection

● Hard and soft configuration lock bits

● Reset configuration inputs allow timer to be enabled out of reset

1.5.15 Fault collection unit (FCU)

The FCU provides an independent fault reporting mechanism even if the CPU is
malfunctioning.

The FCU module has the following features:

● FCU status register reporting the device status

● Continuous monitoring of critical fault signals

● User selection of critical signals from different fault sources inside the device

● Critical fault events trigger 2 external pins (user selected signal protocol) that can be

used externally to reset the device and/or other circuitry (for example, safety relay or
FlexRay transceiver)

● Faults are latched into a register

1.5.16 System integration unit – Lite (SIUL)

The SPC560P44Lx, SPC560P50Lx SIUL controls MCU pad configuration, external
interrupt, general purpose I/O (GPIO), and internal peripheral multiplexing.

The pad configuration block controls the static electrical characteristics of I/O pins. The
GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU.

18/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Introduction

The SIU provides the following features:

● Centralized general purpose input output (GPIO) control of as many as 80 input/output

pins and 26 analog input-only pads (package dependent)

● All GPIO pins can be independently configured to support pull-up, pull down, or no pull

● Reading and writing to GPIO supported both as individual pins and 16-bit wide ports

● All peripheral pins (except ADC channels) can be alternatively configured as both

general purpose input or output pins

● ADC channels support alternative configuration as general purpose inputs

● Direct readback of the pin value is supported on all pins through the SIUL

● Configurable digital input filter that can be applied to some general purpose input pins

for noise elimination: as many as 4 internal functions can be multiplexed onto 1 pin

1.5.17 Boot and censorship

Different booting modes are available in the SPC560P44Lx, SPC560P50Lx: booting from
internal flash memory and booting via a serial link.

The default booting scheme uses the internal flash memory (an internal pull-down is used to
select this mode). Optionally, the user can boot via FlexCAN or LINFlex (using the boot
assist module software).

A censorship scheme is provided to protect the content of the flash memory and offer
increased security for the entire device.

A password mechanism is designed to grant the legitimate user access to the non-volatile
memory.

Boot assist module (BAM)

The BAM is a block of read-only one-time programmed memory and is identical for all
SPC560Pxx devices that are based on the e200z0h core. The BAM program is executed
every time the device is powered on if the alternate boot mode has been selected by the
user.

The BAM provides the following features:

● Serial bootloading via FlexCAN or LINFlex

● Ability to accept a password via the used serial communication channel to grant the

legitimate user access to the non-volatile memory

1.5.18 Error correction status module (ECSM)

The ECSM provides a myriad of miscellaneous control functions regarding program-visible
information about the platform configuration and revision levels, a reset status register, a
software watchdog timer, wakeup control for exiting sleep modes, and information on
platform memory errors reported by error-correcting codes and/or generic access error
information for certain processor cores.

The Error Correction Status Module supports a number of miscellaneous control functions
for the platform. The ECSM includes these features:

● Registers for capturing information on platform memory errors if error-correcting codes

(ECC) are implemented

● For test purposes, optional registers to specify the generation of double-bit memory

errors are enabled on the SPC560P44Lx, SPC560P50Lx.

Doc ID 14723 Rev 8 19/115

Introduction SPC560P44Lx, SPC560P50Lx

The sources of the ECC errors are:

● Flash memory

● SRAM

1.5.19 Peripheral bridge (PBRIDGE)

The PBRIDGE implements the following features:

● Duplicated periphery

● Master access privilege level per peripheral (per master: read access enable; write

access enable)

● Write buffering for peripherals

● Checker applied on PBRIDGE output toward periphery

● Byte endianess swap capability

1.5.20 Controller area network (FlexCAN)

The SPC560P44Lx, SPC560P50Lx MCU contains one controller area network (FlexCAN)
module. This module is a communication controller implementing the CAN protocol
according to Bosch Specification version 2.0B. The CAN protocol was designed to be used
primarily as a vehicle serial data bus, meeting the specific requirements of this field: real­time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness
and required bandwidth. The FlexCAN module contains 32 message buffers.

20/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Introduction

The FlexCAN module provides the following features:

● Full implementation of the CAN protocol specification, version 2.0B

– Standard data and remote frames

– Extended data and remote frames

– Up to 8-bytes data length

– Programmable bit rate up to 1 Mbit/s

● 32 message buffers of up to 8-bytes data length

● Each message buffer configurable as Rx or Tx, all supporting standard and extended

messages

● Programmable loop-back mode supporting self-test operation

● 3 programmable mask registers

● Programmable transmit-first scheme: lowest ID or lowest buffer number

● Time stamp based on 16-bit free-running timer

● Global network time, synchronized by a specific message

● Maskable interrupts

● Independent of the transmission medium (an external transceiver is assumed)

● High immunity to EMI

● Short latency time due to an arbitration scheme for high-priority messages

● Transmit features

– Supports configuration of multiple mailboxes to form message queues of scalable

depth

– Arbitration scheme according to message ID or message buffer number

– Internal arbitration to guarantee no inner or outer priority inversion

– Transmit abort procedure and notification

● Receive features

– Individual programmable filters for each mailbox

– 8 mailboxes configurable as a six-entry receive FIFO

– 8 programmable acceptance filters for receive FIFO

● Programmable clock source

– System clock

– Direct oscillator clock to avoid PLL jitter

1.5.21 Safety port (FlexCAN)

The SPC560P44Lx, SPC560P50Lx MCU has a second CAN controller synthesized to run at
high bit rates to be used as a safety port. The CAN module of the safety port provides the
following features:

● Identical to the FlexCAN module

● Bit rate as fast as 7.5 Mbit/s at 60 MHz CPU clock using direct connection between

CAN modules (no physical transceiver required)

● 32 message buffers of up to 8 bytes data length

● Can be used as a second independent CAN module

Doc ID 14723 Rev 8 21/115

Introduction SPC560P44Lx, SPC560P50Lx

1.5.22 FlexRay

The FlexRay module provides the following features:

● Full implementation of FlexRay Protocol Specification 2.1

● 32 configurable message buffers can be handled

● Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate

● Message buffers configurable as Tx, Rx or RxFIFO

● Message buffer size configurable

● Message filtering for all message buffers based on FrameID, cycle count and message

ID

● Programmable acceptance filters for RxFIFO message buffers

1.5.23 Serial communication interface module (LINFlex)

The LINFlex (local interconnect network flexible) on the SPC560P44Lx, SPC560P50Lx
features the following:

● Supports LIN Master mode, LIN Slave mode and UART mode

● LIN state machine compliant to LIN1.3, 2.0, and 2.1 specifications

● Handles LIN frame transmission and reception without CPU intervention

● LIN features

– Autonomous LIN frame handling

– Message buffer to store Identifier and as much as 8 data bytes

– Supports message length as long as 64 bytes

– Detection and flagging of LIN errors (sync field, delimiter, ID parity, bit framing,

checksum, and time-out)

– Classic or extended checksum calculation

– Configurable Break duration as long as 36-bit times

– Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional)

– Diagnostic features: Loop back; Self Test; LIN bus stuck dominant detection

– Interrupt-driven operation with 16 interrupt sources

● LIN slave mode features

– Autonomous LIN header handling

– Autonomous LIN response handling

● UART mode

– Full-duplex operation

– Standard non return-to-zero (NRZ) mark/space format

– Data buffers with 4-byte receive, 4-byte transmit

– Configurable word length (8-bit or 9-bit words)

– Error detection and flagging

– Parity, Noise and Framing errors

– Interrupt-driven operation with four interrupt sources

– Separate transmitter and receiver CPU interrupt sources

– 16-bit programmable baud-rate modulus counter and 16-bit fractional

– 2 receiver wake-up methods

22/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Introduction

1.5.24 Deserial serial peripheral interface (DSPI)

The deserial serial peripheral interface (DSPI) module provides a synchronous serial
interface for communication between the SPC560P44Lx, SPC560P50Lx MCU and external
devices.

The DSPI modules provide these features:

● Full duplex, synchronous transfers

● Master or slave operation

● Programmable master bit rates

● Programmable clock polarity and phase

● End-of-transmission interrupt flag

● Programmable transfer baud rate

● Programmable data frames from 4 to 16 bits

● Up to 20 chip select lines available

– 8 on DSPI_0

– 4 each on DSPI_1, DSPI_2 and DSPI_3

● 8 clock and transfer attributes registers

● Chip select strobe available as alternate function on one of the chip select pins for

deglitching

● FIFOs for buffering as many as 5 transfers on the transmit and receive side

● Queueing operation possible through use of the eDMA

● General purpose I/O functionality on pins when not used for SPI

1.5.25 Pulse width modulator (FlexPWM)

The pulse width modulator module (PWM) contains four PWM submodules, each capable of
controlling a single half-bridge power stage. There are also four fault channels.

This PWM is capable of controlling most motor types: AC induction motors (ACIM),
permanent magnet AC motors (PMAC), both brushless (BLDC) and brush DC motors
(BDC), switched (SRM) and variable reluctance motors (VRM), and stepper motors.

Doc ID 14723 Rev 8 23/115

Introduction SPC560P44Lx, SPC560P50Lx

The FlexPWM block implements the following features:

● 16-bit resolution for center, edge-aligned, and asymmetrical PWMs

● Maximum operating clock frequency of 120 MHz

● PWM outputs can operate as complementary pairs or independent channels

● Can accept signed numbers for PWM generation

● Independent control of both edges of each PWM output

● Synchronization to external hardware or other PWM supported

● Double buffered PWM registers

– Integral reload rates from 1 to 16

– Half cycle reload capability

● Multiple ADC trigger events can be generated per PWM cycle via hardware

● Write protection for critical registers

● Fault inputs can be assigned to control multiple PWM outputs

● Programmable filters for fault inputs

● Independently programmable PWM output polarity

● Independent top and bottom deadtime insertion

● Each complementary pair can operate with its own PWM frequency and deadtime

values

● Individual software-control for each PWM output

● All outputs can be programmed to change simultaneously via a “Force Out” event

● PWMX pin can optionally output a third PWM signal from each submodule

● Channels not used for PWM generation can be used for buffered output compare

functions

● Channels not used for PWM generation can be used for input capture functions

● Enhanced dual-edge capture functionality

● eDMA support with automatic reload

● 2 fault inputs

● Capture capability for PWMA, PWMB, and PWMX channels not supported

24/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Introduction

1.5.26 eTimer

The SPC560P44Lx, SPC560P50Lx includes two eTimer modules. Each module provides
six 16-bit general purpose up/down timer/counter units with the following features:

● Maximum operating clock frequency of 120 MHz

● Individual channel capability

– Input capture trigger

– Output compare

– Double buffer (to capture rising edge and falling edge)

– Separate prescaler for each counter

– Selectable clock source

– 0–100% pulse measurement

– Rotation direction flag (Quad decoder mode)

● Maximum count rate

– External event counting: max. count rate = peripheral clock/2

– Internal clock counting: max. count rate = peripheral clock

● Counters are:

– Cascadable

– Preloadable

● Programmable count modulo

● Quadrature decode capabilities

● Counters can share available input pins

● Count once or repeatedly

● Pins available as GPIO when timer functionality not in use

1.5.27 Analog-to-digital converter (ADC) module

The ADC module provides the following features:

Analog part:

● 2 on-chip AD converters

– 10-bit AD resolution

– 1 sample and hold unit per ADC

– Conversion time, including sampling time, less than 1 µs (at full precision)

– Typical sampling time is 150 ns min. (at full precision)

– Differential non-linearity error (DNL) ±1 LSB

– Integral non-linearity error (INL) ±1.5 LSB

–TUE <3LSB

– Single-ended input signal up to 5.0 V

– The ADC and its reference can be supplied with a voltage independent from V

– The ADC supply can be equal or higher than V

– The ADC supply and the ADC reference are not independent from each other

(they are internally bonded to the same pad)

– Sample times of 2 (default), 8, 64, or 128 ADC clock cycles

DDIO

DDIO

Doc ID 14723 Rev 8 25/115

Introduction SPC560P44Lx, SPC560P50Lx

Digital part:

● 2 × 13 input channels including 4 channels shared between the 2 converters

● 4 analog watchdogs comparing ADC results against predefined levels (low, high,

range) before results are stored in the appropriate ADC result location,

● 2 modes of operation: Normal mode or CTU control mode

● Normal mode features

– Register-based interface with the CPU: control register, status register, 1 result

register per channel

– ADC state machine managing 3 request flows: regular command, hardware

injected command, software injected command

– Selectable priority between software and hardware injected commands

– 4 analog watchdogs comparing ADC results against predefined levels (low, high,

range)

– DMA compatible interface

● CTU control mode features

– Triggered mode only

– 4 independent result queues (2 × 16 entries, 2 × 4 entries)

– Result alignment circuitry (left justified; right justified)

– 32-bit read mode allows to have channel ID on one of the 16-bit part

– DMA compatible interfaces

1.5.28 Cross triggering unit (CTU)

The cross triggering unit allows automatic generation of ADC conversion requests on user
selected conditions without CPU load during the PWM period and with minimized CPU load
for dynamic configuration.

It implements the following features:

● Double buffered trigger generation unit with as many as eight independent triggers

generated from external triggers

● Trigger generation unit configurable in sequential mode or in triggered mode

● Each Trigger can be appropriately delayed to compensate the delay of external low

pass filter

● Double buffered global trigger unit allowing eTimer synchronization and/or ADC

command generation

● Double buffered ADC command list pointers to minimize ADC-trigger unit update

● Double buffered ADC conversion command list with as many as 24 ADC commands

● Each trigger has the capability to generate consecutive commands

● ADC conversion command allows to control ADC channel from each ADC, single or

synchronous sampling, independent result queue selection

1.5.29 Nexus development interface (NDI)

The NDI (Nexus Development Interface) block provides real-time development support
capabilities for the SPC560P44Lx, SPC560P50Lx Power Architecture based MCU in
compliance with the IEEE-ISTO 5001-2003 standard. This development support is supplied
for MCUs without requiring external address and data pins for internal visibility. The NDI

26/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Introduction

block is an integration of several individual Nexus blocks that are selected to provide the
development support interface for this device. The NDI block interfaces to the host
processor and internal busses to provide development support as per the IEEE-ISTO 5001­2003 Class 2+ standard. The development support provided includes access to the MCU’s
internal memory map and access to the processor’s internal registers during run time.

The Nexus Interface provides the following features:

● Configured via the IEEE 1149.1

● All Nexus port pins operate at V

● Nexus 2+ features supported

(no dedicated power supply)

DDIO

– Static debug

– Watchpoint messaging

– Ownership trace messaging

– Program trace messaging

– Real time read/write of any internally memory mapped resources through JTAG

pins

– Overrun control, which selects whether to stall before Nexus overruns or keep

executing and allow overwrite of information

– Watchpoint triggering, watchpoint triggers program tracing

● Auxiliary Output Port

– 4 MDO (Message Data Out) pins

– MCKO (Message Clock Out) pin

– 2 MSEO

–EVTO

● Auxiliary Input Port

–EVTI

(Message Start/End Out) pins

(Event Out) pin

(Event In) pin

1.5.30 Cyclic redundancy check (CRC)

The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The
CRC module features:

● Support for CRC-16-CCITT (x25 protocol):

16

– x

● Support for CRC-32 (Ethernet protocol):

– x

● Zero wait states for each write/read operations to the CRC_CFG and CRC_INP

+ x12 + x5 + 1

32

+ x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1

registers at the maximum frequency

1.5.31 IEEE 1149.1 JTAG controller

The JTAG controller (JTAGC) block provides the means to test chip functionality and
connectivity while remaining transparent to system logic when not in test mode. All data
input to and output from the JTAGC block is communicated in serial format. The JTAGC
block is compliant with the IEEE standard.

Doc ID 14723 Rev 8 27/115

Introduction SPC560P44Lx, SPC560P50Lx

The JTAG controller provides the following features:

● IEEE Test Access Port (TAP) interface with 4 pins (TDI, TMS, TCK, TDO)

● Selectable modes of operation include JTAGC/debug or normal system operation.

● A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined

instructions:

– BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD

● A 5-bit instruction register that supports the additional following public instructions:

– ACCESS_AUX_TAP_NPC, ACCESS_AUX_TAP_ONCE

● 3 test data registers: a bypass register, a boundary scan register, and a device

identification register.

● A TAP controller state machine that controls the operation of the data registers,

instruction register and associated circuitry.

1.5.32 On-chip voltage regulator (VREG)

The on-chip voltage regulator module provides the following features:

● Uses external NPN (negative-positive-negative) transistor

● Regulates external 3.3 V /5.0 V down to 1.2 V for the core logic

● Low voltage detection on the internal 1.2 V and I/O voltage 3.3 V

28/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Package pinouts and signal descriptions

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73

3738394041424344454647484950515253545556575859606162636465666768697071

72

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

NMI
A[6]
D[1]
F[4]

F[5]
VDD_HV_IO0
VSS_HV_IO0

F[6]

MDO[0]

A[7]

C[4]

A[8]

C[5]

A[5]

C[7]

C[3]

VSS_LV_COR0
VDD_LV_COR0

F[7]

F[8]
VDD_HV_IO1
VSS_HV_IO1

F[9]

F[10]
F[11]

D[9]

VDD_HV_OSC
VSS_HV_OSC

XTAL

EXTAL

RESET

D[8]

D[5]

D[6]

VSS_LV_COR3
VDD_LV_COR3

A[4]
VPP_TEST
F[12]
D[14]
G[3]
C[14]
G[2]
C[13]
G[4]
D[12]
G[6]
VDD_HV_FL
VSS_HV_FL
D[13]
VSS_LV_COR1
VDD_LV_COR1
A[3]
VDD_HV_IO2
VSS_HV_IO2
TDO
TCK
TMS
TDI
G[5]
A[2]
G[7]
C[12]
G[8]
C[11]
G[9]
D[11]
G[10]
D[10]
G[11]
A[1]
A[0]

D[7]

G[0]

E[1]

E[3]

C[1]

E[4]

B[7]

E[5]

C[2]

E[6]

B[8]

E[7]

E[2]

VDD_HV_ADC0

VSS_HV_ADC0

B[9]

B[10]

B[11]

B[12]

VDD_HV_ADC1

VSS_HV_ADC1

D[15]

E[8]

B[13]

E[9]

B[15]

E[10]

B[14]

E[11]

C[0]

E[12]

E[0]

BCTRL

VDD_LV_REGCOR

VSS_LV_REGCOR

VDD_HV_REG

A[15]

A[14]

C[6]

G[1]

D[2]

F[3]

B[6]

F[2]

A[13]

F[1]

A[9]

F[0]

VSS_LV_COR2

VDD_LV_COR2

C[8]

D[4]

D[3]

VSS_HV_IO3

VDD_HV_IO3

D[0]

C[15]

C[9]

A[12]

E[15]

A[11]

E[14]

A[10]

E[13]

B[3]

F[14]

B[2]

F[15]

F[13]

C[10]

B[1]

B[0]

LQFP144

Note: Availability of port pin alternate functions depends on product selection.

2 Package pinouts and signal descriptions

2.1 Package pinouts

The LQFP pinouts are shown in the following figures.

Figure 2. 144-pin LQFP pinout – Full featured configuration (top view)

Doc ID 14723 Rev 8 29/115

Package pinouts and signal descriptions SPC560P44Lx, SPC560P50Lx

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

26272829303132333435363738394041424344454647484950

100

9998979695949392919089888786858483828180797877

76

NMI
A[6]
D[1]
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]

C[3]
VSS_LV_COR0
VDD_LV_COR0

VDD_HV_IO1
VSS_HV_IO1

D[9]

VDD_HV_OSC
VSS_HV_OSC

XTAL

EXTAL

RESET

D[8]

D[5]

D[6]
VSS_LV_COR3
VDD_LV_COR3

A[4]
VPP_TEST
D[14]
C[14]
C[13]
D[12]
VDD_HV_FL
VSS_HV_FL
D[13]
VSS_LV_COR1
VDD_LV_COR1
A[3]
VDD_HV_IO2
VSS_HV_IO2
TDO
TCK
TMS
TDI
A[2]
C[12]
C[11]
D[11]
D[10]
A[1]
A[0]

D[7]

E[1]

C[1]

B[7]

C[2]

B[8]

E[2]

VDD_HV_ADC0

VSS_HV_ADC0

B[9]

B[10]

B[11]

B[12]

VDD_HV_ADC1

VSS_HV_ADC1

D[15]

B[13]

B[15]

B[14]

C[0]

E[0]

BCTRL

VDD_LV_REGCOR

VSS_LV_REGCOR

VDD_HV_REG

A[15]

A[14]

C[6]

D[2]

B[6]

A[13]

A[9]

VSS_LV_COR2

VDD_LV_COR2

C[8]

D[4]

D[3]

VSS_HV_IO3

VDD_HV_IO3

D[0]

C[15]

C[9]

A[12]

A[11]

A[10]

B[3]

B[2]

C[10]

B[1]

B[0]

LQFP100

Note: Availability of port pin alternate functions depends on product selection.

Figure 3. 100-pin LQFP pinout – Airbag configuration (top view)

30/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Package pinouts and signal descriptions

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

26272829303132333435363738394041424344454647484950

100

9998979695949392919089888786858483828180797877

76

NMI
A[6]
D[1]
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]

C[3]
VSS_LV_COR0
VDD_LV_COR0

VDD_HV_IO1
VSS_HV_IO1

D[9]

VDD_HV_OSC
VSS_HV_OSC

XTAL

EXTAL

RESET

D[8]

D[5]

D[6]
VSS_LV_COR3
VDD_LV_COR3

A[4]
VPP_TEST
D[14]
C[14]
C[13]
D[12]
VDD_HV_FL
VSS_HV_FL
D[13]
VSS_LV_COR1
VDD_LV_COR1
A[3]
VDD_HV_IO2
VSS_HV_IO2
TDO
TCK
TMS
TDI
A[2]
C[12]
C[11]
D[11]
D[10]
A[1]
A[0]

D[7]

E[1]

C[1]

B[7]

C[2]

B[8]

E[2]

VDD_HV_ADC0

VSS_HV_ADC0

B[9]

B[10]

B[11]

B[12]

VDD_HV_ADC1

VSS_HV_ADC1

D[15]

B[13]

B[15]

B[14]

C[0]

E[0]

BCTRL

VDD_LV_REGCOR

VSS_LV_REGCOR

VDD_HV_REG

A[15]

A[14]

C[6]

D[2]

B[6]

A[13]

A[9]

VSS_LV_COR2

VDD_LV_COR2

C[8]

D[4]

D[3]

VSS_HV_IO3

VDD_HV_IO3

D[0]

C[15]

C[9]

A[12]

A[11]

A[10]

B[3]

B[2]

C[10]

B[1]

B[0]

LQFP100

Note: Availability of port pin alternate functions depends on product selection.

Figure 4. 100-pin LQFP pinout – Full featured configuration (top view)

2.2 Pin description

2.2.1 Power supply and reference voltage pins

The following sections provide signal descriptions and related information about the
functionality and configuration of the SPC560P44Lx, SPC560P50Lx devices.

Ta bl e 5 lists the power supply and reference voltage for the SPC560P44Lx, SPC560P50Lx

devices.

Doc ID 14723 Rev 8 31/115

Package pinouts and signal descriptions SPC560P44Lx, SPC560P50Lx

Table 5. Supply pins

Supply Pin

Symbol Description 100-pin 144-pin

VREG control and power supply pins. Pins available on 100-pin and 144-pin package.

BCTRL Voltage regulator external NPN ballast base control pin 47 69

or 5.0 V)

(3.3 V

Voltage regulator supply voltage 50 72

V

DD_HV_REG

1.2 V decoupling pins for core logic and regulator feedback.

V

DD_LV_REGCOR

Decoupling capacitor must be connected between this pins
and V

SS_LV_REGCOR

.

48 70

1.2 V decoupling pins for core logic and regulator feedback.

V

SS_LV_REGCOR

Decoupling capacitor must be connected between this pins
and V

DD_LV_REGCOR

.

49 71

ADC_0/ADC_1 reference and supply voltage. Pins available on 100-pin and 144-pin package.

V

DD_HV_ADC0

V

SS_HV_ADC0

V

DD_HV_ADC1

V

SS_HV_ADC1

(1)

ADC_0 supply and high reference voltage 33 50

ADC_0 ground and low reference voltage 34 51

ADC_1 supply and high reference voltage 39 56

ADC_1 ground and low reference voltage 40 57

Power supply pins (3.3 V or 5.0 V). All pins available on 144-pin package.

; VSS) available on 100-pin package.

DD

V

DD_HV_IO0

V

SS_HV_IO0

V

DD_HV_IO1

V

SS_HV_IO1

V

DD_HV_IO2

V

SS_HV_IO2

V

DD_HV_IO3

V

SS_HV_IO3

V

DD_HV_FL

V

SS_HV_FL

V

DD_HV_OSC

V

SS_HV_OSC

Five pairs (V

(2)

Input/Output supply voltage — 6

(2)

Input/Output ground — 7

Input/Output supply voltage 13 21

Input/Output ground 14 22

Input/Output supply voltage 63 91

Input/Output ground 62 90

Input/Output supply voltage 87 126

Input/Output ground 88 127

Code and data flash supply voltage 69 97

Code and data flash supply ground 68 96

Crystal oscillator amplifier supply voltage 16 27

Crystal oscillator amplifier ground 17 28

Power supply pins (1.2 V). All pins available on 100-pin and 144-pin package.

1.2 V Decoupling pins for core logic. Decoupling capacitor

V

DD_LV_COR0

must be connected between these pins and the nearest
V

SS_LV_COR

pin.

12 18

1.2 V Decoupling pins for core logic. Decoupling capacitor

V

SS_LV_COR0

must be connected between these pins and the nearest
V

DD_LV_COR

pin.

11 17

32/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Package pinouts and signal descriptions

Table 5. Supply pins (continued)

Supply Pin

Symbol Description 100-pin 144-pin

1.2 V Decoupling pins for core logic. Decoupling capacitor

V

DD_LV_COR1

must be connected between these pins and the nearest
V

SS_LV_COR

pin.

1.2 V Decoupling pins for core logic. Decoupling capacitor

V

SS_LV_COR1

must be connected between these pins and the nearest
V

DD_LV_COR

pin.

1.2 V Decoupling pins for core logic. Decoupling capacitor

V

DD_LV_COR2

must be connected between these pins and the nearest
V

SS_LV_COR

pin.

1.2 V Decoupling pins for core logic. Decoupling capacitor

V

SS_LV_COR2

must be connected between these pins and the nearest
V

DD_LV_COR

pin.

1.2 V Decoupling pins for on-chip PLL modules. Decoupling

V

DD_LV_COR3

capacitor must be connected between this pin and
V

SS_LV_COR3

.

1.2 V Decoupling pins for on-chip PLL modules. Decoupling

V

SS_LV_COR3

1. Analog supply/ground and high/low reference lines are internally physically separate, but are shorted via a double-bonding
connection on V

2. Not available on 100-pin package.

capacitor must be connected between this pin and
V

DD_LV_COR3

DD_HV_ADCx/VSS_HV_ADCx

.

pins.

65 93

66 94

92 131

93 132

25 36

24 35

2.2.2 System pins

Ta bl e 5 and Ta bl e 6 contain information on pin functions for the SPC560P44Lx,

SPC560P50Lx devices. The pins listed in Ta bl e 6 are single-function pins. The pins shown
in Ta bl e 7 are multi-function pins, programmable via their respective Pad Configuration
Register (PCR) values.

Table 6. System pins

Symbol Description Direction

MDO[0] Nexus Message Data Output—line 0 Output only Fast — 9

NMI Non-Maskable Interrupt Input only Slow — 1 1

XTAL

EXTAL

Dedicated pins. Available on 100-pin and 144-pin package.

Analog output of the oscillator amplifier
circuit; needs to be grounded if oscillator
is used in bypass mode

– Analog input of oscillator amplifier

circuit, when oscillator not in bypass
mode

– Analog input for clock generator when

oscillator in bypass mode

Pad speed

(1)

Pin

SRC = 0 SRC = 1 100-pin 144-pin

———1829

———1930

Doc ID 14723 Rev 8 33/115

Package pinouts and signal descriptions SPC560P44Lx, SPC560P50Lx

Table 6. System pins (continued)

Pad speed

Symbol Description Direction

SRC = 0 SRC = 1 100-pin 144-pin

TMS JTAG state machine control Bidirectional Slow Fast 59 87

TCK JTAG clock Input only Slow — 60 88

TDI Test Data In Input only Slow Medium 58 86

TDO Test Data Out Output only Slow Fast 61 89

Reset pin, available on 100-pin and 144-pin package.

RESET

VPP_TEST

1. SCR values refer to the value assigned to the Slew Rate Control bits of the pad configuration register.

Bidirectional reset with Schmitt trigger
characteristics and noise filter

Test pin, available on 100-pin and 144-pin package.

Pin for testing purpose only. To be tied
to ground in normal operating mode.

Bidirectional Medium — 20 31

———74107

(1)

Pin

2.2.3 Pin muxing

Ta bl e 7 defines the pin list and muxing for the SPC560P44Lx, SPC560P50Lx devices.

Each row of Ta bl e 7 shows all the possible ways of configuring each pin, via alternate
functions. The default function assigned to each pin after reset is the ALT0 function.

SPC560P44Lx, SPC560P50Lx devices provide four main I/O pad types, depending on the
associated functions:

● Slow pads are the most common, providing a compromise between transition time and

low electromagnetic emission.

● Medium pads provide fast enough transition for serial communication channels with

controlled current to reduce electromagnetic emission.

● Fast pads provide maximum speed. They are used for improved NEXUS debugging

capability.

● Symmetric pads are designed to meet FlexRay requirements.

Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at
the cost of reducing AC performance. For more information, see the datasheet’s “Pad AC
Specifications” section.

34/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Package pinouts and signal descriptions

Table 7. Pin muxing

Port

pin

Pad

configuration

register (PCR)

Alternate

function

A[0] PCR[0]

A[1] PCR[1]

(6)

(6)

(6)

PCR[2]

PCR[3]

PCR[4]

A[2]

A[3]

A[4]

(2)

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—
—
—

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

—
—

(1),

Functions Peripheral

Port A (16-bit)

GPIO[0]

ETC[0]

SCK

F[0]

EIRQ[0]

GPIO[1]

ETC[1]

SOUT

F[1]

EIRQ[1]

GPIO[2]

ETC[2]

—

A[3]

SIN

ABS[0]

EIRQ[2]

GPIO[3]

ETC[3]

CS0

B[3]

ABS[2]

EIRQ[3]

GPIO[4]

ETC[0]

CS1

ETC[4]

FAB

EIRQ[4]

SIUL

eTimer_0

DSPI_2

FCU_0

SIUL

SIUL

eTimer_0

DSPI_2

FCU_0

SIUL

SIUL

eTimer_0

—

FlexPWM_0

DSPI_2

MC_RGM

SIUL

SIUL

eTimer_0

DSPI_2

FlexPWM_0

MC_RGM

SIUL

SIUL

eTimer_1

DSPI_2

eTimer_0

MC_RGM

SIUL

(3)

I/O

direction

(4)

I/O
I/O

O
O

I

I/O
I/O

O
O

I

I/O
I/O

—

O

I
I
I

I/O
I/O
I/O

O

I
I

I/O
I/O

O

I/O

I
I

Pad speed

(5)

Pin No.

SRC = 0 SRC = 1

100-pin

Slow Medium 51 73

Slow Medium 52 74

Slow Medium 57 84

Slow Medium 64 92

Slow Medium 75 108

144-pin

A[5] PCR[5]

A[6] PCR[6]

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

GPIO[5]

CS0

ETC[5]

CS7

EIRQ[5]

GPIO[6]

SCK

—
—

EIRQ[6]

SIUL

DSPI_1

eTimer_1

DSPI_0

SIUL

SIUL

DSPI_1

—
—

SIUL

I/O
I/O
I/O

O

I/O
I/O

—
—

Slow Medium 8 14

I

Slow Medium 2 2

I

Doc ID 14723 Rev 8 35/115

Package pinouts and signal descriptions SPC560P44Lx, SPC560P50Lx

Table 7. Pin muxing (continued)

Port

pin

Pad

configuration

register (PCR)

A[7] PCR[7]

A[8] PCR[8]

Alternate

function

(2)

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—
—

(1),

Functions Peripheral

GPIO[7]

SOUT

—
—

EIRQ[7]

GPIO[8]

—
—
—

SIN

EIRQ[8]

SIUL

DSPI_1

—
—

SIUL

SIUL

—
—
—

DSPI_1

SIUL

(3)

I/O

direction

(4)

I/O

O
—
—

I

I/O

—
—
—

I
I

Pad speed

SRC = 0 SRC = 1

Slow Medium 4 10

Slow Medium 6 12

(5)

Pin No.

100-pin

144-pin

A[9] PCR[9]

A[10] PCR[10]

A[11] PCR[11]

A[12] PCR[12]

A[13] PCR[13]

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—
—
—

GPIO[9]

CS1

—

B[3]

FAULT[0]

GPIO[10]

CS0

B[0]
X[2]

EIRQ[9]

GPIO[11]

SCK

A[0]
A[2]

EIRQ[10]

GPIO[12]

SOUT

A[2]
B[2]

EIRQ[11]

GPIO[13]

—

B[2]

—

SIN

FAULT[0]

EIRQ[12]

SIUL

DSPI_2

—
FlexPWM_0
FlexPWM_0

SIUL

DSPI_2
FlexPWM_0
FlexPWM_0

SIUL

SIUL

DSPI_2
FlexPWM_0
FlexPWM_0

SIUL

SIUL

DSPI_2
FlexPWM_0
FlexPWM_0

SIUL

SIUL

—

FlexPWM_0

—

DSPI_2
FlexPWM_0

SIUL

I/O

O

—

O

I/O
I/O

O

I/O

I/O
I/O

O
O

I/O

O
O
O

I/O

—

O

—

Slow Medium 94 134

I

Slow Medium 81 118

I

Slow Medium 82 120

I

Slow Medium 83 122

I

Slow Medium 95 136
I
I
I

36/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Package pinouts and signal descriptions

Table 7. Pin muxing (continued)

Port

pin

Pad

configuration

register (PCR)

A[14] PCR[14]

A[15] PCR[15]

B[0] PCR[16]

B[1] PCR[17]

B[2] PCR[18]

B[3] PCR[19]

B[6] PCR[22]

Alternate

function

(2)

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

(1),

Functions Peripheral

GPIO[14]

TXD

ETC[4]

—

EIRQ[13]

GPIO[15]

—

ETC[5]

—

RXD

EIRQ[14]

Port B (16-bit)

GPIO[16]

TXD

ETC[2]

DEBUG[0]

EIRQ[15]

GPIO[17]

—

ETC[3]

DEBUG[1]

RXD

EIRQ[16]

GPIO[18]

TXD

—

DEBUG[2]

EIRQ[17]

GPIO[19]

—
—

DEBUG[3]

RXD

GPIO[22]

CLKOUT

CS2

—

EIRQ[18]

(3)

SIUL

Safety Port_0

eTimer_1

—

SIUL

SIUL

—

eTimer_1

—

Safety Port_0

SIUL

SIUL

FlexCAN_0

eTimer_1

SSCM

SIUL

SIUL

—

eTimer_1

SSCM

FlexCAN_0

SIUL

SIUL

LIN_0

—

SSCM

SIUL

SIUL

—
—

SSCM

LIN_0

SIUL

MC_CGL

DSPI_2

—

SIUL

I/O

direction

(4)

I/O

O

I/O

—

I

I/O

—

I/O

—

I
I

I/O

O

I/O

—

I

I/O

—

I/O

—

I
I

I/O

O
—
—

I

I/O

—
—
—

I

I/O

O

O
—

I

Pad speed

SRC = 0 SRC = 1

Slow Medium 99 143

Slow Medium 100 144

Slow Medium 76 109

Slow Medium 77 110

Slow Medium 79 114

Slow Medium 80 116

Slow Medium 96 138

(5)

Pin No.

100-pin

144-pin

Doc ID 14723 Rev 8 37/115

Package pinouts and signal descriptions SPC560P44Lx, SPC560P50Lx

Table 7. Pin muxing (continued)

Port

pin

Pad

configuration

register (PCR)

B[7] PCR[23]

Alternate

function

(2)

ALT0
ALT1
ALT2
ALT3

—
—

(1),

Functions Peripheral

GPIO[23]

—
—
—

AN[0]

RXD

SIUL

—
—
—

ADC_0

LIN_0

Pad speed

SRC = 0 SRC = 1

(3)

I/O

direction

(4)

Input only — — 29 43

(5)

Pin No.

100-pin

144-pin

B[8] PCR[24]

B[9] PCR[25]

B[10] PCR[26]

B[11] PCR[27]

B[12] PCR[28]

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

GPIO[24]

—
—
—

AN[1]

ETC[5]

GPIO[25]

—
—
—

AN[11]

GPIO[26]

—
—
—

AN[12]

GPIO[27]

—
—
—

AN[13]

GPIO[28]

—
—
—

AN[14]

SIUL

—
—
—

ADC_0

eTimer_0

SIUL

—
—
—

ADC_0 / ADC_1

SIUL

—
—
—

ADC_0 / ADC_1

SIUL

—
—
—

ADC_0 / ADC_1

SIUL

—
—
—

ADC_0 / ADC_1

Input only — — 31 47

Input only — — 35 52

Input only — — 36 53

Input only — — 37 54

Input only — — 38 55

SIUL

—
—
—

ADC_1

LIN_1

B[13] PCR[29]

ALT0
ALT1
ALT2
ALT3

—
—

GPIO[29]

—
—
—

AN[0]

RXD

38/115 Doc ID 14723 Rev 8

Input only — — 42 60

SPC560P44Lx, SPC560P50Lx Package pinouts and signal descriptions

Table 7. Pin muxing (continued)

Port

pin

Pad

configuration

register (PCR)

B[14] PCR[30]

B[15] PCR[31]

Alternate

function

(2)

ALT0
ALT1
ALT2
ALT3

—
—
—

ALT0
ALT1
ALT2
ALT3

—
—

(1),

Functions Peripheral

GPIO[30]

—
—
—

AN[1]

ETC[4]

EIRQ[19]

GPIO[31]

—
—
—

AN[2]

EIRQ[20]

Port C (16-bit)

SIUL

—
—
—

ADC_1

eTimer_0

SIUL

SIUL

—
—
—

ADC_1

SIUL

Pad speed

SRC = 0 SRC = 1

(3)

I/O

direction

(4)

Input only — — 44 64

Input only — — 43 62

(5)

Pin No.

100-pin

144-pin

C[0] PCR[32]

C[1] PCR[33]

C[2] PCR[34]

C[3] PCR[35]

C[4] PCR[36]

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

GPIO[32]

—
—
—

AN[3]

GPIO[33]

—
—
—

AN[2]

GPIO[34]

—
—
—

AN[3]

GPIO[35]

CS1

ETC[4]

TXD

EIRQ[21]

GPIO[36]

CS0

X[1]

DEBUG[4]

EIRQ[22]

SIUL

—
—
—

ADC_1

SIUL

—
—
—

ADC_0

SIUL

—
—
—

ADC_0

SIUL

DSPI_0

eTimer_1

LIN_1

SIUL

SIUL

DSPI_0

FlexPWM_0

SSCM

SIUL

Input only — — 45 66

Input only — — 28 41

Input only — — 30 45

I/O

O

I/O

Slow Medium 10 16

O

I

I/O
I/O
I/O

Slow Medium 5 11

—

I

Doc ID 14723 Rev 8 39/115

Package pinouts and signal descriptions SPC560P44Lx, SPC560P50Lx

Table 7. Pin muxing (continued)

Port

pin

Pad

configuration

register (PCR)

C[5] PCR[37]

Alternate

function

(2)

ALT0
ALT1
ALT2
ALT3

—
—

(1),

Functions Peripheral

GPIO[37]

SCK

—

DEBUG[5]

FAULT[3]

EIRQ[23]

SIUL

DSPI_0

—

SSCM

FlexPWM_0

SIUL

(3)

I/O

direction

(4)

I/O
I/O

—
—

I
I

Pad speed

SRC = 0 SRC = 1

Slow Medium 7 13

(5)

Pin No.

100-pin

144-pin

C[6] PCR[38]

C[7] PCR[39]

C[8] PCR[40]

C[9] PCR[41]

C[10] PCR[42]

C[11] PCR[43]

C[12] PCR[44]

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

GPIO[38]

SOUT

B[1]

DEBUG[6]

EIRQ[24]

GPIO[39]

—

A[1]

DEBUG[7]

SIN

GPIO[40]

CS1

—

CS6

FAULT[2]

GPIO[41]

CS3

—

X[3]

FAULT[2]

GPIO[42]

CS2

—

A[3]

FAULT[1]

GPIO[43]

ETC[4]

CS2
CS0

GPIO[44]

ETC[5]

CS3
CS1

SIUL

DSPI_0

FlexPWM_0

SSCM

SIUL

SIUL

—

FlexPWM_0

SSCM

DSPI_0

SIUL

DSPI_1

—

DSPI_0

FlexPWM_0

SIUL

DSPI_2

—
FlexPWM_0
FlexPWM_0

SIUL

DSPI_2

—
FlexPWM_0
FlexPWM_0

SIUL

eTimer_0

DSPI_2
DSPI_3

SIUL

eTimer_0

DSPI_2
DSPI_3

I/O
I/O

O

—

I/O

—

O

—

I/O

O

—

O

I/O

O

—

I/O

I/O

O

—

O

I/O
I/O

O

I/O

I/O
I/O

O
O

Slow Medium 98 142

I

Slow Medium 9 15

I

Slow Medium 91 130

I

Slow Medium 84 123

I

Slow Medium 78 111

I

Slow Medium 55 80

Slow Medium 56 82

40/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Package pinouts and signal descriptions

Table 7. Pin muxing (continued)

Port

pin

Pad

configuration

register (PCR)

C[13] PCR[45]

Alternate

function

(2)

ALT0
ALT1
ALT2
ALT3

—
—

(1),

Functions Peripheral

GPIO[45]

ETC[1]

—
—

EXT_IN

EXT_SYNC

SIUL

eTimer_1

—

—

CTU_0

FlexPWM_0

(3)

I/O

direction

(4)

I/O
I/O

—
—

I
I

Pad speed

SRC = 0 SRC = 1

Slow Medium 71 101

(5)

Pin No.

100-pin

144-pin

C[14] PCR[46]

C[15] PCR[47]

D[0] PCR[48]

D[1] PCR[49]

D[2] PCR[50]

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

GPIO[46]

ETC[2]

EXT_TGR

—

GPIO[47]

CA_TR_EN

ETC[0]

A[1]

EXT_IN

EXT_SYNC

GPIO[48]

CA_TX
ETC[1]

B[1]

GPIO[49]

—

ETC[2]

EXT_TRG

CA_RX

GPIO[50]

—

ETC[3]

X[3]

CB_RX

SIUL

eTimer_1

CTU_0

—

SIUL

FlexRay_0

eTimer_1

FlexPWM_0

CTU_0

FlexPWM_0

Port D (16-bit)

SIUL

FlexRay_0

eTimer_1

FlexPWM_0

SIUL

—

eTimer_1

CTU_0

FlexRay_0

SIUL

—

eTimer_1

FlexPWM_0

FlexRay_0

I/O
I/O

O

—

I/O

O

I/O

O

I/O

O

I/O

O

I/O

—

I/O

O

I/O

—
I/O
I/O

Slow Medium 72 103

Slow Symmetric 85 124

I
I

Slow Symmetric 86 125

Slow Medium 3 3

I

Slow Medium 97 140

I

D[3] PCR[51]

D[4] PCR[52]

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

GPIO[51]

CB_TX
ETC[4]

A[3]

GPIO[52]

CB_TR_EN

ETC[5]

B[3]

SIUL

FlexRay_0

eTimer_1

FlexPWM_0

SIUL

FlexRay_0

eTimer_1

FlexPWM_0

I/O

O

I/O

O

I/O

O

I/O

O

Slow Symmetric 89 128

Slow Symmetric 90 129

Doc ID 14723 Rev 8 41/115

Package pinouts and signal descriptions SPC560P44Lx, SPC560P50Lx

Table 7. Pin muxing (continued)

Port

pin

Pad

configuration

register (PCR)

D[5] PCR[53]

D[6] PCR[54]

D[7] PCR[55]

Alternate

function

(2)

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

(1),

Functions Peripheral

GPIO[53]

CS3

F[0]

SOUT

GPIO[54]

CS2
SCK

—

FAULT[1]

GPIO[55]

CS3

F[1]

CS4

SIN

SIUL

DSPI_0

FCU_0

DSPI_3

SIUL
DSPI_0
DSPI_3

—

FlexPWM_0

SIUL
DSPI_1

FCU_0
DSPI_0
DSPI_3

(3)

I/O

direction

(4)

I/O

O
O
O

I/O

O

I/O

—

I

I/O

O
O
O

I

Pad speed

SRC = 0 SRC = 1

Slow Medium 22 33

Slow Medium 23 34

Slow Medium 26 37

(5)

Pin No.

100-pin

144-pin

D[8] PCR[56]

D[9] PCR[57]

D[10] PCR[58]

D[11] PCR[59]

D[12] PCR[60]

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

—

GPIO[56]

CS2

—

CS5

FAULT[3]

GPIO[57]

X[0]

TXD

—

GPIO[58]

A[0]

CS0

—

GPIO[59]

B[0]
CS1
SCK

GPIO[60]

X[1]

—
—

RXD

SIUL

DSPI_1

—

DSPI_0

FlexPWM_0

SIUL

FlexPWM_0

LIN_1

—

SIUL

FlexPWM_0

DSPI_3

—

SIUL

FlexPWM_0

DSPI_3
DSPI_3

SIUL

FlexPWM_0

—
—

LIN_1

I/O

O

—

O

I/O
I/O

O

—

I/O

O

I/O

—

I/O

O
O

I/O

I/O
I/O

—
—

Slow Medium 21 32

I

Slow Medium 15 26

Slow Medium 53 76

Slow Medium 54 78

Slow Medium 70 99

I

D[13] PCR[61]

ALT0
ALT1
ALT2
ALT3

GPIO[61]

A[1]
CS2

SOUT

SIUL

FlexPWM_0

DSPI_3
DSPI_3

42/115 Doc ID 14723 Rev 8

I/O

O
O
O

Slow Medium 67 95

SPC560P44Lx, SPC560P50Lx Package pinouts and signal descriptions

Table 7. Pin muxing (continued)

Port

pin

Pad

configuration

register (PCR)

D[14] PCR[62]

D[15] PCR[63]

Alternate

function

(2)

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

(1),

Functions Peripheral

GPIO[62]

B[1]
CS3

—

SIN

GPIO[63]

—
—
—

AN[4]

Port E(16-bit)

SIUL

FlexPWM_0

DSPI_3

—

DSPI_3

SIUL

—
—
—

ADC_1

Pad speed

SRC = 0 SRC = 1

(3)

I/O

direction

(4)

I/O

O
O

Slow Medium 73 105

—

I

Input only — — 41 58

(5)

Pin No.

100-pin

144-pin

E[0] PCR[64]

E[1] PCR[65]

E[2] PCR[66]

E[3] PCR[67]

E[4] PCR[68]

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

GPIO[64]

—
—
—

AN[5]

GPIO[65]

—
—
—

AN[4]

GPIO[66]

—
—
—

AN[5]

GPIO[67]

—
—
—

AN[6]

GPIO[68]

—
—
—

AN[7]

SIUL

—
—
—

ADC_1

SIUL

—
—
—

ADC_0

SIUL

—
—
—

ADC_0

SIUL

—
—
—

ADC_0

SIUL

—
—
—

ADC_0

Input only — — 46 68

Input only — — 27 39

Input only — — 32 49

Input only — — — 40

Input only — — — 42

Doc ID 14723 Rev 8 43/115

Package pinouts and signal descriptions SPC560P44Lx, SPC560P50Lx

Table 7. Pin muxing (continued)

Port

pin

Pad

configuration

register (PCR)

E[5] PCR[69]

E[6] PCR[70]

E[7] PCR[71]

E[8] PCR[72]

E[9] PCR[73]

E[10] PCR[74]

E[11] PCR[75]

E[12] PCR[76]

Alternate

function

(2)

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

(1),

Functions Peripheral

GPIO[69]

—
—
—

AN[8]

GPIO[70]

—
—
—

AN[9]

GPIO[71]

—
—
—

AN[10]

GPIO[72]

—
—
—

AN[6]

GPIO[73]

—
—
—

AN[7]

GPIO[74]

—
—
—

AN[8]

GPIO[75]

—
—
—

AN[9]

GPIO[76]

—
—
—

AN[10]

SIUL

—
—
—

ADC_0

SIUL

—
—
—

ADC_0

SIUL

—
—
—

ADC_0

SIUL

—
—
—

ADC_1

SIUL

—
—
—

ADC_1

SIUL

—
—
—

ADC_1

SIUL

—
—
—

ADC_1

SIUL

—
—
—

ADC_1

Pad speed

SRC = 0 SRC = 1

(3)

I/O

direction

(4)

Input only — — — 44

Input only — — — 46

Input only — — — 48

Input only — — — 59

Input only — — — 61

Input only — — — 63

Input only — — — 65

Input only — — — 67

(5)

Pin No.

100-pin

144-pin

44/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Package pinouts and signal descriptions

Table 7. Pin muxing (continued)

Port

pin

Pad

configuration

register (PCR)

E[13] PCR[77]

E[14] PCR[78]

E[15] PCR[79]

F[0] PCR[80]

F[1] PCR[81]

F[2] PCR[82]

Alternate

function

(2)

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

(1),

Functions Peripheral

GPIO[77]

SCK

—
—

EIRQ[25]

GPIO[78]

SOUT

—
—

EIRQ[26]

GPIO[79]

—
—
—

SIN

EIRQ[27]

Port F (16-bit)

GPIO[80]

DBG0

CS3

—

EIRQ[28]

GPIO[81]

DBG1

CS2

—

EIRQ[29]

GPIO[82]

DBG2

CS1

—

SIUL

DSPI_3

—
—

SIUL

SIUL

DSPI_3

—
—

SIUL

SIUL

—
—
—

DSPI_3

SIUL

SIUL

FlexRay_0

DSPI_3

—

SIUL

SIUL

FlexRay_0

DSPI_3

—

SIUL

SIUL

FlexRay_0

DSPI_3

—

(3)

I/O

direction

(4)

I/O
I/O

—
—

I

I/O

O
—
—

I

I/O

—
—
—

I
I

I/O

O

O
—

I

I/O

O

O
—

I

I/O

O

O
—

Pad speed

SRC = 0 SRC = 1

Slow Medium — 117

Slow Medium — 119

Slow Medium — 121

Slow Medium — 133

Slow Medium — 135

Slow Medium — 137

(5)

Pin No.

100-pin

144-pin

F[3] PCR[83]

F[4] PCR[84]

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

GPIO[83]

DBG3

CS0

—

GPIO[84]

MDO[3]

—
—

SIUL

FlexRay_0

DSPI_3

—

SIUL

NEXUS_0

—
—

I/O

O

I/O

—

I/O

O
—
—

Slow Medium — 139

Slow Fast — 4

Doc ID 14723 Rev 8 45/115

Package pinouts and signal descriptions SPC560P44Lx, SPC560P50Lx

Table 7. Pin muxing (continued)

Port

pin

Pad

configuration

register (PCR)

F[5] PCR[85]

F[6] PCR[86]

Alternate

function

(2)

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

(1),

Functions Peripheral

GPIO[85]

MDO[2]

—
—

GPIO[86]

MDO[1]

—
—

SIUL

NEXUS_0

—
—

SIUL

NEXUS_0

—
—

(3)

I/O

direction

(4)

I/O

O
—
—

I/O

O
—
—

Pad speed

SRC = 0 SRC = 1

Slow Fast — 5

Slow Fast — 8

(5)

Pin No.

100-pin

144-pin

F[7] PCR[87]

F[8] PCR[88]

F[9] PCR[89]

F[10] PCR[90]

F[11] PCR[91]

F[12] PCR[92]

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

GPIO[87]

MCKO

—
—

GPIO[88]

MSEO1

—
—

GPIO[89]

MSEO0

—
—

GPIO[90]

EVTO

—
—

GPIO[91]

—
—
—

EVTI

GPIO[92]

ETC[3]

—
—

SIUL

NEXUS_0

—
—

SIUL

NEXUS_0

—
—

SIUL

NEXUS_0

—
—

SIUL

NEXUS_0

—
—

SIUL

—
—
—

NEXUS_0

SIUL

eTimer_1

—
—

I/O

O
—
—

I/O

O
—
—

I/O

O
—
—

I/O

O
—
—

I/O

—
—
—

I/O
I/O

—
—

Slow Fast — 19

Slow Fast — 20

Slow Fast — 23

Slow Fast — 24

Slow Medium — 25

I

Slow Medium — 106

F[13] PCR[93]

ALT0
ALT1
ALT2
ALT3

GPIO[92]

ETC[4]

—
—

SIUL

eTimer_1

—
—

46/115 Doc ID 14723 Rev 8

I/O
I/O

—
—

Slow Medium — 112

SPC560P44Lx, SPC560P50Lx Package pinouts and signal descriptions

Table 7. Pin muxing (continued)

Port

pin

Pad

configuration

register (PCR)

F[14] PCR[94]

F[15] PCR[95]

Alternate

function

(2)

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

—

(1),

Functions Peripheral

GPIO[94]

TXD

—
—

GPIO[95]

—
—
—

RXD

Port G (12-bit)

SIUL

LIN_1

—
—

SIUL

—
—
—

LIN_1

(3)

I/O

direction

(4)

I/O

O
—
—

I/O

—
—
—

I

Pad speed

SRC = 0 SRC = 1

Slow Medium — 115

Slow Medium — 113

(5)

Pin No.

100-pin

144-pin

G[0] PCR[96]

G[1] PCR[97]

G[2] PCR[98]

G[3] PCR[99]

G[4] PCR[100]

G[5] PCR[101]

G[6] PCR[102]

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

GPIO[96]

F[0]

—
—

EIRQ[30]

GPIO[97]

F[1]

—
—

EIRQ[31]

GPIO[98]

X[2]

—
—

GPIO[99]

A[2]

—
—

GPIO[100]

B[2]

—
—

GPIO[101]

X[3]

—
—

GPIO[102]

A[3]

—
—

SIUL

FCU_0

—
—

SIUL

SIUL

FCU_0

—
—

SIUL

SIUL

FlexPWM_0

—
—

SIUL

FlexPWM_0

—
—

SIUL

FlexPWM_0

—
—

SIUL

FlexPWM_0

—
—

SIUL

FlexPWM_0

—
—

I/O

O
—
—

I/O

O
—
—

I/O
I/O

—
—

I/O

O
—
—

I/O

O
—
—

I/O
I/O

—
—

I/O

O
—
—

Slow Medium — 38

I

Slow Medium — 141

I

Slow Medium — 102

Slow Medium — 104

Slow Medium — 100

Slow Medium — 85

Slow Medium — 98

Doc ID 14723 Rev 8 47/115

Package pinouts and signal descriptions SPC560P44Lx, SPC560P50Lx

Table 7. Pin muxing (continued)

Port

pin

Pad

configuration

register (PCR)

G[7] PCR[103]

G[8] PCR[104]

G[9] PCR[105]

Alternate

function

(2)

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

(1),

Functions Peripheral

GPIO[103]

B[3]

—
—

GPIO[104]

—
—
—

FAULT[0]

GPIO[105]

—
—
—

FAULT[1]

SIUL

FlexPWM_0

—
—

SIUL

—
—
—

FlexPWM_0

SIUL

—
—
—

FlexPWM_0

(3)

I/O

direction

(4)

I/O

O
—
—

I/O

—
—
—

I

I/O

—
—
—

I

Pad speed

SRC = 0 SRC = 1

Slow Medium — 83

Slow Medium — 81

Slow Medium — 79

(5)

Pin No.

100-pin

144-pin

ALT0
ALT1

G[10] PCR[106]

ALT2
ALT3

—

ALT0
ALT1

G[11] PCR[107]

ALT2
ALT3

—

1. ALT0 is the primary (default) function for each port after reset.

2. Alternate functions are chosen by setting the values of the PCR[PA] bitfields inside the SIU module.
PCR[PA] = 00  ALT0; PCR[PA] = 01  ALT1; PCR[PA] = 10  ALT2; PCR[PA] = 11  ALT3. This is intended to select
the output functions; to use one of the input-only functions, the PCR[IBE] bit must be written to ‘1’, regardless of the values
selected in the PCR[PA] bitfields. For this reason, the value corresponding to an input only function is reported as “—”.

3. Module included on the MCU.

4. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the
values of the PSMI[PADSELx] bitfields inside the SIUL module.

5. Programmable via the SRC (Slew Rate Control) bits in the respective Pad Configuration Register.

6. Weak pull down during reset.

GPIO[106]

—
—
—

FAULT[2]

GPIO[107]

—
—
—

FAULT[3]

SIUL

—
—
—

FlexPWM_0

SIUL

—
—
—

FlexPWM_0

I/O

—
—
—

I/O

—
—
—

Slow Medium — 77

I

Slow Medium — 75

I

48/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Electrical characteristics

3 Electrical characteristics

3.1 Introduction

This section contains device electrical characteristics as well as temperature and power
considerations.

This microcontroller contains input protection against damage due to high static voltages.
However, it is advisable to take precautions to avoid application of any voltage higher than
the specified maximum rated voltages.

To enhance reliability, unused inputs can be driven to an appropriate logic voltage level
(V

or VSS). This can be done by the internal pull-up or pull-down resistors, which are

DD

provided by the device for most general purpose pins.

The following tables provide the device characteristics and its demands on the system.

In the tables where the device logic provides signals with their respective timing
characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol
column.

In the tables where the external system must provide signals with their respective timing
characteristics to the device, the symbol “SR” for System Requirement is included in the
Symbol column.

Caution: All of the following parameter values can vary depending on the application and must be

confirmed during silicon characterization or silicon reliability trial.

3.2 Parameter classification

The electrical parameters are guaranteed by various methods. To give the customer a
better understanding, the classifications listed in Ta b le 8 are used and the parameters are
tagged accordingly in the tables where appropriate.

Table 8. Parameter classifications

Classification tag Tag description

Note: The classification is shown in the column labeled “C” in the parameter tables where

P Those parameters are guaranteed during production testing on each individual device.

C

T

D Those parameters are derived mainly from simulations.

Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.

Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical
column are within this category.

appropriate.

Doc ID 14723 Rev 8 49/115

Electrical characteristics SPC560P44Lx, SPC560P50Lx

3.3 Absolute maximum ratings

Table 9. Absolute maximum ratings

(1)

Symbol Parameter Conditions

V

SS

V

DD_HV_IOx

V

SS_HV_IOx

SR Device ground — 0 0 V

(3)

3.3 V / 5.0 V input/output supply

SR

voltage with respect to ground (V

Input/output ground voltage with

SR

respect to ground (V

SS

)

SS

)

3.3 V / 5.0 V code and data flash

V

DD_HV_FL

SR

supply voltage with respect to ground
(VSS)

Code and data flash ground with

V

SS_HV_FL

SR

respect to ground (V

SS

)

3.3 V / 5.0 V crystal oscillator

SR

V

DD_HV_OSC

amplifier supply voltage with respect
to ground (VSS)

3.3 V / 5.0 V crystal oscillator

V

SS_HV_OSC

SR

amplifier reference voltage with
respect to ground (VSS)

Val ue

Min Max

— –0.3 6.0 V

— –0.1 0.1 V

—

Relative to
V

DD_HV_IOx

–0.3

V

DD_HV_IOx

— –0.1 0.1 V

—

Relative to
V

DD_HV_IOx

–0.3

V

DD_HV_IOx

— –0.1 0.1 V

6.0

6.0

(2)

+ 0.3

+ 0.3

Unit

V

V

V

DD_HV_REG

V

DD_HV_ADC0

(4)

V

SS_HV_ADC0

V

DD_HV_ADC1

4)

V

SS_HV_ADC1

TV

DD

V

IN

3.3 V / 5.0 V voltage regulator supply

SR

voltage with respect to ground (V

3.3 V / 5.0 V ADC_0 supply and high

SR

reference voltage with respect to
ground (VSS)

ADC_0 ground and low reference

SR

voltage with respect to ground (V

3.3 V / 5.0 V ADC_0 supply and high

(

SR

reference voltage with respect to
ground (VSS)

ADC_1 ground and low reference

SR

voltage with respect to ground (V

Slope characteristics on all VDD

SR

during power up

(5)

with respect to

ground (VSS)

Voltage on any pin with respect to

SR

ground (V

SS_HV_IOx

) with respect to

ground (VSS)

SS

SS

SS

)

)

)

—

Relative to
V

DD_HV_IOx

V

DD_HV_REG

<

–0.3

V

DD_HV_IOx

V

DD_HV_REG

2.7 V
–0.3

V

DD_HV_REG

>

2.7 V

— –0.1 0.1 V

V

DD_HV_REG

<

V

DD_HV_REG

2.7 V
–0.3

V

DD_HV_REG

>

2.7 V

— –0.1 0.1 V

—3.0

500 x 10

(0.5 [V/µs])

—

Relative to
V

DD_HV_IOx

–0.3

V

DD_HV_IOx

6.0

0.3

6.0

0.3

6.0

6.0

+ 0.3

+

+

3

+0.3

V

V

V

V/s

V

50/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Electrical characteristics

Table 9. Absolute maximum ratings

(1)

(continued)

Val ue

Symbol Parameter Conditions

Min Max

V

DD_HV_REG

V

INAN0

ADC0 and shared ADC0/1 analog

SR

input voltage

(6)

2.7 V

V

DD_HV_REG

2.7 V

V

DD_HV_REG

V

INAN1

SR ADC1 analog input voltage

(7)

2.7 V

V

DD_HV_REG

2.7 V

I

INJPAD

I

INJSUM

I

VDD_LV

T

STG

T

J

1. Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress ratings
only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device
reliability or cause permanent damage to the device.

2. Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress
have not yet been determined.

3. The difference between each couple of voltage supplies must be less than 300 mV,
|V

DD_HV_IOy

4. The difference between ADC voltage supplies must be less than 100 mV, |V

5. Guaranteed by device validation

6. Not allowed to refer this voltage to V

7. Not allowed to refer this voltage to V

Injected input current on any pin

SR

during overload condition

Absolute sum of all injected input

SR

currents during overload condition

Low voltage static current sink

SR

through V

DD_LV

SR Storage temperature — –55 150 °C

SR Junction temperature under bias — –40 150 °C

– V

DD_HV_IOx

| < 300 mV.

DD_HV_ADV1

DD_HV_ADV0

, V

SS_HV_ADV1

, V

SS_HV_ADV0

>

V

SS_HV_ADV0



V

0.3

<

>

V

V

SS_HV_ADV0

SS_HV_ADV1



V

V

0.3

<

V

SS_HV_ADV1

V

— –10 10 mA

— –50 50 mA

— — 155 mA

DD_HV_ADC1

– V

DD_HV_ADC0

(2)

DD_HV_ADV0

0.3

DD_HV_ADV0

DD_HV_ADV1

0.3

DD_HV_ADV1

| < 100 mV.

+

+

Unit

V

V

V

V

Figure 5 shows the constraints of the different power supplies.

Doc ID 14723 Rev 8 51/115

Electrical characteristics SPC560P44Lx, SPC560P50Lx

VDD_HV_xxx

VDD_HV_IOx

–0.3 V

6.0 V

–0.3 V

6.0 V

VDD_HV_ADCx

6.0 V

VDD_HV_REG

–0.3 V

2.7 V

–0.3 V

6.0 V

Figure 5. Power supplies constraints (–0.3 V  V

DD_HV_IOx

 6.0 V)

The SPC560P44Lx, SPC560P50Lx supply architecture allows of having ADC supply
managed independently from standard V

supply. Figure 6 shows the constraints of the

DD_HV

ADC power supply.

Figure 6. Independent ADC supply (–0.3 V  V

52/115 Doc ID 14723 Rev 8

DD_HV_REG

 6.0 V)

SPC560P44Lx, SPC560P50Lx Electrical characteristics

3.4 Recommended operating conditions

Table 10. Recommended operating conditions (5.0 V)

Symbol Parameter Conditions

V

SS

V

DD_HV_IOx

V

SS_HV_IOx

SR Device ground — 0 0 V

(2)

5.0 V input/output supply

SR

voltage

—4.5 5.5V

SR Input/output ground voltage — 0 0 V

—4.5 5.5

5.0 V code and data flash

V

DD_HV_FL

V

SS_HV_FL

SR

supply voltage

Relative to
V

DD_HV_IOx

SR Code and data flash ground — 0 0 V

—4.5 5.5

5.0 V crystal oscillator amplifier

V

DD_HV_OSC

V

SS_HV_OSC

SR

supply voltage

5.0 V crystal oscillator amplifier

SR

reference voltage

Relative to
V

DD_HV_IOx

—0 0V

—4.5 5.5

V

DD_HV_REG

5.0 V voltage regulator supply

SR

voltage

Relative to
V

DD_HV_IOx

—4.5 5.5

V

DD_HV_ADC0

V

SS_HV_ADC0

(3)

5.0 V ADC_0 supply and high

SR

reference voltage

ADC_0 ground and low

SR

reference voltage

Relative to
V

DD_HV_REG

—0 0V

—4.5 5.5

V

DD_HV_ADC1

V

SS_HV_ADC1

V

DD_LV_REGCOR

(5)

(3)

(4),

5.0 V ADC_1 supply and high

SR

reference voltage

ADC_1 ground and low

SR

reference voltage

Relative to
V

DD_HV_REG

—0 0V

CC Internal supply voltage — — — V

Min Max

V

DD_HV_IOx

V

DD_HV_IOx

V

DD_HV_IOx

V

DD_HV_REG

V

DD_HV_REG

– 0.1 V

– 0.1 V

– 0.1 V

– 0.1 —

– 0.1 —

Value

DD_HV_IOx

DD_HV_IOx

DD_HV_IOx

(1)

Unit

V

+0.1

V

+0.1

V

+0.1

V

V

V

SS_LV_REGCOR

V

DD_LV_CORx

V

SS_LV_CORx

T

1. Parametric figures can be out of specification when voltage drops below 4.5 V, however, guaranteeing the full functionality.
In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed.

2. The difference between each couple of voltage supplies must be less than 100 mV, |V

(4)

SR Internal reference voltage — 0 0 V

(4),(5)

CC Internal supply voltage — — — V

(4)

SR Internal reference voltage — 0 0 V

f

= 64 MHz –40 105

Ambient temperature under

A

SR

bias

CPU

= 60 MHz –40 125

f

CPU

DD_HV_IOy

– V

DD_HV_IOx

| < 100 mV.

Doc ID 14723 Rev 8 53/115

°C

Electrical characteristics SPC560P44Lx, SPC560P50Lx

3. The difference between ADC voltage supplies must be less than 100 mV, |V

4. To be connected to emitter of external NPN. Low voltage supplies are not under user control—they are produced by an on­chip voltage regulator—but for the device to function properly the low voltage grounds (V
voltage grounds (V
emitter.

5. The low voltage supplies (V

V

DD_LV_COR1

and V

SS_HV_xxx

DD_LV_COR2

voltage supply to the data flash module. Similarly, V

V

DD_LV_REGCOR

Table 11. Recommended operating conditions (3.3 V)

and V

) and the low voltage supply pins (V

DD_LV_xxx

) are not all independent.

are shorted internally via double bonding connections with lines that provide the low

DD_LV_REGCORx

are physically shorted internally, as are V

DD_LV_xxx

SS_LV_COR1

DD_HV_ADC1

) must be connected to the external ballast

and V

 V

SS_LV_xxx

SS_LV_COR2

SS_LV_REGCOR

DD_HV_ADC0

| < 100 mV.

) must be shorted to high

are internally shorted.

and V

SS_LV_CORx

Val ue

Symbol Parameter Conditions

V

SS

V

DD_HV_IOx

V

SS_HV_IOx

SR Device ground — 0 0 V

(2)

3.3 V input/output supply

SR

voltage

SR Input/output ground voltage — 0 0 V

Min Max

—3.0 3.6V

(1)

—3.0 3.6

3.3 V code and data flash

V

DD_HV_FL

V

SS_HV_FL

SR

supply voltage

Relative to
V

DD_HV_IOx

V

DD_HV_IOx

– 0.1 V

DD_HV_IOx

+0.1

SR Code and data flash ground — 0 0 V

—3.0 3.6

V

DD_HV_OSC

V

SS_HV_OSC

3.3 V crystal oscillator amplifier

SR

supply voltage

3.3 V crystal oscillator amplifier

SR

reference voltage

Relative to
V

DD_HV_IOx

V

DD_HV_IOx

– 0.1 V

DD_HV_IOx

+0.1

—0 0V

.

Unit

V

V

V

DD_HV_REG

3.3 V voltage regulator supply

SR

voltage

Relative to
V

DD_HV_IOx

—3.0 5.5

—3.0 3.6

V

DD_HV_ADC0

V

SS_HV_ADC0

(3)

3.3 V ADC_0 supply and high

SR

reference voltage

ADC_0 ground and low

SR

reference voltage

Relative to
V

DD_HV_REG

—0 0V

—3.0 5.5

V

DD_HV_ADC1

V

SS_HV_ADC1

V

DD_LV_REGCOR

(5)

V

SS_LV_REGCOR

V

DD_LV_CORx

(3)

(4),

(4)

(4),(5)

3.3 V ADC_1 supply and high

SR

reference voltage

ADC_1 ground and low

SR

reference voltage

Relative to
V

DD_HV_REG

—0 0V

CC Internal supply voltage — — — V

SR Internal reference voltage — 0 0 V

CC Internal supply voltage — — — V

54/115 Doc ID 14723 Rev 8

V

DD_HV_IOx

V

DD_HV_REG

V

DD_HV_REG

– 0.1 V

DD_HV_IOx

– 0.1 5.5

– 0.1 5.5

+0.1

V

V

V

SPC560P44Lx, SPC560P50Lx Electrical characteristics

VDD_HV_xxx

VDD_HV_IOx

3.0 V

5.5 V

3.0 V

5.5 V

3.3 V

3.3 V

Note: IO AC and DC characteristics are guaranteed only in the range of 3.0–3.6 V when
PAD3V5V is low, and in the range of 4.5–5.5 V when PAD3V5V is high.

Table 11. Recommended operating conditions (3.3 V) (continued)

Val ue

Symbol Parameter Conditions

V

SS_LV_CORx

(4)

SR Internal reference voltage — 0 0 V

T

A

Ambient temperature under

SR

bias

f

f

Min Max

= 64 MHz –40 105

CPU

= 60 MHz –40 125

CPU

(1)

1. Parametric figures can be out of specification when voltage drops below 4.5 V, however, guaranteeing the full functionality.
In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed.

2. The difference between each couple of voltage supplies must be less than 100 mV, |V

3. The difference between each couple of voltage supplies must be less than 100 mV, |V
mV. As long as that condition is met, ADC_0 and ADC_1 can be operated at 5 V with the rest of the device operating at 3.3
V.

4. To be connected to emitter of external NPN. Low voltage supplies are not under user control—they are produced by an on­chip voltage regulator—but for the device to function properly the low voltage grounds (V
voltage grounds (V
emitter.

SS_HV_xxx

5. The low voltage supplies (V

V

DD_LV_COR1

and V

DD_LV_COR2

voltage supply to the data flash module. Similarly, V

V

DD_LV_REGCOR

and V

) and the low voltage supply pins (V

DD_LV_xxx

) are not all independent.

are shorted internally via double bonding connections with lines that provide the low

DD_LV_REGCORx

are physically shorted internally, as are V

DD_LV_xxx

SS_LV_COR1

) must be connected to the external ballast

and V

DD_HV_IOy

DD_HV_ADC1

SS_LV_COR2

SS_LV_REGCOR

– V

DD_HV_IOx

– V

SS_LV_xxx

) must be shorted to high

are internally shorted.

| < 100 mV.

DD_HV_ADC0

and V

SS_LV_CORx

Unit

°C

| < 100

.

Figure 7 shows the constraints of the different power supplies.

Figure 7. Power supplies constraints (3.0 V  V

DD_HV_IOx

Doc ID 14723 Rev 8 55/115

 5.5 V)

Electrical characteristics SPC560P44Lx, SPC560P50Lx

5.5 V

3.0 V

VDD_HV_REG

3.0 V

5.5 V

VDD_HV_ADCx

The SPC560P44Lx, SPC560P50Lx supply architecture allows the ADC supply to be
managed independently from the standard V

supply. Figure 8 shows the constraints of

DD_HV

the ADC power supply.

Figure 8. Independent ADC supply (3.0 V  V

3.5 Thermal characteristics

3.5.1 Package thermal characteristics

Table 12. Thermal characteristics for 144-pin LQFP

Symbol Parameter Conditions

Thermal resistance junction-to-ambient,

JA

natural convection

Thermal resistance junction-to-board

JB

Thermal resistance junction-to-case

(3)

(top)

Junction-to-board, natural convection

JB

Junction-to-case, natural convection

JC

(1)

R

R

R

JCtop





1. Junction-to-ambient thermal resistance determined per JEDEC JESD51-7. Thermal test board meets
JEDEC specification for this package.

(5)

DD_HV_REG

 5.5 V)

Single layer board—1s 54.2

Four layer board—2s2p 44.4

(2)

Four layer board—2s2p 29.9

Single layer board—1s 9.3

(4)

Operating conditions 30.2

Operating conditions 0.8

Typical

value

Unit

°C/

W

°C/

W

°C/

W

°C/

W

°C/

W

°C/

W

56/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Electrical characteristics

2. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.

3. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the
interface layer.

4. Thermal characterization parameter indicating the temperature difference between the board and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal
characterization parameter is written as Psi-JB.

5. Thermal characterization parameter indicating the temperature difference between the case and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal
characterization parameter is written as Psi-JC.

Table 13. Thermal characteristics for 100-pin LQFP

Symbol Parameter Conditions Typical value Unit

R

Thermal resistance junction-to-ambient,

JA

natural convection

(1)

Four layer board—2s2p 35.3

Single layer board—1s 47.3

(5)

(2)

Four layer board—2s2p 19.1

Single layer board—1s 9.7

(4)

Operating conditions 19.1

Operating conditions 0.8

R

R

JCtop





1. Junction-to-ambient thermal resistance determined per JEDEC JESD51-7. Thermal test board meets
JEDEC specification for this package.

2. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.

3. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the
interface layer.

4. Thermal characterization parameter indicating the temperature difference between the board and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal
characterization parameter is written as Psi-JB.

5. Thermal characterization parameter indicating the temperature difference between the case and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal
characterization parameter is written as Psi-JC.

Thermal resistance junction-to-board

JB

Thermal resistance junction-to-case

(3)

(top)

Junction-to-board, natural convection

JB

Junction-to-case, natural convection

JC

°C/

W

°C/

W

°C/

W

°C/

W

°C/

W

°C/

W

3.5.2 General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, TJ, can be obtained from Equation 1:

Equation 1 T

where:

T

A

R

JA

P

D

The junction to ambient thermal resistance is an industry standard value that provides a
quick and easy estimation of thermal performance. Unfortunately, there are two values in

= TA + (R

J

JA

* PD)

= ambient temperature for the package (°C)

= junction to ambient thermal resistance (°C/W)

= power dissipation in the package (W)

Doc ID 14723 Rev 8 57/115

Electrical characteristics SPC560P44Lx, SPC560P50Lx

common usage: the value determined on a single layer board and the value obtained on a
board with two planes. For packages such as the PBGA, these values can be different by a
factor of two. Which value is closer to the application depends on the power dissipated by
other components on the board. The value obtained on a single layer board is appropriate
for the tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are
well separated.

When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a
junction to case thermal resistance and a case to ambient thermal resistance:

Equation 2 R

JA

= R

JC

+ R

CA

where:

R

= junction to ambient thermal resistance (°C/W)

JA

R

JC

R

CA

R

is device related and cannot be influenced by the user. The user controls the thermal

JC

environment to change the case to ambient thermal resistance, R

= junction to case thermal resistance (°C/W)

= case to ambient thermal resistance (°C/W)

. For instance, the user

CA

can change the size of the heat sink, the air flow around the device, the interface material,
the mounting arrangement on printed circuit board, or change the thermal dissipation on the
printed circuit board surrounding the device.

To determine the junction temperature of the device in the application when heat sinks are
not used, the Thermal Characterization Parameter (

) can be used to determine the

JT

junction temperature with a measurement of the temperature at the top center of the
package case using Equation 3:

Equation 3 T

= TT + (JT x PD)

J

where:

T

T



JT

P

D

= thermocouple temperature on top of the package (°C)

= thermal characterization parameter (°C/W)

= power dissipation in the package (W)

The thermal characterization parameter is measured per JESD51-2 specification using a 40
gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the package.
A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of
wire extending from the junction. The thermocouple wire is placed flat against the package
case to avoid measurement errors caused by cooling effects of the thermocouple wire.

References:

Semiconductor Equipment and Materials International

3081 Zanker Road

San Jose, CA 95134 U.S.A.

[phone]

MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global
Engineering Documents at 800-854-7179 or 303-397-7956.

JEDEC specifications are available on the WEB at http://www.jedec.org.

58/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Electrical characteristics

1. C.E. Triplett and B. Joiner, An Experimental Characterization of a 272 PBGA Within an

Automotive Engine Controller Module, Proceedings of SemiTherm, San Diego, 1998,

pp. 47–54.

2. G. Kromann, S. Shidore, and S. Addison, Thermal Modeling of a PBGA for Air-Cooled

Applications, Electronic Packaging and Production, pp. 53–58, March 1998.

3. B. Joiner and V. Adams, Measurement and Simulation of Junction to Board Thermal

Resistance and Its Application in Thermal Modeling, Proceedings of SemiTherm, San
Diego, 1999, pp. 212–220.

3.6 Electromagnetic interference (EMI) characteristics

Table 14. EMI testing specifications

Symbol Parameter Conditions Clocks Frequency

V

Radiated emissions

EME

Device configuration, test
conditions and EM testing per
standard IEC61967-2

Supply voltage = 5 V DC
Ambient temperature = 25 °C
Worst-case orientation

8MHz

f

OSC

64 MHz

f

CPU

No PLL frequency
modulation

8MHz

f

OSC

64 MHz

f

CPU

1% PLL frequency
modulation

150 kHz–150 MHz 16

150–1000 MHz 15

IEC Level M —

150 kHz–150 MHz 15

150–1000 MHz 14

IEC Level M —

3.7 Electrostatic discharge (ESD) characteristics

Table 15. ESD ratings

Symbol Parameter Conditions Value Unit

V

ESD(HBM)

V

ESD(CDM)

S
R

S
R

(1),(2)

Electrostatic discharge (Human Body Model) — 2000 V

750 (corners)

Electrostatic discharge (Charged Device Model) —

500 (other)

Level

(Max)

Unit

dBµV

dBµV

V

1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.

2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at
room temperature followed by hot temperature, unless specified otherwise in the device specification.

3.8 Power management electrical characteristics

3.8.1 Voltage regulator electrical characteristics

The internal voltage regulator requires an external NPN ballast to be connected as shown in

Figure 9. Ta bl e 1 6 contains all approved NPN ballast components. Capacitances should be

placed on the board as near as possible to the associated pins. Care should also be taken

Doc ID 14723 Rev 8 59/115

Electrical characteristics SPC560P44Lx, SPC560P50Lx

BCTRL

VDD_LV_COR

C

DEC3

C

DEC2

C

DEC1

VDD_HV_REG

BJT

(1)

SPC560P44Lx,

1. Refer to Table 16.

R

B

to limit the serial inductance of the V
L

, see Ta bl e 1 7.

Reg

DD_HV_REG

, BCTRL and V

DD_LV_CORx

pins to less than

Note: The voltage regulator output cannot be used to drive external circuits. Output pins are used

only for decoupling capacitances.

V

DD_LV_COR

not possible to provide V

must be generated using internal regulator and external NPN transistor. It is

DD_LV_COR

through external regulator.

For the SPC560P44Lx, SPC560P50Lx microcontroller, capacitors, with total values not
below C
ballast transistor emitter. 4 capacitors, with total values not below C
close to microcontroller pins between each V
V

DD_LV_REGCOR/VSS_LV_REGCOR

C

DEC3

, should be placed between V

DEC1

pair . Additionally, capacitors with total values not below

, should be placed between the V

DD_LV_CORx/VSS_LV_CORx

DD_LV_CORx/VSS_LV_CORx

DD_HV_REG/VSS_HV_REG

close to external

, should be placed

DEC2

supply pairs and the

pins close to ballast
collector. Capacitors values have to take into account capacitor accuracy, aging and
variation versus temperature.

All reported information are valid for voltage and temperature ranges described in
recommended operating condition, Ta bl e 1 0 and Ta b le 1 1 .

60/115 Doc ID 14723 Rev 8

Figure 9. Configuration with resistor on base

Table 16. Approved NPN ballast components (configuration with resistor on base)

Part Manufacturer Approved derivatives

BCP68

BCX68 Infineon BCX68-10;BCX68-16;BCX68-25

ON Semi BCP68

NXP BCP68-25

Infineon BCP68-25

(1)

SPC560P44Lx, SPC560P50Lx Electrical characteristics

Table 16. Approved NPN ballast components (configuration with resistor on base)

Part Manufacturer Approved derivatives

BC868 NXP BC868

(1)

BC817

Infineon BC817-16;BC817-25;BC817SU;

NXP BC817-16;BC817-25

ST BCP56-16

Infineon BCP56-10;BCP56-16

BCP56

ON Semi BCP56-10

NXP BCP56-10;BCP56-16

1. For automotive applications please check with the appropriate transistor vendor for automotive grade

certification

Table 17. Voltage regulator electrical characteristics (configuration with resistor on base)

Value

Symbol C Parameter Conditions

Min Typ Max

Output voltage under

V

DD_LV_REGCOR

CC P

maximum load run supply

Post-trimming 1.15 — 1.32 V

current configuration

R

B

SR —

External resistance on bipolar
junction transistor (BJT) base

—18—22k

BJT from Ta bl e 1 6 . 3

C

DEC1

SR —

External decoupling/stability
ceramic capacitor

capacitances (i.e. X7R or
X8R capacitors) with nominal
value of 10 µF

BJT BC817, one capacitance
of 22 µF

19.5 30 — µF

14.3 22 µF

Unit

R

C

DEC2

C

DEC3

L

REG

Reg

SR —

SR —

SR —

SR —

Resulting ESR of all three
capacitors of C

DEC1

Resulting ESR of the unique
capacitor C

DEC1

External decoupling/stability
ceramic capacitor

External decoupling/stability
ceramic capacitor on
V

DD_HV_REG

Resulting ESL of V
BCTRL and V

DD_HV_REG

DD_LV_CORx

pins

Doc ID 14723 Rev 8 61/115

BJT from Ta bl e 1 6 . 3x10 µF.
Absolute maximum value
between 100 kHz and

——50m

10 MHz

BJT BC817, 1x 22 µF.
Absolute maximum value
between 100 kHz and

10 — 40 m

10 MHz

4 capacitances (i.e. X7R or
X8R capacitors) with nominal

1200 1760 — nF

value of 440 nF

3 capacitances (i.e. X7R or
X8R capacitors) with nominal
value of 10 µF; C

DEC3

has to

19.5 30 — µF
be equal or greater than
C

DEC1

,

———15nH

Electrical characteristics SPC560P44Lx, SPC560P50Lx

BCTRL

VDD_LV_COR

C

DEC3

C

DEC2

C

DEC1

VDD_HV_REG

SPC560P44Lx,

BCP56,
BCP68,
BCX68,
BC817

Figure 10. Configuration without resistor on base

Table 18. Voltage regulator electrical characteristics (configuration without resistor on base)

Symbol C Parameter Conditions

Output voltage under

V

DD_LV_REGCOR

CC P

maximum load run supply

Post-trimming 1.15 — 1.32 V

current configuration

C

DEC1

R

C

DEC2

REG

SR —

SR —

SR —

External decoupling/stability
ceramic capacitor

Resulting ESR of all four
C

DEC1

External decoupling/stability
ceramic capacitor

4 capacitances 40 56 — µF

Absolute maximum value
between 100 kHz and
10 MHz

4 capacitances of 100 nF
each

External decoupling/stability

C

DEC3

SR —

ceramic capacitor on
VDD_HV_REG

L

Reg

SR —

Resulting ESL of V
BCTRL and V

DD_LV_CORx

DD_HV_REG

,

———15nH

pins

Value

Unit

Min Typ Max

——45m

400 — — nF

—40——µF

62/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Electrical characteristics

3.8.2 Voltage monitor electrical characteristics

The device implements a Power-on Reset module to ensure correct power-up initialization,
as well as three low voltage detectors to monitor the V
device is supplied:

● POR monitors V

during the power-up phase to ensure device is maintained in a safe

DD

reset state

● LVDHV3 monitors V

● LVDHV5 monitors V

● LVDLVCOR monitors low voltage digital power domain

Table 19. Low voltage monitor electrical characteristics

to ensure device reset below minimum functional supply

DD

when application uses device in the 5.0 V ± 10 % range

DD

and the V

DD

voltage while

DD_LV

Symbol C Parameter

V

PORH

V

PORUP

V

REGLVDMOK_H

V

REGLVDMOK_L

V

FLLVDMOK_H

V

FLLVDMOK_L

V

IOLVDMOK_H

V

IOLVDMOK_L

V

IOLVDM5OK_H

V

IOLVDM5OK_L

V

MLVDDOK_H

V

MLVDDOK_L

1. VDD = 3.3V ± 10% / 5.0V ± 10%, TA = –40 °C to T

T Power-on reset threshold — 1.5 2.7 V

P Supply for functional POR module TA = 25 °C 1.0 — V

P Regulator low voltage detector high threshold — — 2.95 V

P Regulator low voltage detector low threshold — 2.6 — V

P Flash low voltage detector high threshold — — 2.95 V

P Flash low voltage detector low threshold — 2.6 — V

P I/O low voltage detector high threshold — — 2.95 V

P I/O low voltage detector low threshold — 2.6 — V

P I/O 5V low voltage detector high threshold — — 4.4 V

P I/O 5V low voltage detector low threshold — 3.8 — V

P Digital supply low voltage detector high — — 1.145 V

P Digital supply low voltage detector low — 1.08 — V

, unless otherwise specified

A MAX

3.9 Power up/down sequencing

Conditions

(1)

Value

Unit

Min Max

To prevent an overstress event or a malfunction within and outside the device, the
SPC560P44Lx, SPC560P50Lx implements the following sequence to ensure each module
is started only when all conditions for switching it ON are available:

● A POWER_ON module working on voltage regulator supply controls the correct start-

up of the regulator. This is a key module ensuring safe configuration for all voltage
regulator functionality when supply is below 1.5V. Associated POWER_ON (or POR)
signal is active low.

● Several low voltage detectors, working on voltage regulator supply monitor the voltage

of the critical modules (voltage regulator, I/Os, flash memory and low voltage domain).
LVDs are gated low when POWER_ON is active.

● A POWER_OK signal is generated when all critical supplies monitored by the LVD are

available. This signal is active high and released to all modules including I/Os, flash

Doc ID 14723 Rev 8 63/115

Electrical characteristics SPC560P44Lx, SPC560P50Lx

VDD_HV_REG

0V

3.3V

0V

3.3V

VDD_LV_REGCOR

0V

1.2V

0V

3.3V

POWER_ON

LVDM (HV)

0V

LVDD (LV)

3.3V

0V

POWER_OK

3.3V

RC16MHz Oscillator

0V

1.2V

P0 P1

0V

1.2V

Internal Reset Generation Module
FSM

~1us

V

POR_UP

V

PORH

V

LVDHV3H

V

MLVDOK_H

VDD_HV_REG

0V

3.3V

0V

3.3V

VDD_LV_REGCOR

0V

1.2V

3.3V

POWER_ON

LVDM (HV)

0V

LVDD (LV)

3.3V

0V

POWER_OK

3.3V

RC16MHz Oscillator

0V

1.2V

P0IDLE

0V

1.2V

Internal Reset Generation Module
FSM

V

LVDHV3L

V

PORH

0V

memory and RC16 oscillator needed during power-up phase and reset phase. When
POWER_OK is low the associated module are set into a safe state.

64/115 Doc ID 14723 Rev 8

Figure 11. Power-up typical sequence

Figure 12. Power-down typical sequence

SPC560P44Lx, SPC560P50Lx Electrical characteristics

VDD_HV_REG

0V

3.3V

0V

3.3V

VDD_LV_REGCOR

0V

1.2V

3.3V

POWER_ON

LVDM (HV)

0V

LVDD (LV)

3.3V

0V

POWER_OK

3.3V

RC16MHz Oscillator

0V

1.2V

P0IDLE

0V

1.2V

Internal Reset Generation Module
FSM

V

LVDHV3L

0V

V

LVDHV3H

P1

~1us

3.10 DC electrical characteristics

3.10.1 NVUSRO register

Figure 13. Brown-out typical sequence

Portions of the device configuration, such as high voltage supply, and watchdog
enable/disable after reset are controlled via bit values in the non-volatile user options
(NVUSRO) register.

For a detailed description of the NVUSRO register, please refer to the device reference
manual.

NVUSRO[PAD3V5V] field description

The DC electrical characteristics are dependent on the PAD3V5V bit value. Ta b le 2 0 shows
how NVUSRO[PAD3V5V] controls the device configuration.

Table 20. PAD3V5V field description

1. Default manufacturing value before flash initialization is ‘1’ (3.3 V).

(1)

Value

0 High voltage supply is 5.0 V

1 High voltage supply is 3.3 V

Doc ID 14723 Rev 8 65/115

Description

Electrical characteristics SPC560P44Lx, SPC560P50Lx

3.10.2 DC electrical characteristics (5 V)

Ta bl e 2 1 gives the DC electrical characteristics at 5 V (4.5 V < V

NVUSRO[PAD3V5V] = 0); see Figure 14.

Table 21. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)

Symbol C Parameter Conditions

V

IL

V

IH

V

HYS

V

OL_S

V

OH_S

V

OL_M

V

OH_M

V

OL_F

V

OH_F

V

OL_SYM

V

OH_SYM

I

PU

I

PD

I

IL

I

IL

Min Max

D

— –0.1

(1)

Low level input voltage

P——0.35V

P

High level input voltage

—0.65V

DD_HV_IOx

D——V

T Schmitt trigger hysteresis — 0.1 V

DD_HV_IOx

P Slow, low level output voltage IOL=3mA — 0.1V

P Slow, high level output voltage IOH=–3mA 0.8V

DD_HV_IOx

P Medium, low level output voltage IOL=3mA — 0.1V

P Medium, high level output voltage IOH=–3mA 0.8V

DD_HV_IOx

P Fast, low level output voltage IOL=3mA — 0.1V

P Fast, high level output voltage IOH=–3mA 0.8V

DD_HV_IOx

P Symmetric, low level output voltage IOL=3mA — 0.1V

P Symmetric, high level output voltage IOH=–3mA 0.8V

V

P Equivalent pull-up current

P Equivalent pull-down current

Input leakage current (all

P

bidirectional ports)

Input leakage current (all ADC input-

P

only ports)

IN=VIL

V

IN=VIH

VIN=V

IL

V

IN=VIH

= –40 to 125 °C –1 1 µA

T

A

TA = –40 to 125 °C –0.5 0.5 µA

DD_HV_IOx

–130 —

—–10

10 —

—130

DD_HV_IOx

Value

DD_HV_IOx

< 5.5 V,

Unit

—V

(1)

V

V

V

V

V

V

µA

µA

DD_HV_IOx

—V

+0.1

—V

DD_HV_IOx

—V

DD_HV_IOx

—V

DD_HV_IOx

—V

DD_HV_IOx

—V

C

I

1. “SR” parameter values must not exceed the absolute maximum ratings shown in Table 9.

D Input capacitance — — 10 pF

IN

D RESET, equivalent pull-up current

PU

V

IN=VIL

V

IN=VIH

–130 —

—–10

66/115 Doc ID 14723 Rev 8

µA

SPC560P44Lx, SPC560P50Lx Electrical characteristics

Table 22. Supply current (5.0 V, NVUSRO[PAD3V5V] = 0)

Symbol C Parameter Conditions

(2)

(2)

(1)

(3)

(1)

V

DD_LV_CORx

externally forced at 1.3 V

V

DD_LV_CORx

externally forced at 1.3 V

V

DD_LV_CORx

externally forced at 1.3 V

V

DD_LV_CORx

externally forced at 1.3 V

DD_HV_FL

V

DD_HV_FL

V

DD_HV_ADC0

V

DD_HV_ADC1

f

ADC

at 5.0 V — 10 12

at 5.0 V — 15 19

at 5.0 V
at 5.0 V

= 16MHz

I

DD_LV_CORx

I

DD_FLASH

I

DD_ADC

RUN—Maximum mode

T

RUN—Typical mode

RUN—Maximum mode

P

HALT mode

STOP mode

Flash during read V

Supply current

T

Flash during erase operation on 1

(4)

(5)

flash module

ADC—Maximum mode

T

ADC—Typical mode

Value

Typ M ax

40 MHz 62 77

64 MHz 71 88

40 MHz 45 56

64 MHz 52 65

64 MHz 60 75

—1.510

—110

ADC_1 3.5 5

ADC_0 3 4

ADC_1 0.8 1

ADC_0 0.005 0.006

Unit

mA

I

DD_OSC

1. Maximum mode: FlexPWM, ADCs, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, 1st and 2nd PLL enabled. I/O supply
current excluded.

2. Typical mode configurations: DSPI, LINFlex, FlexCAN, 15 output pins, 1st PLL only. I/O supply current excluded.

3. Code fetched from RAM, PLL_0: 64 MHz system clock (x4 multiplier with 16 MHz XTAL), PLL_1 is ON at
PHI_div2 = 120 MHz and PHI_div3 = 80 MHz, auxiliary clock sources set that all peripherals receive maximum frequency,
all peripherals enabled.

4. Halt mode configurations: code fetched from RAM, code and data flash memories in low power mode, OSC/PLL_0/PLL_1
are OFF, core clock frozen, all peripherals are disabled.

5. STOP “P” mode Device Under Test (DUT) configuration: code fetched from RAM, code and data flash memories OFF,
OSC/PLL_0/PLL_1 are OFF, core clock frozen, all peripherals are disabled.

T Oscillator V

DD_OSC

at 5.0 V 8 MHz 2.6 3.2

3.10.3 DC electrical characteristics (3.3 V)

Ta bl e 2 3 gives the DC electrical characteristics at 3.3 V (3.0 V < V

NVUSRO[PAD3V5V] = 1); see Figure 14.

Table 23. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)

Symbol C Parameter Conditions

V

IL

Min Max

D

—–0.1

(2)

Low level input voltage

P——0.35V

DD_HV_IOx

(1)

Value

< 3.6 V,

—V

DD_HV_IOx

Unit

V

Doc ID 14723 Rev 8 67/115

Electrical characteristics SPC560P44Lx, SPC560P50Lx

Table 23. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)

Symbol C Parameter Conditions

Min Max

V

V

HYS

V

OL_S

V

OH_S

V

OL_M

V

OH_M

V

OL_F

V

OH_F

V

OL_SYM

V

OH_SYM

I

PU

I

PD

I

I

C

IH

IL

IL

IN

High level input voltage

D——V

T Schmitt trigger hysteresis — 0.1 V

P Slow, low level output voltage IOL= 1.5 mA — 0.5 V

P Slow, high level output voltage IOH= –1.5 mA V

P Medium, low level output voltage IOL=2mA — 0.5 V

P Medium, high level output voltage IOH=–2mA V

P Fast, low level output voltage IOL= 1.5 mA — 0.5 V

P Fast, high level output voltage IOH= –1.5 mA V

P Symmetric, low level output voltage IOL= 1.5 mA — 0.5 V

P Symmetric, high level output voltage IOH= –1.5 mA V

P Equivalent pull-up current

P Equivalent pull-down current

Input leakage current (all

P

bidirectional ports)

Input leakage current (all ADC input-

P

only ports)

TA = –40 to 125 °C — 1 µA

T

D Input capacitance — — 10 pF

V

I

D RESET, equivalent pull-up current

P

PU

1. These specifications are design targets and subject to change per device characterization.

2. “SR” parameter values must not exceed the absolute maximum ratings shown in Table 9.

V

—0.65V

V

IN=VIL

V

IN=VIH

V

IN=VIL

V

IN=VIH

= –40 to 125 °C — 0.5 µA

A

IN=VIL

IN=VIH

DD_HV_IOx

DD_HV_IOx

DD_HV_IOx

DD_HV_IOx

DD_HV_IOx

DD_HV_IOx

–130 —

— –10

10 —

— 130

–130 —

— –10

(1)

(continued)

Value

Unit

—V

DD_HV_IOx

+0.1

V

(2)

—V

–0.8 — V

–0.8 — V

–0.8 — V

–0.8 — V

µA

µA

µA

68/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Electrical characteristics

Table 24. Supply current (3.3 V, NVUSRO[PAD3V5V] = 1)

Symbol C Parameter Conditions

(2)

(2)

(1)

(3)

(1)

V

DD_LV_CORx

externally forced at 1.3 V

V

DD_LV_CORx

externally forced at 1.3 V

V

DD_LV_CORx

externally forced at 1.3 V

V

DD_LV_CORx

externally forced at 1.3 V

DD_HV_FL

V

DD_HV_FL

V

DD_HV_ADC0

V

DD_HV_ADC1

f

ADC

at 3.3 V — 8 10

at 3.3 V — 10 12

at 3.3 V
at 3.3 V

=16MHz

I

DD_LV_CORx

I

DD_FLASH

I

DD_ADC

RUN—Maximum mode

T

RUN—Typical mode

RUN—Maximum mode

HALT mode

P

STOP mode

Flash during read on single mode V

Supply current

T

Flash during erase operation on

(4)

(5)

single mode

ADC—Maximum mode

T

ADC—Typical mode

Val ue

Typ Max

40 MHz 62 77

64 MHz 71 89

40 MHz 45 56

64 MHz 53 66

64 MHz 60 75

—1.510

—110

ADC_1 2.5 4

ADC_0 2 4

ADC_1 0.8 1

ADC_0 0.005 0.006

Unit

mA

I

DD_OSC

1. Maximum mode: FlexPWM, ADCs, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, 1st and 2nd PLL enabled. I/O supply
current excluded.

2. Typical mode: DSPI, LINFlex, FlexCAN, 15 output pins, 1st PLL only. I/O supply current excluded.

3. Code fetched from RAM, PLL_0: 64 MHz system clock (x4 multiplier with 16 MHz XTAL), PLL_1 is ON at
PHI_div2 = 120 MHz and PHI_div3 = 80 MHz, auxiliary clock sources set that all peripherals receive maximum frequency,
all peripherals enabled.

4. Halt mode configurations: code fetched from RAM, code and data flash memories in low power mode, OSC/PLL_0/PLL_1
are OFF, core clock frozen, all peripherals are disabled.

5. STOP “P” mode Device Under Test (DUT) configuration: code fetched from RAM, code and data flash memories OFF,
OSC/PLL_0/PLL_1 are OFF, core clock frozen, all peripherals are disabled.

T Oscillator V

at 3.3V 8MHz 2.4 3

DD_OSC

3.10.4 Input DC electrical characteristics definition

Figure 14 shows the DC electrical characteristics behavior as function of time.

Doc ID 14723 Rev 8 69/115

Electrical characteristics SPC560P44Lx, SPC560P50Lx

V

IL

V

IN

V

IH

PDIx = ‘1’

V

DD

V

HYS

(GPDI register of SIUL)

PDIx = ‘0’

Figure 14. Input DC electrical characteristics definition

3.10.5 I/O pad current specification

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is
associated to a V

Table 25. I/O supply segment

DD/VSS

Package

12345 6 7

LQFP144 pin8 – pin20 pin23 – pin38 pin39 – pin55 pin58 – pin68 pin73 – pin89 pin92 – pin125 pin128 – pin5

LQFP100 pin15 – pin26 pin27 – pin38 pin41 – pin46 pin51 – pin61 pin64 – pin86 pin89 – pin10 —

Ta bl e 2 6 provides the weight of concurrent switching I/Os.

In order to ensure device functionality, the sum of the weight of concurrent switching I/Os on
a single segment should remain below 100%.

Table 26. I/O weight

Pad

NMI 1% 1% 1% 1%

PAD[6] 6% 5% 14% 13%

PAD[49] 5% 4% 14% 12%

PAD[84] 14% 10% — —

PA D[ 8 5] 9% 7 % — —

supply pair as described in Ta bl e 2 5.

Supply segment

LQFP144 LQFP100

Weight 5V Weight 3.3V Weight 5V Weight 3.3V

70/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Electrical characteristics

Table 26. I/O weight (continued)

LQFP144 LQFP100

Pad

Weight 5V Weight 3.3V Weight 5V Weight 3.3V

PA D[ 8 6] 9% 6 % — —

MODO[0] 12% 8% — —

PAD[7] 4% 4% 11% 10%

PAD[36] 5% 4% 11% 9%

PAD[8] 5% 4% 10% 9%

PAD[37] 5% 4% 10% 9%

PAD[5] 5% 4% 9% 8%

PA D[ 3 9] 5% 4 % 9 % 8 %

PA D[ 3 5] 5% 4 % 8 % 7 %

PAD[87] 12% 9% — —

PA D[ 8 8] 9% 6 % — —

PAD[89] 10% 7% — —

PAD[90] 15% 11% — —

PA D[ 9 1] 6% 5 % — —

PA D[ 5 7] 8% 7 % 8 % 7 %

PAD[56] 13% 11% 13% 11%

PAD[53] 14% 12% 14% 12%

PAD[54] 15% 13% 15% 13%

PAD[55] 25% 22% 25% 22%

PAD[96] 27% 24% — —

PA D[ 6 5] 1% 1 % 1 % 1 %

PA D[ 6 7] 1% 1 % — —

PA D[ 3 3] 1% 1 % 1 % 1 %

PA D[ 6 8] 1% 1 % — —

PA D[ 2 3] 1% 1 % 1 % 1 %

PA D[ 6 9] 1% 1 % — —

PA D[ 3 4] 1% 1 % 1 % 1 %

PA D[ 7 0] 1% 1 % — —

PA D[ 2 4] 1% 1 % 1 % 1 %

PA D[ 7 1] 1% 1 % — —

PA D[ 6 6] 1% 1 % 1 % 1 %

PA D[ 2 5] 1% 1 % 1 % 1 %

PA D[ 2 6] 1% 1 % 1 % 1 %

Doc ID 14723 Rev 8 71/115

Electrical characteristics SPC560P44Lx, SPC560P50Lx

Table 26. I/O weight (continued)

LQFP144 LQFP100

Pad

Weight 5V Weight 3.3V Weight 5V Weight 3.3V

PA D[ 8 6] 9% 6 % — —

MODO[0] 12% 8% — —

PAD[7] 4% 4% 11% 10%

PAD[36] 5% 4% 11% 9%

PAD[8] 5% 4% 10% 9%

PAD[37] 5% 4% 10% 9%

PAD[5] 5% 4% 9% 8%

PA D[ 3 9] 5% 4 % 9 % 8 %

PA D[ 3 5] 5% 4 % 8 % 7 %

PAD[87] 12% 9% — —

PA D[ 8 8] 9% 6 % — —

PAD[89] 10% 7% — —

PAD[90] 15% 11% — —

PA D[ 9 1] 6% 5 % — —

PA D[ 5 7] 8% 7 % 8 % 7 %

PAD[56] 13% 11% 13% 11%

PAD[53] 14% 12% 14% 12%

PAD[54] 15% 13% 15% 13%

PAD[55] 25% 22% 25% 22%

PAD[96] 27% 24% — —

PA D[ 6 5] 1% 1 % 1 % 1 %

PA D[ 6 7] 1% 1 % — —

PA D[ 3 3] 1% 1 % 1 % 1 %

PA D[ 6 8] 1% 1 % — —

PA D[ 2 3] 1% 1 % 1 % 1 %

PA D[ 6 9] 1% 1 % — —

PA D[ 3 4] 1% 1 % 1 % 1 %

PA D[ 7 0] 1% 1 % — —

PA D[ 2 4] 1% 1 % 1 % 1 %

PA D[ 7 1] 1% 1 % — —

PA D[ 6 6] 1% 1 % 1 % 1 %

PA D[ 2 5] 1% 1 % 1 % 1 %

PA D[ 2 6] 1% 1 % 1 % 1 %

72/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Electrical characteristics

Table 26. I/O weight (continued)

LQFP144 LQFP100

Pad

Weight 5V Weight 3.3V Weight 5V Weight 3.3V

PA D[ 8 6] 9% 6 % — —

MODO[0] 12% 8% — —

PAD[7] 4% 4% 11% 10%

PAD[36] 5% 4% 11% 9%

PAD[8] 5% 4% 10% 9%

PAD[37] 5% 4% 10% 9%

PAD[5] 5% 4% 9% 8%

PA D[ 3 9] 5% 4 % 9 % 8 %

PA D[ 3 5] 5% 4 % 8 % 7 %

PAD[87] 12% 9% — —

PA D[ 8 8] 9% 6 % — —

PAD[89] 10% 7% — —

PAD[90] 15% 11% — —

PA D[ 9 1] 6% 5 % — —

PA D[ 5 7] 8% 7 % 8 % 7 %

PAD[56] 13% 11% 13% 11%

PAD[53] 14% 12% 14% 12%

PAD[54] 15% 13% 15% 13%

PAD[55] 25% 22% 25% 22%

PAD[96] 27% 24% — —

PA D[ 6 5] 1% 1 % 1 % 1 %

PA D[ 6 7] 1% 1 % — —

PA D[ 3 3] 1% 1 % 1 % 1 %

PA D[ 6 8] 1% 1 % — —

PA D[ 2 3] 1% 1 % 1 % 1 %

PA D[ 6 9] 1% 1 % — —

PA D[ 3 4] 1% 1 % 1 % 1 %

PA D[ 7 0] 1% 1 % — —

PA D[ 2 4] 1% 1 % 1 % 1 %

PA D[ 7 1] 1% 1 % — —

PA D[ 6 6] 1% 1 % 1 % 1 %

PA D[ 2 5] 1% 1 % 1 % 1 %

PA D[ 2 6] 1% 1 % 1 % 1 %

Doc ID 14723 Rev 8 73/115

Electrical characteristics SPC560P44Lx, SPC560P50Lx

Table 26. I/O weight (continued)

LQFP144 LQFP100

Pad

Weight 5V Weight 3.3V Weight 5V Weight 3.3V

PA D[ 8 6] 9% 6 % — —

MODO[0] 12% 8% — —

PAD[7] 4% 4% 11% 10%

PAD[36] 5% 4% 11% 9%

PAD[8] 5% 4% 10% 9%

PAD[37] 5% 4% 10% 9%

PAD[5] 5% 4% 9% 8%

PA D[ 3 9] 5% 4 % 9 % 8 %

PA D[ 3 5] 5% 4 % 8 % 7 %

PAD[87] 12% 9% — —

PA D[ 8 8] 9% 6 % — —

PAD[89] 10% 7% — —

PAD[90] 15% 11% — —

PA D[ 9 1] 6% 5 % — —

PA D[ 5 7] 8% 7 % 8 % 7 %

PAD[56] 13% 11% 13% 11%

PAD[53] 14% 12% 14% 12%

PAD[54] 15% 13% 15% 13%

PAD[55] 25% 22% 25% 22%

PAD[96] 27% 24% — —

PA D[ 6 5] 1% 1 % 1 % 1 %

PA D[ 6 7] 1% 1 % — —

PA D[ 3 3] 1% 1 % 1 % 1 %

PA D[ 6 8] 1% 1 % — —

PA D[ 2 3] 1% 1 % 1 % 1 %

PA D[ 6 9] 1% 1 % — —

PA D[ 3 4] 1% 1 % 1 % 1 %

PA D[ 7 0] 1% 1 % — —

PA D[ 2 4] 1% 1 % 1 % 1 %

PA D[ 7 1] 1% 1 % — —

PA D[ 6 6] 1% 1 % 1 % 1 %

PA D[ 2 5] 1% 1 % 1 % 1 %

PA D[ 2 6] 1% 1 % 1 % 1 %

74/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Electrical characteristics

Table 26. I/O weight (continued)

LQFP144 LQFP100

Pad

Weight 5V Weight 3.3V Weight 5V Weight 3.3V

PA D[ 2 7] 1% 1 % 1 % 1 %

PA D[ 2 8] 1% 1 % 1 % 1 %

PA D[ 6 3] 1% 1 % 1 % 1 %

PA D[ 7 2] 1% 1 % — —

PA D[ 2 9] 1% 1 % 1 % 1 %

PA D[ 7 3] 1% 1 % — —

PA D[ 3 1] 1% 1 % 1 % 1 %

PA D[ 7 4] 1% 1 % — —

PA D[ 3 0] 1% 1 % 1 % 1 %

PA D[ 7 5] 1% 1 % — —

PA D[ 3 2] 1% 1 % 1 % 1 %

PA D[ 7 6] 1% 1 % — —

PA D[ 6 4] 1% 1 % 1 % 1 %

PAD[0] 23% 20% 23% 20%

PAD[1] 21% 18% 21% 18%

PAD[107] 20% 17% — —

PAD[58] 19% 16% 19% 16%

PAD[106] 18% 16% — —

PAD[59] 17% 15% 17% 15%

PAD[105] 16% 14% — —

PAD[43] 15% 13% 15% 13%

PAD[104] 14% 13% — —

PAD[44] 13% 12% 13% 12%

PAD[103] 12% 11% — —

PAD[2] 11% 10% 11% 10%

PAD[101] 11% 9% — —

PAD[21] 10% 8% 10% 8%

TMS 1% 1% 1% 1%

TCK 1% 1% 1% 1%

PAD[20] 16% 11% 16% 11%

PAD[3] 4% 3% 4% 3%

PA D[ 6 1] 9% 8 % 9 % 8 %

PAD[102] 11% 10% — —

Doc ID 14723 Rev 8 75/115

Electrical characteristics SPC560P44Lx, SPC560P50Lx

Table 26. I/O weight (continued)

LQFP144 LQFP100

Pad

Weight 5V Weight 3.3V Weight 5V Weight 3.3V

PAD[60] 11% 10% 11% 10%

PAD[100] 12% 10% — —

PAD[45] 12% 10% 12% 10%

PAD[98] 12% 11% — —

PAD[46] 12% 11% 12% 11%

PAD[99] 13% 11% — —

PAD[62] 13% 11% 13% 11%

PAD[92] 13% 12% — —

VPP_TEST 1% 1% 1% 1%

PAD[4] 14% 12% 14% 12%

PAD[16] 13% 12% 13% 12%

PAD[17] 13% 11% 13% 11%

PAD[42] 13% 11% 13% 11%

PAD[93] 12% 11% — —

PAD[95] 12% 11% — —

PAD[18] 12% 10% 12% 10%

PAD[94] 11% 10% — —

PAD[19] 11% 10% 11% 10%

PAD[77] 10% 9% — —

PAD[10] 10% 9% 10% 9%

PA D[ 7 8] 9% 8 % — —

PA D[ 1 1] 9% 8 % 9 % 8 %

PA D[ 7 9] 8% 7 % — —

PA D[ 1 2] 7% 7 % 7 % 7 %

PA D[ 4 1] 7% 6 % 7 % 6 %

PA D[ 4 7] 5% 4 % 5 % 4 %

PA D[ 4 8] 4% 4 % 4 % 4 %

PA D[ 5 1] 4% 4 % 4 % 4 %

PA D[ 5 2] 5% 4 % 5 % 4 %

PA D[ 4 0] 5% 5 % 6 % 5 %

PA D[ 8 0] 9% 8 % — —

PAD[9] 10% 9% 11% 10%

PAD[81] 10% 9% — —

76/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Electrical characteristics

Table 26. I/O weight (continued)

LQFP144 LQFP100

Pad

Weight 5V Weight 3.3V Weight 5V Weight 3.3V

PAD[13] 10% 9% 12% 11%

PAD[82] 10% 9% — —

PAD[22] 10% 9% 13% 12%

PAD[83] 10% 9% — —

PAD[50] 10% 9% 14% 12%

PAD[97] 10% 9% — —

PAD[38] 10% 9% 14% 13%

PAD[14] 9% 8% 14% 13%

PAD[15] 9% 8% 15% 13%

Table 27. I/O consumption

Symbol C Parameter Conditions

Dynamic I/O current

CC D

for SLOW

CL = 25 pF

I

SWTSLW

(2)

configuration

Dynamic I/O current

CC D

for MEDIUM

CL = 25 pF

I

SWTMED

(2)

configuration

Dynamic I/O current

CC D

for FAST

CL = 25 pF

I

SWTFST

(2)

configuration

CL = 25 pF, 2 MHz

= 25 pF, 4 MHz — — 3.2

C

L

I

RMSSLW

Root medium square

CC D

I/O current for SLOW
configuration

= 100 pF, 2 MHz — — 6.6

C

L

C

= 25 pF, 2 MHz

L

= 25 pF, 4 MHz — — 2.3

C

L

= 100 pF, 2 MHz — — 4.7

C

L

(1)

V

= 5.0 V ± 10%,

DD

PAD3V5V = 0

= 3.3 V ± 10%,

V

DD

PAD3V5V = 1

V

= 5.0 V ± 10%,

DD

PAD3V5V = 0

V

= 3.3 V ± 10%,

DD

PAD3V5V = 1

V

= 5.0 V ± 10%,

DD

PAD3V5V = 0

= 3.3 V ± 10%,

V

DD

PAD3V5V = 1

V

= 5.0 V ± 10%,

DD

PAD3V5V = 0

V

= 3.3 V ± 10%,

DD

PAD3V5V = 1

Val ue

Unit

Min Typ Max

——20

mA

——16

——29

mA

——17

— — 110

mA

——50

——2.3

mA

——1.6

Doc ID 14723 Rev 8 77/115

Electrical characteristics SPC560P44Lx, SPC560P50Lx

Table 27. I/O consumption (continued)

Symbol C Parameter Conditions

= 25 pF, 13 MHz

C

L

= 25 pF, 40 MHz — — 13.4

C

Root medium square

I

RMSMED

CC D

I/O current for
MEDIUM
configuration

Root medium square

I

RMSFST

CC D

I/O current for FAST
configuration

Sum of all the static

I

AVGSEG

SR D

I/O current within a
supply segment

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified

2. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.

L

= 100 pF, 13 MHz — — 18.3

C

L

= 25 pF, 13 MHz

C

L

C

= 25 pF, 40 MHz — — 8.5

L

= 100 pF, 13 MHz — — 11

C

L

C

= 25 pF, 40 MHz

L

= 25 pF, 64 MHz — — 33

C

L

= 100 pF, 40 MHz — — 56

C

L

C

= 25 pF, 40 MHz

L

= 25 pF, 64 MHz — — 20

C

L

= 100 pF, 40 MHz — — 35

C

L

V

= 5.0 V ± 10%, PAD3V5V = 0 — — 70

DD

= 3.3 V ± 10%, PAD3V5V = 1 — — 65

V

DD

(1)

V

= 5.0 V ± 10%,

DD

PAD3V5V = 0

V

= 3.3 V ± 10%,

DD

PAD3V5V = 1

V

= 5.0 V ± 10%,

DD

PAD3V5V = 0

V

= 3.3 V ± 10%,

DD

PAD3V5V = 1

Val ue

Unit

Min Typ Max

——6.6

mA

—— 5

——22

mA

——14

mA

3.11 Main oscillator electrical characteristics

The SPC560P44Lx, SPC560P50Lx provides an oscillator/resonator driver.

Table 28. Main oscillator output electrical characteristics (5.0 V,

NVUSRO[PAD3V5V] = 0)

Symbol C Parameter

Min Max

f

OSC

g

m

V

OSC

t

OSCSU

1. The start-up time is dependent upon crystal characteristics, board leakage, etc., high ESR and excessive
capacitive loads can cause long start-up time.

2. Value captured when amplitude reaches 90% of XTAL

SR —

—P

—T

—T

Oscillator
frequency

Transcondu
ctance

Oscillation
amplitude on
XTAL pin

Start-up

(1),(2)

time

440MHz

6.5 25 mA/V

1—V

8—ms

Value

Unit

78/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Electrical characteristics

Table 29. Main oscillator output electrical characteristics (3.3 V,

NVUSRO[PAD3V5V] = 1)

Value

Symbol C Parameter

Min Max

Unit

f

OSC

V

t

OSCSU

1. The start-up time is dependent upon crystal characteristics, board leakage, etc., high ESR and excessive

2. Value captured when amplitude reaches 90% of XTAL

Table 30. Input clock characteristics

SR — Oscillator frequency 4 40 MHz

g

OSC

— P Transconductance 4 20 mA/V

m

— T Oscillation amplitude on XTAL pin 1 — V

— T Start-up time

capacitive loads can cause long start-up time.

(1),(2)

Symbol Parameter

f

SR Oscillator frequency 4 — 40 MHz

OSC

SR Frequency in bypass — — 64 MHz

f

CLK

t

SR Rise/fall time in bypass — — 1 ns

rCLK

SR Duty cycle 47.5 50 52.5 %

t

DC

3.12 FMPLL electrical characteristics

Table 31. FMPLL electrical characteristics

8—ms

Value

Unit

Min Typ Max

Symbol C Parameter Conditions

f

ref_crystal

f

ref_ext

f

PLLIN

f

FMPLLOUT

f

FREE

t

CYC

f

LORL

f

LORH

f

SCM

D PLL reference frequency range

Phase detector input frequency range

D

(after pre-divider)

D Clock frequency range in normal mode — 16 120 MHz

P Free-running frequency

D System clock period — — 1 / f

D Loss of reference frequency window

D Self-clocked mode frequency

(2)

(4),(5)

Crystal reference 4 40 MHz

—416MHz

Measured using clock
division — typically /16

Lower limit 1.6 3.7

(3)

Upper limit 24 56

—20150MHz

Doc ID 14723 Rev 8 79/115

(1)

Val ue

Unit

Min Max

20 150 MHz

SYS

ns

MHz

Electrical characteristics SPC560P44Lx, SPC560P50Lx

Table 31. FMPLL electrical characteristics (continued)

Val ue

Unit

Symbol C Parameter Conditions

(1)

Min Max

Short-term jitter

C

JITTER

CLKOUT period

T

jitter

(6),(7),(8),(9)

Long-term jitter (avg.
over 2 ms interval)

t

lpll

t

dc

f

LCK

f

UL

f

CS

f

DS

f

MOD

1. V

DD_LV_CORx

2. Considering operation with PLL not bypassed

3. “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self-clocked mode.

4. Self-clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the f
window.

5. f

VCO

mode.

6. This value is determined by the crystal manufacturer and board design.

7. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via V
percentage for a given interval.

8. Proper PC board layout procedures must be followed to achieve specifications.

9. Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C
fCS or f

10. Short term jitter is measured on the clock rising edge at cycle n and cycle n+4.

11. This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this
PLL, load capacitors should not exceed these limits.

12. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR).

13. This value is true when operating at frequencies above 60 MHz, otherwise f

14. Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.

DPLL lock time

D Duty cycle of reference

D Frequency LOCK range — 66% f

D Frequency un-LOCK range — -18 18 % f

D Modulation depth

D Modulation frequency

= 1.2 V ±10%; VSS = 0 V; TA = –40 to 125 °C, unless otherwise specified

self clock range is 20–150 MHz. f

(depending on whether center spread or down spread modulation is enabled).

DS

(11), (12)

SCM

DDPLL

(14)

represents f

and V

SSPLL

(10)

f

maximum 44%f

SYS

= 16 MHz

f

PLLIN

(resonator), f

PLLCLK

at

—10 ns

64 MHz, 4000 cycles

——200µs

—4060%

Center spread ±0.25 ±4.0

(13)

Down spread 0.5 8.0

— — 70 kHz

after PLL output divider (ERFD) of 2 through 16 in enhanced

SYS

and variation in crystal oscillator frequency increase the C

JITTER

is 2% (above 64 MHz).

CS

CLKOUT

% f

LOR

.

SYS

JITTER

and either

SYS

SYS

SYS

80/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Electrical characteristics

3.13 16 MHz RC oscillator electrical characteristics

Table 32. 16 MHz RC oscillator electrical characteristics

Value

Symbol C Parameter Conditions

Min Typ Max

f

RC

P RC oscillator frequency TA = 25 °C — 16 — MHz

Fast internal RC oscillator variation over temperature



RCMVAR

and

P

supply with respect to f

at TA = 25 °C in high-

RC

—–5—5%

frequency configuration

(1)



RCMTRIM



RCMSTEP

1. PTF = Post Trimming Frequency: The frequency of the output clock after trimming at typical supply voltage and
temperature

Post Trim Accuracy: The variation of the PTF

T

the 16 MHz

T Fast internal RC oscillator trimming step TA = 25 °C — 1.6 — %

from

T

= 25 °C –1 — 1 %

A

3.14 Analog-to-digital converter (ADC) electrical characteristics

The device provides a 10-bit successive approximation register (SAR) analog-to-digital
converter.

Unit

Doc ID 14723 Rev 8 81/115

Electrical characteristics SPC560P44Lx, SPC560P50Lx

(2)

(1)

(3)

(4)

(5)

Offset Error OSE

Offset Error OSE

Gain Error GE

1 LSB (ideal)

1023

1022

1021

1020

1019

1018

5

4

3

2

1

0

7

6

1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) Differential non-linearity error (DNL)

(4) Integral non-linearity error (INL)

(5) Center of a step of the actual transfer curve

1 LSB ideal = V

DD_ADC

/ 1024

V

in(A)

(LSB

ideal

)

code out

Figure 15. ADC characteristics and error definitions

3.14.1 Input impedance and ADC accuracy

To preserve the accuracy of the A/D converter, it is necessary that analog input pins have

82/115 Doc ID 14723 Rev 8

low AC impedance. Placing a capacitor with good high frequency characteristics at the input
pin of the device can be effective: the capacitor should be as large as possible, ideally
infinite. This capacitor contributes to attenuating the noise present on the input pin; further, it
sources charge during the sampling phase, when the analog signal source is a high­impedance source.

A real filter can typically be obtained by using a series resistance with a capacitor on the
input pin (simple RC filter). The RC filtering may be limited according to the source
impedance value of the transducer or circuit supplying the analog signal to be measured.

SPC560P44Lx, SPC560P50Lx Electrical characteristics

V

A

RSRF+

R

EQ

-------------------- -



1
2

-- -LSB



R

F

C

F

R

S

R

L

R

SW1

C

P2

C

S

V

DD

Sampling

Source Filter Current Limiter

EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME

C

P1

R

AD

Channel

Selection

V

A

RS: Source impedance

R

F

: Filter resistance

C

F

: Filter capacitance

R

L

: Current limiter resistance

R

SW1

: Channel selection switch impedance

R

AD

: Sampling switch impedance

C

P

: Pin capacitance (two contributions, C

P1

and CP2)

C

S

: Sampling capacitance

The filter at the input pins must be designed taking into account the dynamic characteristics
of the input signal (bandwidth) and the equivalent input impedance of the ADC itself.

In fact a current sink contributor is represented by the charge sharing effects with the
sampling capacitance: C

and CP2 being substantially two switched capacitances, with a

S

frequency equal to the ADC conversion rate, it can be seen as a resistive path to ground.
For instance, assuming a conversion rate of 1 MHz, with C
of 330 k is obtained (R

= 1 / (fc × (CS+CP2)), where fc represents the conversion rate at

EQ

equal to 3 pF, a resistance

S+CP2

the considered channel). To minimize the error induced by the voltage partitioning between
this resistance (sampled voltage on C

) and the sum of RS + RF, the external circuit

S+CP2

must be designed to respect the Equation 4:

Equation 4

Equation 4 generates a constraint for external network design, in particular on resistive

path.

Figure 16. Input equivalent circuit

Doc ID 14723 Rev 8 83/115

Electrical characteristics SPC560P44Lx, SPC560P50Lx

V

A

V

A1

V

A2

t

T

S

V

CS

Voltage Transient on C

S

V <0.5 LSB

1

2

1 < (RSW + RAD) CS << T

S

2 = RL (CS + CP1 + CP2)



1

R

SWRAD

+=

CPC

S



CPCS+

-------------------- -



1R

SWRAD

+ CSTS«

A second aspect involving the capacitance network shall be considered. Assuming the three
capacitances C

, CP1 and C

F

are initially charged at the source voltage VA (refer to the

P2

equivalent circuit reported in Figure 16): A charge sharing phenomenon is installed when
the sampling phase is started (A/D switch closed).

Figure 17. Transient behavior during sampling phase

In particular two different transient periods can be distinguished:

● A first and quick charge transfer from the internal capacitance C

sampling capacitance C

occurs (CS is supposed initially completely discharged):

S

and CP2 to the

P1

considering a worst case (since the time constant in reality would be faster) in which
C

is reported in parallel to C

P2

C

are in series, and the time constant is

S

(call CP = CP1 + CP2), the two capacitances CP and

P1

Equation 5

Equation 5 can again be simplified considering only CS as an additional worst

condition. In reality, the transient is faster, but the A/D converter circuitry has been
designed to be robust also in the very worst case: the sampling time T

is always much

S

longer than the internal time constant:

Equation 6

The charge of C
voltage V

A1

and CP2 is redistributed also on CS, determining a new value of the

P1

on the capacitance according to Equation 7:

84/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Electrical characteristics

V

A1CSCP1CP2

++ VAC

P1CP2

+=

2R

L

 C

SCP1CP2

++

8.5 2 8.5 R

LCSCP1CP2

++=T

S



V

A2CSCP1CP2CF

+++ VAC

F

 V

A1

+CP1CP2+C

S

+=

f

0

f

Analog Source Bandwidth (VA)

f

0

f

Sampled Signal Spectrum (fC = conversion Rate)

f

C

f

Anti-Aliasing Filter (fF = RC Filter pole)

f

F

2 f0 fC (Nyquist)

f

F

 f0 (Anti-aliasing Filtering Condition)

T

C

2 RFCF (Conversion Rate vs. Filter Pole)

Noise

Equation 7

● A second charge transfer involves also C

capacitance) through the resistance R
and C

were in parallel to CP1 (since the time constant in reality would be faster), the

S

(that is typically bigger than the on-chip

F

: again considering the worst case in which CP2

L

time constant is:

Equation 8

In this case, the time constant depends on the external circuit: in particular imposing
that the transient is completed well before the end of sampling time T
R

sizing is obtained:

L

, a constraints on

S

Equation 9

Of course, R
combination with R
definitively bigger than C
charge transfer transient) will be much higher than V
(charge balance assuming now C

shall be sized also according to the current limitation constraints, in

L

(source impedance) and RF (filter resistance). Being CF

S

, CP2 and CS, then the final voltage V

P1

already charged at VA1):

S

. Equation 10 must be respected

A1

(at the end of the

A2

Equation 10

The two transients above are not influenced by the voltage source that, due to the presence
of the R
C

with respect to the ideal source VA; the time constant RFCF of the filter is very high with

S

filter, is not able to provide the extra charge to compensate the voltage drop on

FCF

respect to the sampling time (T

Figure 18. Spectral representation of input signal

). The filter is typically designed to act as anti-aliasing.

S

Doc ID 14723 Rev 8 85/115

Electrical characteristics SPC560P44Lx, SPC560P50Lx

V

A

V

A2

----------- -

C

P1CP2

+C

F

+

C

P1CP2

+CFC

S

++

------------------------------------------------------- -=

CF2048 C

S



Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of
the anti-aliasing filter, f
at least 2f

; it means that the constant time of the filter is greater than or at least equal to

0

twice the conversion period (T
sampling time T

S

), according to the Nyquist theorem the conversion rate fC must be

F

). Again the conversion period TC is longer than the

C

, which is just a portion of it, even when fixed channel continuous
conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it
is evident that the time constant of the filter R
sampling time T

, so the charge level on CS cannot be modified by the analog signal source

S

is definitively much higher than the

FCF

during the time in which the sampling switch is closed.

The considerations above lead to impose new constraints on the external circuit, to reduce
the accuracy error due to the voltage drop on C
above, it is simple to derive Equation 11 between the ideal and real sampled voltage on C

; from the two charge balance equations

S

S

Equation 11

:

From this formula, in the worst case (when V
assuming to accept a maximum error of half a count, a constraint is evident on C

Equation 12

3.14.2 ADC conversion characteristics

Table 33. ADC conversion characteristics

Symbol C Parameter Conditions

V

INAN0

V

INAN1

f

CK

f

s

t

ADC_S

t

ADC_C

ADC0 and shared ADC0/1

SR

analog input voltage

ADC1 analog input voltage

SR

(4)

(2), (3)

(2),

—

—

ADC clock frequency
(depends on ADC
configuration)

SR —

(The duty cycle depends on

(5)

AD_clk

frequency)

—3

SR — Sampling frequency — — — 1.53 MHz

f

= 20 MHz,

ADC

— D Sample time

(7)

INPSAMP = 3

f

= 9 MHz,

ADC

INPSAMP = 255

f

— P Conversion time

(8)

= 20 MHz

ADC

INPCMP = 1

is maximum, that is for instance 5 V),

A

(1)

Value

Min Typ Max

V

SS_HV_ADV0

0.3

V

SS_HV_ADV1

0.3

(6)

V

DD_HV_ADV0

—

—

+ 0.3

V

DD_HV_ADV1

+ 0.3

—60MHz

125 — — ns

— — 28.2 µs

(9)

,

0.650 — — µs

value:

F

Unit

V

V

86/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Electrical characteristics

Table 33. ADC conversion characteristics (continued)

Symbol C Parameter Conditions

(1)

Min Typ Max

ADC power-up delay (time

t

ADC_PU

needed for ADC to settle

SR —

exiting from software power

———1.5µs

down; PWDN bit = 0)

ADC input sampling

—D

capacitance

———2.5pF

— D ADC input pin capacitance 1 — — — 3 pF

— D ADC input pin capacitance 2 — — — 1 pF

=

=

——0.6k

——3k

———2k

Internal resistance of analog

—D

source

Internal resistance of analog

—D

source

V

DD_HV_ADC

5 V ± 10%

V

DD_HV_ADC

3.3 V ± 10%

R

C

C

C

R

S

P1

P2

SW1

AD

(10)

(10)

(10)

(10)

(10)

Current injection
on one ADC input,

I

— T Input current injection

INJ

different from the
converted one.

–5 — 5 mA

Remains within
TUE spec.

INL CC P Integral non-linearity No overload –1.5 — 1.5 LSB

DNL CC P Differential non-linearity No overload –1.0 — 1.0 LSB

OSE

CC T Offset error — — ±1 — LSB

Value

Unit

GE

CC T Gain error — — ±1 — LSB

TUE CC P

TUE CC T

1. VDD = 3.3 V to 3.6 V / 4.5 V to 5.5 V, TA = –40 °C to T
V

SS_HV_ADCx

2. V

3. Not allowed to refer this voltage to V

4. Not allowed to refer this voltage to V

5. AD_clk clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.

6. When configured to allow 60 MHz ADC, the minimum ADC clock speed is 9 MHz, below which precision is lost.

7. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal

8. This parameter includes the sample time t

9. 20 MHz ADC clock. Specific prescaler is programmed on MC_PLL_CLK to provide 20 MHz clock to the ADC.

10. See Figure 16.

may exceed V

AINx

conversion will be clamped respectively to 0x000 or 0x3FF.

resistance of the analog source must allow the capacitance to reach its final voltage level within t
sample time t
clock t

ADC_S

Total unadjusted error
without current injection

Total unadjusted error with
current injection

to V

DD_HV_ADCx

SS_HV_AD

, changes of the analog input voltage have no effect on the conversion result. Values for the sample

ADC_S

depend on programming.

.

and V

DD_HV_AD

DD_HV_ADV1

DD_HV_ADV0

ADC_S

limits, remaining on absolute maximum ratings, but the results of the

, V

SS_HV_ADV1

, V

SS_HV_ADV0

.

— –2.5 — 2.5 LSB

—–3—3LSB

, unless otherwise specified and analog input voltage from

A MAX

. After the end of the

ADC_S

Doc ID 14723 Rev 8 87/115

Electrical characteristics SPC560P44Lx, SPC560P50Lx

3.15 Flash memory electrical characteristics

Table 34. Program and erase specifications

Value

Symbol C Parameter

Min Typical

T

dwprogram

T

BKPRG

T

16kpperase

T

32kpperase

T

128kpperase

1. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change
pending device characterization.

2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.

3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values
are characterized but not guaranteed.

4. Actual hardware programming times. This does not include software overhead.

5. Typical Bank programming time assumes that all cells are programmed in a single pulse. In reality some cells will require
more than one pulse, adding a small overhead to total bank programming time (see Initial Max column).

P Double Word (64 bits) Program Time

P Bank Program (512 KB)

P Bank Program (64 KB)

(4)(5)

(4)(5)

P 16 KB Block Pre-program and Erase Time — 300 500 5000 ms

P 32 KB Block Pre-program and Erase Time — 400 600 5000 ms

128 KB Block Pre-program and Erase

P

Time

(4)

—2250500µs

— 1.45 1.65 33 s

— 0.18 0.21 4.10 s

— 800 1300 7500 ms

(1)

Initial

max

(2)

Max

(3)

Unit

Table 35. Flash memory module life

Value

Symbol C Parameter Conditions

Min Typ

Number of program/erase cycles per block

P/E C

for 16 KB blocks over the operating
temperature range (T

)

J

— 100000 — cycles

Number of program/erase cycles per block

P/E C

for 32 KB blocks over the operating
temperature range (T

)

J

— 10000 100000 cycles

Number of program/erase cycles per block

P/E C

Retention C

1. Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature
range.

for 128 KB blocks over the operating
temperature range (T

Minimum data retention at 85 °C average
ambient temperature

(1)

)

J

— 1000 100000 cycles

Blocks with 0–1000 P/E
cycles

Blocks with 10000 P/E
cycles

Blocks with 100000 P/E
cycles

20 — years

10 — years

5—years

Unit

88/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Electrical characteristics

Table 36. Flash memory read access timing

Symbol C Parameter Conditions

(1)

Max value Unit

f

max

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified

Maximum working frequency at given number of

C

wait states in worst conditions

3.16 AC specifications

3.16.1 Pad AC specifications

Table 37. Output pin transition times

Symbol C Parameter Conditions

t

tr

t

tr

t

tr

(3)

t

SYM

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 °C to T

includes device and package capacitances (C

2. C

L

3. Transition timing of both positive and negative slopes will differ maximum 50%

D

TC

DC

CC

Output transition time output pin
SLOW configuration

DC

(2)

TC

DC

D

TC

DC

CC

Output transition time output pin
MEDIUM configuration

DC

(2)

TC

DC

(2)

A MAX

PKG

< 5 pF).

CC D

CC T

Output transition time output pin
FAST configuration

Symmetric transition time, same drive
strength between N and P transistor

= 25 pF

C

L

= 50 pF — — 100

L

= 100 pF — — 125

L

= 25 pF

L

= 50 pF — — 50

L

= 100 pF — — 75

L

= 25 pF

C

L

= 50 pF — — 20

L

= 100 pF — — 40

L

= 25 pF

L

= 50 pF — — 25

L

= 100 pF — — 40

L

= 25 pF

C

L

C

= 50 pF — — 6

L

= 100 pF — — 12

C

L

C

= 25 pF

L

= 50 pF — — 7

C

L

C

= 100 pF — — 12

L

= 5.0 V ± 10%, PAD3V5V = 0 — — 4

V

DD

= 3.3 V ± 10%, PAD3V5V = 1 — — 5

V

DD

, unless otherwise specified

V

DD

PAD3V5V = 0

V

DD

PAD3V5V = 1

V

DD

PAD3V5V = 0
SIUL.PCRx.SRC = 1

V

DD

PAD3V5V = 1
SIUL.PCRx.SRC = 1

V

DD

PAD3V5V = 0
SIUL.PCRx.SRC = 1

V

DD

PAD3V5V = 1
SIUL.PCRx.SRC = 1

2 wait states 66

0 wait states 18

(1)

= 5.0 V ± 10%,

= 3.3 V ± 10%,

= 5.0 V ± 10%,

= 3.3 V ± 10%,

= 5.0 V ± 10%,

= 3.3 V ± 10%,

MHz

Value

Unit

Min Typ Max

——50

ns

——40

——10

ns

——12

—— 4

ns

—— 4

ns

Doc ID 14723 Rev 8 89/115

Electrical characteristics SPC560P44Lx, SPC560P50Lx

V

DD_HV_IOx

/2

V

OH

V

OL

Rising
Edge
Output
Delay

Falling
Edge
Output
Delay

Pad
Data Input

Pad
Output

V

IL

V

DD

device reset forced by V

RESET

V

DDMIN

V

RESET

V

IH

device start-up phase

T

POR

Figure 19. Pad output delay

3.17 AC timing characteristics

3.17.1 RESET pin characteristics

The SPC560P44Lx, SPC560P50Lx implements a dedicated bidirectional RESET pin.

Figure 20. Start-up reset requirements

90/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Electrical characteristics

V

RESET

V

IL

V

IH

V

DD

filtered by
hysteresis

filtered by
lowpass filter

W

FRST

W

NFRST

hw_rst

‘1’

‘0’

filtered by
lowpass filter

W

FRST

unknown reset
state

device under hardware reset

Figure 21. Noise filtering on reset signal

Table 38. RESET electrical characteristics

Symbol C Parameter Conditions

V

IH

V

IL

V

HYS

V

OL

Input High Level CMOS

SR P

(Schmitt Trigger)

Input low Level CMOS

SR P

(Schmitt Trigger)

Input hysteresis CMOS

CC C

(Schmitt Trigger)

CC P Output low level

Push Pull, I

= 5.0 V ± 10%, PAD3V5V = 0

V

DD

OL

= 2mA,

(recommended)

Push Pull, I
V

= 5.0 V ± 10%, PAD3V5V = 1

DD

Push Pull, I
V

= 3.3 V ± 10%, PAD3V5V = 1

DD

OL

OL

= 1mA,

= 1mA,

(recommended)

(1)

Value

Min Typ Max

—0.65V

—VDD+0.4 V

DD

— –0.4 — 0.35V

—0.1V

DD

——V

——0.1V

(2)

——0.1V

——0.5

DD

DD

DD

Unit

V

V

Doc ID 14723 Rev 8 91/115

Electrical characteristics SPC560P44Lx, SPC560P50Lx

Table 38. RESET electrical characteristics (continued)

Symbol C Parameter Conditions

= 25pF,

C

L

= 5.0 V ± 10%, PAD3V5V = 0

V

DD

= 50pF,

C

L

V

= 5.0 V ± 10%, PAD3V5V = 0

DD

C

= 100pF,

L

V

= 5.0 V ± 10%, PAD3V5V = 0

DD

= 25pF,

C

L

= 3.3 V ± 10%, PAD3V5V = 1

V

DD

= 50pF,

C

L

V

= 3.3 V ± 10%, PAD3V5V = 1

DD

C

= 100pF,

L

V

= 3.3 V ± 10%, PAD3V5V = 1

DD

W

W

t

tr

FRST

NFRST

Output transition time

CC D

output pin
MEDIUM configuration

RESET

SR P

pulse

RESET

SR P

filtered pulse

(3)

input filtered

input not

Maximum delay before
internal reset is

CC D

t

POR

released after all
V

reach nominal

DD_HV

Monotonic V

DD_HV

supply

(1)

Value

Unit

Min Typ Max

——10

——20

——40

ns

——12

——25

——40

———40ns

— 500 — — ns

supply ramp — — 1 ms

= 3.3 V ± 10%, PAD3V5V = 1 10 — 150

V

|I

|CCP

WPU

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 °C to T

2. This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of device
reference manual).

includes device and package capacitance (C

3. C

L

4. The configuration PAD3V5 = 1 when V
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

Weak pull-up current
absolute value

DD

= 5.0 V ± 10%, PAD3V5V = 0 10 — 150

DD

= 5.0 V ± 10%, PAD3V5V = 1

V

DD

, unless otherwise specified

A MAX

<5pF).

PKG

= 5 V is only transient configuration during power-up. All pads but RESET and

DD

(4)

10 — 250

3.17.2 IEEE 1149.1 interface timing

JCYC

JDC

TCKRISE

Value

Min Max

CC D TCK cycle time — 100 — ns

CC D TCK clock pulse width (measured at V

DD_HV_IOx

/2) — 40 60 ns

CC D TCK rise and fall times (40% – 70%) — — 3 ns

CC D TMS, TDI data setup time — 5 — ns

Table 39. JTAG pin AC electrical characteristics

No. Symbol C Parameter Conditions

1t

2t

3t

4t

TMSS, tTDIS

µAV

Unit

92/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Electrical characteristics

TCK

1

2

2

3

3

Table 39. JTAG pin AC electrical characteristics (continued)

Value

No. Symbol C Parameter Conditions

Min Max

Unit

5t

TMSH, tTDIH

6t

TDOV

7t

8t

11 t

12 t

13 t

14 t

15 t

TDOI

TDOHZ

BSDV

BSDVZ

BSDHZ

BSDST

BSDHT

CC D TMS, TDI data hold time — 25 — ns

CC D TCK low to TDO data valid — — 40 ns

CC D TCK low to TDO data invalid — 0 — ns

CC D TCK low to TDO high impedance — 40 — ns

CC D TCK falling edge to output valid — — 50 ns

CC D

TCK falling edge to output valid out of high
impedance

— — 50 ns

CC D TCK falling edge to output high impedance — — 50 ns

CC D Boundary scan input valid to TCK rising edge — 50 — ns

CC D TCK rising edge to boundary scan input invalid — 50 — ns

Figure 22. JTAG test clock input timing

Doc ID 14723 Rev 8 93/115

Electrical characteristics SPC560P44Lx, SPC560P50Lx

TCK

4

5

6

7

8

TMS, TDI

TDO

Figure 23. JTAG test access port timing

94/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Electrical characteristics

TCK

Output
Signals

Input
Signals

Output
Signals

11

12

13

14

15

Figure 24. JTAG boundary scan timing

3.17.3 Nexus timing

Table 40. Nexus debug port timing

No. Symbol C Parameter

1t

2t

3t

4t

5t

MCYC

MDOV

MSEOV

EVTOV

TCYC

(1)

CC D MCKO cycle time 32 — — ns

CC D MCKO low to MDO data valid

CC D MCKO low to MSEO data valid

CC D MCKO low to EVTO data valid

CC D TCK cycle time 64

Doc ID 14723 Rev 8 95/115

(2)

(2)

(2)

Value

Unit

Min Typ Max

——6ns

——6ns

——6ns

(3)

——ns

Electrical characteristics SPC560P44Lx, SPC560P50Lx

1

3

4

MCKO

MDO
MSEO
EVTO

Output Data Valid

2

TCK

5

EVTI
EVTO

Table 40. Nexus debug port timing

(1)

(continued)

Value

No. Symbol C Parameter

Min Typ Max

t

NTDIS

6

t

NTMSS

t

NTDIH

7

t

NTMSH

8t

TDOV

9t

1. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal.

2. MDO, MSEO

3. Lower frequency is required to be fully compliant to standard.

TDOI

CC D TDI data setup time 6 — — ns

CC D TMS data setup time 6 — — ns

CC D TDI data hold time 10 — — ns

CC D TMS data hold time 10 — — ns

CC D TCK low to TDO data valid — — 35 ns

CC D TCK low to TDO data invalid 6 — — ns

, and EVTO data is held valid until next MCKO low cycle.

Unit

Figure 25. Nexus output timing

Figure 26. Nexus event trigger and test clock timings

96/115 Doc ID 14723 Rev 8

SPC560P44Lx, SPC560P50Lx Electrical characteristics

TDO

6

7

TMS, TDI

8

TCK

9

Figure 27. Nexus TDI, TMS, TDO timing

3.17.4 External interrupt timing (IRQ pin)

Table 41. External interrupt timing

No. Symbol C Parameter Conditions

1t

2t

IPWH

3t

1. IRQ timing specified at f
SRC = 0b00.

2. Applies when IRQ pins are configured for rising edge or falling edge events, but not both.

3. N = ISR time to clear the flag

CC D IRQ pulse width low — 4 — t

IPWL

CC D IRQ pulse width high — 4 — t

CC D IRQ edge to edge time

ICYC

= 64 MHz and V

SYS

(1)

DD_HV_IOx

(2)

= 3.0 V to 5.5 V, TA = TL to TH, and CL = 200 pF with

—4 + N

Doc ID 14723 Rev 8 97/115

Value

Min Max

(3)

—t

Unit

CYC

CYC

CYC

Electrical characteristics SPC560P44Lx, SPC560P50Lx

IRQ

2

3

1

Figure 28. External interrupt timing

3.17.5 DSPI timing

Table 42. DSPI timing

(1)

No. Symbol C Parameter Conditions

Master (MTFE = 0) 60 —

1t

2t

3t

4t

5t

6t

7t

8t

CC D DSPI cycle time

SCK

CC D CS to SCK delay — 16 — ns

CSC

CC D After SCK delay — 26 — ns

ASC

CC D SCK duty cycle — 0.4 * t

SDC

CC D Slave access time SS active to SOUT valid — 30 ns

A

CC D Slave SOUT disable time

DIS

CC D PCSx to PCSS time — 13 — ns

PCSC

CC D PCSS to PCSx time — 13 — ns

PASC

Slave (MTFE = 0) 60 —

SS

inactive to SOUT high

impedance or invalid

Master (MTFE = 0) 35 —

Slave 4 —

9t

CC D Data setup time for inputs

SUI

Master (MTFE = 1, CPHA = 0) 35 —

Master (MTFE = 1, CPHA = 1) 35 —

Master (MTFE = 0) –5 —

Val ue

Unit

Min Max

ns

SCK

0.6 * t

SCK

ns

—16ns

ns

10 t

CC D Data hold time for inputs

HI

Master (MTFE = 1, CPHA = 0) 11 —

Master (MTFE = 1, CPHA = 1) –5 —

98/115 Doc ID 14723 Rev 8

Slave 4 —

ns

SPC560P44Lx, SPC560P50Lx Electrical characteristics

Data

Last Data

First Data

First Data Data Last Data

SIN

SOUT

PCSx

SCK Output

4

9

12

1

11

10

4

SCK Output

(CPOL=0)

(CPOL=1)

3

2

Note: Numbers shown reference Tab l e 4 2.

Table 42. DSPI timing

(1)

(continued)

No. Symbol C Parameter Conditions

Master (MTFE = 0) — 12

Slave — 36

11 t

CC D Data valid (after SCK edge)

SUO

Master (MTFE = 1, CPHA = 0) — 12

Master (MTFE = 1, CPHA = 1) — 12

Master (MTFE = 0) –2 —

Slave 6 —

12 t

CC D Data hold time for outputs

HO

Master (MTFE = 1, CPHA = 0) 6 —

Master (MTFE = 1, CPHA = 1) –2 —

1. All timing is provided with 50 pF capacitance on output, 1 ns transition time on input signal.

Val ue

Unit

Min Max

ns

ns

Figure 29. DSPI classic SPI timing – Master, CPHA = 0

Doc ID 14723 Rev 8 99/115

Electrical characteristics SPC560P44Lx, SPC560P50Lx

Data

Last Data

First Data

SIN

SOUT

12

11

10

Last Data

Data

First Data

SCK Output

SCK Output

PCSx

9

(CPOL=0)

(CPOL=1)

Note: Numbers shown reference Ta bl e 4 2 .

Last Data

First Data

3

4

1

Data

Data

SIN

SOUT

SS

4

5

6

9

11

10

12

SCK Input

First Data

Last Data

SCK Input

2

(CPOL=0)

(CPOL=1)

Note: Numbers shown reference Ta bl e 4 2 .

Figure 30. DSPI classic SPI timing – Master, CPHA = 1

Figure 31. DSPI classic SPI timing – Slave, CPHA = 0

100/115 Doc ID 14723 Rev 8