Datasheet SP9604JP, SP9604JS, SP9604KP, SP9604KS Datasheet (Sipex Corporation)

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Page 1

SP9604

Quad, 12–Bit, Low Power Voltage

Output D/A Converter

■ Low Cost

■ Four 12–Bit DAC’s on a Single Chip

■ Very Low Power — 30 mW (8mW/DAC)

■ Double-Buffered Inputs

■ + 5V Supply Operation

■ Voltage Outputs, + 4.5V Range

■ Midscale Preset, Zero Volts Out

■ Guaranteed +0.5 LSB Max INL

■ Guaranteed +0.75 LSB Max DNL

■ 250kHz 4-Quadrant Multiplying Bandwidth

■ 28–pin SOIC and Plastic DIP

Packages

■ Either 12 or 8 bit µP bus

DESCRIPTION

The SP9604 is a very low power replacement for the popular SP9345, Quad 12-Bit Digital-toAnalog Converter. It features ±4.5V output swings when using ±5 volt supplies. The converter is double-buffered for easy microprocessor interface. Each 12-bit DAC is independently addressable and all DACs may be simultaneously updated using a single transfer command. The output settling-time is specified at 30µs. The SP9604 is available in 28–pin SOIC and plastic DIP packages, specified over commercial temperature range.

Ref In

INPUT

REGISTERS

DATA

INPUTS 8 MSB's

4 LSB's

LATCH

DAC

REGISTERS

LATCH

A1 CS WR1 B1/B2 WR2 XFER CLRA0

DACLATCH

DAC

DACLATCH

DAC

CONTROL LOGIC

– +

VOUT1

VOUT2

VOUT3

VOUT4

Page 2

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of the device at these or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

VDD - GND .....................................................................-0.3V,+6.0V

VSS - GND .................................................................... +0.3V, -6.0V

......................................................................................................................

VDD - V

..................................................................................... VSS, V

REF

DIN....................................................................................... VSS, V

Power Dissipation

Plastic DIP .......................................................................... 375mW

(derate 7mW/°C above +70°C)

Small Outline ...................................................................... 375mW

(derate 7mW/˚C above +70˚C)

-0.3V, +12.0V

DD DD

SPECIFICATIONS

(Typical @ 25˚C, T

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS DIGITAL INPUTS

Logic Levels

V V

4 Quad, Bipolar Coding Offset Binary

REFERENCE INPUT

Voltage Range +3 +4.5 Volts Note 5 Input Resistance 1.5 2.2 kΩ DIN = 1,877; code dependent

ANALOG OUTPUT

Gain

-K +0.5 +2.0 LSB V

-J +1.0 +4.0 LSB V

Initial Offset Bipolar +0.25 +3.0 LSB DIN = 2,048 Voltage Range Bipolar +3.0 +4.5 Volts Output Current +5.0 mA V

STATIC PERFORMANCE

Resolution 12 Bits Integral Linearity

-K +0.25 +0.5 LSB V

-J +0.5 +1.0 LSB V

Differential Linearity

-K +0.25 +0.75 LSB

-J +0.25 +1.0 LSB

Monotonicity Guaranteed

DYNAMIC PERFORMANCE

Settling Time

Small Signal 4 µs to 0.024%

Full Scale 30 µs to 0.024% Slew Rate 0.3 V/µs Multiplying Bandwidth 250 KHz

≤ TA≤T

MIN

; VDD = +5V, VSS = -5V, V

MAX

= +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)

REF

2.4 Volts

0.8 Volts

= +3V; Note 3

REF

= +3V; Note 3

+1.0 +5.0 LSB V

+0.5 mA V

+0.5 +3.0 LSB V

REF

= +4.5V; Note 3

REF

= +3V

REF

= +4.5V

REF

= +3V; Note 3

REF

= +3V; Note 3

REF

= +4.5V; Note 3

REF

Page 3

SPECIFICATIONS (continued)

(Typical @ 25˚C, T

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS STABILITY

Gain 15 ppm/˚C t Bipolar Zero 15 ppm/˚C t

SWITCHING CHARACTERISTICS

tDS Data Set Up Time 140 100 ns to rising edge of WR1 tDN Data Hold Time 0 ns Figure 4 tWR Write Pulse Width 140 100 ns t

XFER

tWC Total Write Command 280 200 ns POWER REQUIREMENTS Note 5

–J, –K 3 4 mA V

–J, –K 3 4 mA Power Dissipation 30 mW

ENVIRONMENTAL AND MECHANICAL

Operating Temperature

-J, -K 0 +70 °C Storage -60 +150 °C Package

-_P 28-pin Plastic DIP

-_S 28-pin SOIC Notes:

1. Integral Linearity, for the SP9604, is measured as the arithmetic mean value of the magnitudes of

2. Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two

3. 1 LSB = 2*V

4. V

5. The following power up sequence is recommended to avoid latch up: VSS (-5V), VDD (+5V), REF IN.

≤ TA≤T

MIN

; VDD = +5V, VSS = -5V, V

MAX

= +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)

REF

to t

MIN

MAX

to t

MIN

MAX

Transfer Pulse Width 140 100 ns

+5V, +3%; Note 4, 5

-5V, +3%; Note 4, 5

the greatest positive deviation and the greatest negative deviation from the theoretical value for any given input condition.

adjacent digital input codes.

/4,096.

REF

= 0V.

REF

+0.25 lsb DNLE

-0.25 lsb +0.25 lsb INLE

-0.25 lsb

0 CODE 4095

DNLE, INLE Plots

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PIN ASSIGNMENTS

Pin 1 — V

— Voltage Output from DAC4.

OUT 4

Pin 2 — VSS — –5V Power Supply Input. Pin 3 — VDD — +5V Power Supply Input. Pin 4 — CLR — Clear. Gated with WR2 (pin 11).

Active low. Clears all DAC outputs to 0V. Pin 5 — REF IN — Reference Input for DACs. Pin 6 — GND — Ground. Pin 7 — B1/B2 — Byte 1/Byte 2 — Selects Data

Input Format. A logic “1” on pin 7 selects the 12–bit mode, and all 12 data bits are presented to the DAC(s) unchanged; a logic “0” selects the 8–bit mode, and the four LSBs are connected to the four MSBs, allowing an 8–bit MSB–justified interface.

PINOUT — 28–PIN PLASTIC DIP & SOIC

REF IN

B1/B2

OUT4

CLR

GND

A A

XFER

WR2 WR1

OUT1

1 2 3 4 5 6 7

SP9604

10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

V DB DB DB DB DB DB DB DB DB DB DB DB V

OUT3

0 1 2 3 4 5 6 7 8 9 10 11

OUT2

Pins 8 and 9 — A0 & A1 — Address for DAC Selection. A1/A0 = 0/0 = DAC1; 0/1 = DAC2; 1/0 = DAC3; 1/1 = DAC4.

Pin 10 — XFER — Transfer. Gated with WR2 (pin

11); loads all DAC registers simultaneously. Active low.

Pin 11 — WR2 — Write Input 2 — In conjunction with XFER (pin 10), controls the transfer of data from the input registers to the DAC registers. In conjunction with CLR (pin 4), the DAC registers are forced to 1000 0000 0000 and the DAC outputs will settle to 0V. Active low.

Pin 12 — WR1 — Write Input1 — In conjunction with CS (pin 13), enables input register selection, and controls the transfer of data from the input bus to the input registers. Active low.

Pin 13 — CS — Chip Select — Enables writing data to input registers and/or transferring data from input bus to DAC registers. Active low.

Pin 14 — V Pin 15 — V

— Voltage Output from DAC1.

OUT1

— Voltage Output from DAC2.

OUT2

Pin 16 — DB11 — Data Bit 11; Most Significant Bit. Pin 17 — DB10 — Data Bit 10. Pin 18 — DB9 — Data Bit 9. Pin 19 — DB8 — Data Bit 8. Pin 20 — DB7 — Data Bit 7. Pin 21 — DB6 — Data Bit 6. Pin 22 — DB5 — Data Bit 5. Pin 23 — DB4 — Data Bit 4. Pin 24 — DB3 — Data Bit 3. Pin 25 — DB2 — Data Bit 2. Pin 26 — DB1 — Data Bit 1. Pin 27 — DB0 — Data Bit 0; LSB Pin 28 — V

— Voltage Output from DAC3.

OUT3

Page 5

FEATURES

The SP9604 is a low–power replacement for the popular SP9345, Quad 12-Bit Digital-to-Analog Converter. This Quad, Voltage Output, 12-Bit Digital-toAnalog Converter features ±4.5V output swings when using ±5 volt supplies. The input coding format used is standard offset binary. (Please refer to Table 1.)

The converter utilizes double-buffering on each of the 12 parallel digital inputs, for easy microprocessor interface. Each 12-bit DAC is independently addressable and all DACs may be simultaneously updated using a single XFER command. The output settlingtime is specified at 30µs to full 12–bit accuracy when driving a 5Kohm, 50pf load combination. The SP9604, Quad 12-Bit Digital-to-Analog Converter is ideally suited for applications such as ATE, process controllers, robotics, and instrumentation. The SP9604 is available in 28–pin plastic DIP or SOIC packages, specified over the commercial (0°C to +70°C) temperature range.

THEORY OF OPERATION

The SP9604 consists of five main functional blocks — input data multiplexer, data registers, control logic, four 12-bit D/A converters, and four bipolar output voltage amplifiers. The input data multiplexer is designed to interface to either 12- or 8-bit microprocessor data busses. The input data format is controlled by the B1/B2 signal — a logic “1” selects the 12-bit mode, while a logic “0” selects the 8-bit mode. In the 12-bit mode the data is transferred to the input registers without changes in its format. In the 8-bit mode, the four least significant bits (LSBs) are connected to the four most significant bits (MSBs), allowing an 8-bit MSB-justified interface. All data inputs are enabled

INPUT OUTPUT

MSB LSB

1111 1111 1111 VREF - 1 LSB 1111 1111 1110 VREF - 2 LSB 1000 0000 0001 0 + 1 LSB 1000 0000 0000 0 0000 0000 0001 -VREF + 1 LSB 0000 0000 0000 -VREF

1 LSB =

Table 1. Offset Binary Coding

REF

using the CS signal in both modes. The digital inputs are designed to be both TTL and 5V CMOS compatible.

In order to reduce the DAC full scale output sensitivity to the large weighting of the MSB’s found in conventional R-2R resistor ladders, the 3 MSB’s are decoded into 8 equally weighted levels. This reduces the contribution of each bit by a factor of 4, thus, reducing the output sensitivity to mis–matches in resistors and switches by the same amount. Linearity errors and stability are both improved for the same reasons.

Each D/A converter is separated from the data bus by two registers, each consisting of level-triggered latches, Figure 1. The first register (input register) is 12-bits wide. The input register is selected by the address input A0 and A1 and is enabled by the CS and WR1 signals. In the 8-bit mode, the enable signal to the 8 MSB’s is disabled by a logic low on B1/B2 to allow the 4 LSB’s to be updated. The second register (DAC register), accepts the decoded 3 MSB’s plus the 9 LSB’s. The four DAC registers are updated simultaneously for all DAC’s using the XFER and WR2 signals. Using the CLR and WR2 signals or the power-on-reset, (enabled when the power is switched on) the DAC registers are set to 1000 0000 0000 and the DAC outputs will settle to 0V.

Using the control logic inputs, the user has full control of address decoding, chip enable, data transfer and clearing of the DAC’s. The control logic inputs are level triggered, and like the data inputs, are TTL and CMOS compatible. The truth table (Table 2) shows the appropriate functions associated with the states of the control logic inputs.

The DACs themselves are implemented with a precision thin–film resistor network and CMOS transmission gate switches. Each D/A converter is used to convert the 12–bit input from its DAC register to a precision voltage.

The bipolar voltage output of the SP9604 is created on-chip from the DAC Voltage Output (V using an operational amplifier and two feedback

DAC

) by

resistors connected as shown in Figure 2. This configuration produces a ±4.5V bipolar output range with standard offset binary coding.

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DAC

Ref In

40 KΩ 40 KΩ

–

VOUT

INPUT

DB11 - DB8

DB7 - DB4

DB3 - DB0

Figure 1. Detailed Block Diagram (only one DAC shown)

44 44

MUX

4 4 4

8–BIT

LATCH

4-BIT

LATCH

USING THE SP9604 WITH DOUBLE-BUFFERED INPUTS Loading Data

To load a 12-bit word to the input register of each DAC, using a 12-bit data bus, the sequence is as follows:

DAC

3 TO 7

DECODE

5 BITS

LATCH

To load a 12-bit word to the input register of each DAC, using an 8-bit data bus, the sequence is as follows:

1) Set XFER=1, B1/B2=1, CLR=1, WR1=1, WR2=1, CS=1.

2) Set D11 through D4 to the 8 MSB’s of the desired digital input code.

1) Set XFER=1, B1/B2=1, CLR=1, WR1=1, WR2=1, CS=1.

2) Set A1 and A0 (the DAC address) to the desired DAC — 0,0 = DAC1; 0,1 = DAC 1,0 = DAC3; 1,1 = DAC4 .

3) Set D11 (MSB) through D0 (LSB) to the desired digital input code.

4) Load the word to the selected DAC by cycling WR1 and CS through the following sequence:

3) Load the 8 MSB’s of the digital word to the selected input register by cycling WR1 and CS through the “1” — “0” — “1” sequence.

4) Reset B1/B2 from “1” —— “0”

5) Set D11 (MSB) through D8 to the 4 LSB’s of the digital input code.

6) Load the 4 LSB’s by cycling WR1 and CS through the “1” — “0” — “1” sequence.

7) Repeat sequence for each input register.

“1” — “0” — “1”

5) Repeat sequence for each input register.

A1A

0 0 1 1 X X Address DAC 1 and load input register 0 0 0 1 X X Address DAC 1 and load 4 LSBs 0 1 1 1 X X Address DAC 2 and load input register 0 1 0 1 X X Address DAC 2 and load 4 LSBs 1 0 1 1 X X Address DAC 3 and load input register 1 0 0 1 X X Address DAC 3 and load 4 LSBs 1 1 1 1 X X Address DAC 4 and load input register 1 1 0 1 X X Address DAC 4 and load 4 LSBs X X ** ** X 1 Transfer data from input registers to DAC registers XXXXX 1 Sets all DAC output voltages to 0V X X 1 1 X 0 0 Temporarily force all DAC output voltages to 0V,

X X 1 X X X X X Invalid state with any other control line active X X X 1 X X X X Invalid state with any other control line active

CS WR1 B1/B2 WR2 XFER CLR FUNCTION

while CLR is low

X = Don’t care; ** = Don’t care; however, CS and WR1 = 1 will inhibit changes to the input registers.

Table 2. Control Logic Truth Table

Page 7

REF IN

DAC

Figure 2. Transfer Function

TRANSFERRING DATA

To transfer the four 12-bit words in the four input registers to the four DAC registers:

1) Set CLR=1, CS=1, WR1=1.

2) Cycle WR2 and XFER through the “1” — “0” — “1” sequence.

To set the outputs of the four DAC’s to 0V, cycle WR2 and CLR through the “1” — “0” — “1” sequence, while keeping XFER=1.

One Latch, or No Latches

The latches that form the registers can be used in a “semi-” transparent mode, and a “fully-” transparent mode. In order to use the SP9604 in either mode the user must be interfaced to a 12-bit bus only (B1=1).

The semi-transparent mode is set up such that the second set of latches is transparent and the first set is used to latch the incoming data. Data is latched into the first set rather than the second set, in order to minimize glitch energy induced from the data formatting. In this mode, XFER, WR2 and CS are tied low, and WR1 is used to strobe the data to the addressed DAC. Each DAC is addressed using the address lines A0 and A1. After the appropriate DAC has been selected and the data is settled at the digital inputs,

Out

DAC

– +

Out

= –1 x

( )

2048

4,096

REF IN

bringing WR1 low will transfer the data to the addressed DAC. The user should be sure to bring WR1 high again so that the next selected DAC will not be overwritten by the last digital code. This mode of operation may be useful in applications where preloading of the input registers is not necessary, Figure 3a.

A fully transparent mode is realized by tying WR1, CS, WR2, and XFER all low. In this mode, anything that is written on the 12-bit data bus will be passed directly to the selected DAC. Since both latches are not being used, the previous digital word will be overwritten by the new data as soon as the address changes. This may be useful should the user want to calibrate a circuit, by taking full scale or zero scale readings for all four DAC’s, Figure 3b.

Zeroing DAC Outputs

While keeping XFER pin high, the DAC outputs can be set to zero volts two different ways. The first involves the CLR and WR2 pins. In normal operation, the CLR pin is tied high, thus, disabling the clear function. By cycling WR2 and CLR through "1"—"0"—"1" sequence, a digital code of 1000 0000 0000 is written to all four DAC registers, producing a half scale output or zero volts. The second utilizes the built in power-

Page 8

on-reset. Using this feature, the SP9604 can be configured such that during power-up, the second register will be digitally “zeroed”, producing a zero volt output at each of the four DAC outputs. This is achieved by powering the unit up with XFER in a high state. Thus, with no external circuitry, the SP9604 can be powered up with the analog outputs at a known, zero volt output level.

Temporarily forcing all DAC outputs to 0V

Set WR1=1, CS=1, WR2=0, XFER=0. The DAC registers can be temporarily forced to 1000 0000 0000 by bringing the CLR pin low. This will force the DAC outputs to 0V, while the CLR pin remains low. When the CLR pin is brought back high, the digital code at the DAC registers will again appear at the DAC's digital inputs, and the analog outputs will return to their previous values.

+3V

Reference

OUT3

OUT4

OUT1

OUT2

GND

+5V –5V

OUT4

CLR

REF IN

GND

B1/B2

SP9604

XFER

WR2

WR1

OUT1

(MSB) DB

OUT3

DB DB DB DB DB DB DB DB DB DB

OUT2

28 27

12–Bit

Data

Bus

DAC Strobe Address

Decode & Control

+3V

Reference

OUT3

OUT4

OUT1

OUT2

GND

+5V –5V

(MSB) DB

OUT3

OUT2

OUT4

CLR

REF IN

GND

B1/B2

SP9604

XFER

WR2

WR1

OUT1

(a) (b)

Figure 3. Latch Control Options — (a) Semi–Transparent Latch Mode; (b) Fully–Transparent Latch Mode

12–Bit Data Bus

Address Decode & Control

WR2

WR1

140ns, t

Loads Input Data to First Set of Latches

XFER

CLR

WR2

140ns, t

Data Transfer from Input Register to DAC's

XFER

Figure 4. Timing

Page 9

D1 = 0.005" min.

(0.127 min.)

e = 0.100 BSC

(2.540 BSC)

PACKAGE: PLASTIC

DUAL–IN–LINE (WIDE)

A1 = 0.015" min.

(0.381min.)

A = 0.25" max.

(6.350 max).

eA = 0.600 BSC

(15.240 BSC)

DIMENSIONS (Inches)

Minimum/Maximum

(mm) A2

24–PIN

0.125/0.195

(3.175/4.953)

0.014/0.022

(0.366/0.559

0.030/0.070

(0.762/1.778)

0.008/0.015

(0.203/0.381)

1.150/1.290

(29.21/32.76)

0.600/0.625

(15.24/15.87)

0.485/0.580

(12.31/14.73)

0.115/0.200

(2.921/5.080)

0°/ 15°

(0°/15°)

28–PIN

0.125/0.195

(3.175/4.953)

0.014/0.022 (0.366/0.559

0.030/0.070

(0.762/1.778)

0.008/0.015

(0.203/0.381)

1.380/1.565

(35.05/39.75)

0.600/0.625

(15.24/15.87)

0.485/0.580

(12.31/14.73)

0.115/0.200

(2.921/5.080)

0°/ 15°

(0°/15°)

32–PIN

0.125/0.195

(3.175/4.953)

0.014/0.022

(0.366/0.559

0.030/0.070

(0.762/1.778)

0.008/0.015

(0.203/0.381)

1.645/1.655

(41.78/42.04)

0.600/0.625

(15.24/15.87)

0.485/0.580

(12.31/14.73)

0.115/0.200

(2.921/5.080)

0°/ 15°

(0°/15°)

40–PIN

0.125/0.195

(3.175/4.953)

0.014/0.022

(0.366/0.559)

0.030/0.070

(0.762/1.778)

0.008/0.015

(0.203/0.381)

1.980/2.095

(50.29/53.21)

0.600/0.625

(15.24/15.87)

0.485/0.580

(12.31/14.73)

0.115/0.200

(2.921/5.080)

0°/ 15°

(0°/15°)

48–PIN

0.125/0.195

(3.175/4.953)

0.014/0.022

(0.366/0.559)

0.030/0.070

(0.762/1.778)

0.008/0.015

(0.203/0.381)

2.385/2.480

(60.57/62.99)

0.600/0.625

(15.24/15.87)

0.485/0.580

(12.31/14.73)

0.115/0.200

(2.921/5.080)

0°/ 15°

(0°/15°)

Page 10

DIMENSIONS (Inches)

Minimum/Maximum

(mm) A

28–PIN

0.090/0.100 (2.29/2.54)

0.004/0.010

(0.102/0.254)

0.014/0.020 (0.36/0.48)

0.706/0.718

(17.93/18.24)

0.340/0.350 (8.64/8.89)

0.050 BSC

(1.270 BSC)

0.463/0.477

(11.76/12.12)

0.020/0.042 (0.51/1.07)

0°/8°

(0°/8°)

PACKAGE: PLASTIC

SMALL OUTLINE (SOIC)

Page 11

ORDERING INFORMATION

Model Temperature Range Package

Monolithic 12-Bit Quad DAC Voltage Output:

SP9604JP ..................................................................................0˚C to +70˚C ...................................................................... 28-pin, 0.6" Plastic DIP

SP9604KP ................................................................................. 0˚C to +70˚C...................................................................... 28-pin, 0.6" Plastic DIP

SP9604JS ..................................................................................0˚C to +70˚C ............................................................................. 28–pin, 0.35" SOIC

SP9604KS ................................................................................. 0˚C to +70˚C............................................................................. 28–pin, 0.35" SOIC

Please consult the factory for pricing and availability on a Tape-On-Reel option.

Corporation

SIGNAL PROCESSING EXCELLENCE

Sipex Corporation Headquarters and

Sales Office

22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com

Sales Office

233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.

Datasheet SP9604JP, SP9604JS, SP9604KP, SP9604KS Datasheet (Sipex Corporation)

Specifications and Main Features

Frequently Asked Questions

User Manual