Datasheet SP9601AN, SP9601AS, SP9601BN, SP9601BS, SP9601JN Datasheet (Sipex Corporation)

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Page 1

SP9601

12–Bit, Lo w Power Voltage Output D/A Con verter

■ Low Power — 2mW

■ Voltage Output, 4.5V range

■ Midscale Preset, Zero Volts Out

■ 250KHz Multiplying Bandwidth

(4-Quadrant)

■ Standard 3-Wire Serial Interface

■ 8–pin (0.15") SOIC and Plastic DIP

Packages

■ ±5V supply operation

DESCRIPTION…

The SP9601 is a very low power 12-Bit Digital-to-Analog Converter. It features ±4.5V output swings when using ±5 volt supplies. The converter uses a standard 3–wire serial interface compatible with SPI™, QSPI™ and Microwire™. The output settling-time is specified at 30µs. The SP9601 is available in 8–pin 0.15" SOIC and DIP packages, specified over commercial and industrial temperature ranges.

Ref In

DAC

DACLATCH

SHIFT

CS SDI SCK

– +

OUT

Page 2

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of the device at these or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

VDD - GND ..................................................................... -0.3V,+6.0V

VSS - GND ....................................................................+0.3V, -6.0V

......................................................................................................................

VDD - V

..................................................................................... VSS, V

REF

DIN....................................................................................... VSS, V

Power Dissipation

Plastic DIP .......................................................................... 375mW

(derate 7mW/°C above +70°C)

Plastic LCC ......................................................................... 375mW

(derate 7mW/˚C above +70˚C)

Small Outline ...................................................................... 375mW

(derate 7mW/˚C above +70˚C)

-0.3V, +12.0V

DD DD

SPECIFICATIONS

(Typical at 25˚C; T

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS DIGITAL INPUTS

Logic Levels

V V

4 Quad, Bipolar Coding Offset Binary

REFERENCE INPUT

Voltage Range ±3 ±4.5 Volts Note 5 Input Resistance 6 8.8 kΩ DIN = 1,877; code dependent

ANALOG OUTPUT

Gain

-B, -K ±0.5 ±2.0 LSB V

-A, -J ±1.0 ±4.0 LSB V

Initial Offset Bipolar ±0.25 ±3.0 LSB DIN = 2,048 Voltage Range Bipolar ±3.0 ±4.5 Volts Output Current ±5.0 mA V

STATIC PERFORMANCE

Resolution 12 Bits Integral Linearity

-B, -K ±0.25 ±0.5 LSB V

-A, -J ±0.5 ±1.0 LSB V

Differential Linearity

-B, -K ±0.25 ±0.75 LSB

-A, -J ±0.25 ±1.0 LSB

Monotonicity Guaranteed

DYNAMIC PERFORMANCE

Settling Time

Small Signal 4 µs to 0.024%

Full Scale 30 µs to 0.024% Slew Rate 0.3 V/µs Multiplying Bandwidth 250 KHz

STABILITY

Gain 15 ppm/˚C t Bipolar Zero 15 ppm/˚C t

≤ TA≤T

MIN

IH IL

; VDD = +5V, VSS = -5V, V

MAX

= +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)

REF

2.4 Volts

0.8 Volts

= ±3V; Note 3

REF

= ±3V; Note 3

±1.0 ±5.0 LSB V

±0.5 mA V

±0.5 ±3.0 LSB V

REF

= ±4.5V; Note 3

REF

= ±3V

REF

= ±4.5V

REF

= ±3V; Note 3

REF

= ±3V; Note 3

REF

= ±4.5V; Note 3

REF

to t

MIN

MAX

to t

MIN

MAX

Page 3

SPECIFICATIONS (continued)

(Typical at 25˚C; T

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS POWER REQUIREMENTS Note 5

-J, -K 0.2 0.3 mA

-A, -B 0.2 0.45 mA

-J, -K 0.2 0.3 mA

-A, -B 0.2 0.45 mA Power Dissipation 2 mW

SWITCHING CHARACTERISTICS

CS Setup Time (t

CSS

SCLK Fall to CS Fall Hold Time (t

CSH0

SCLK Fall to CS Rise Hold Time (t

CSH1

SCLK High Width (tCH)40 ns

SCLK Low Width (tCL)40 ns

DIN Setup Time (tDS)50 ns

≤ TA≤T

MIN

; VDD = +5V, VSS = -5V, V

MAX

= +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)

REF

+5V, ±3%; Note 4, 5

-5V, ±3%; Note 4, 5

)25 ns

)20 ns

)0 ns

DIN Hold Time (tDH)0 ns

CS High Pulse Width (t

)30 ns

CSW

ENVIRONMENTAL AND MECHANICAL

Operating Temperature

-J, -K 0 +70 °C

-A, -B -40 +85 °C Storage -60 +150 °C Package –_N 8-pin Plastic DIP –_S 8-pin 0.15" SOIC

Notes:

1. Integral Linearity, for the SP9601, is measured as the arithmetic mean value of the magnitudes of

the greatest positive deviation and the greatest negative deviation from the theoretical value for any given input condition.

2. Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two

adjacent digital input codes.

3. 1 LSB = 2*V

4. V

REF

= 0V.

REF

/4,096.

5. The following power up sequence is recommended: VSS (-5V), Vdd (+5V), VREF.

Page 4

PINOUT – 8-PIN PLASTIC DIP & SOIC

OUT

SCLK

1 2 3 4

SP9601

REF

GND

THEORY OF OPERATION

The SP9601 consists of four main functional blocks – the input shift register, DAC register, 12-Bit D/A converter and a bipolar output voltage amplifier, Figure 1.

The input shift register is used to convert the serial input data stream to a parallel 12–Bit digital word. The input data is shifted on positive clock (SCLK) edges when the Chip Select (CS) signal is in the “low” state. The MSB is loaded first and LSB last. No shifting of the input data occurs when the Chip Select (CS) signal is in the “high” state.

PIN ASSIGNMENTS

Pin 1- V

– Voltage Output.

OUT

Pin 2- VDD – +5V Power Supply Input. Pin 3- SCLK – Serial Clock Input. Pin 4- DIN – Serial Data Input. Pin 5- CS – Chip Select Input. Pin 6- VSS– –5V Power Supply Input. Pin 7- GND – Ground. Pin 8- V

– Reference Input.

REF

FEATURES...

The SP9601 is a low power 12–Bit Digital-toAnalog Converter. The converter features ±4.5V output swings with ±5V supplies. The input coding format used is standard offset binary,

Table 1.

This Digital-to Analog Converter uses a standard 3–wire interface compatible with SPI™, QSPI™ and Microwire™. The output settling time is specified at 30µs to full 12-bit accuracy when driving a 5KΩ, 50pF load combination.

The SP9601 Digital-to-Analog Converter is ideally suited for applications such as ATE, process controllers, robotics and instrumentation. The SP9601 is available in an 8-pin 0.15" SOIC and 0.3" PDIP packages, specified over commercial and industrial temperature ranges.

The DAC register is used to store the digital word which is sent to the DAC. Its value is updated on the positive transition of the Chip Select (CS) signal.

In order to reduce the DAC full scale output sensitivity to the large weighting of the MSB's found in conventional R-2R resistor ladders, the 3 MSB's are decoded into 8 equally weighted levels. This reduces the contribution of each bit by a factor of 4, thus, reducing the output sensitivity to mismatches in resistors and switches by the same amount. Linearity errors and stability are both improved for the same reasons.

The DAC itself is implemented with precision thin-film resistors and CMOS transmission gate switches. The resistor network is laser-trimmed to achieve better than 12–Bit accuracy. The D/ A converter is used to convert the 12-bit input word to a precision voltage.

INPUT OUTPUT

MSB LSB

1111 1111 1111 V 1111 1111 1110 V 1000 0000 0001 0 + 1 LSB 1000 0000 0000 0 0000 0000 0001 -V 0000 0000 0000 -V

1 LSB =

Table 1. Offset Binary Coding

2 V 2

- 1 LSB

REF

- 2 LSB

REF

+ 1 LSB

REF

Page 5

Figure 1. Detailed Block Diagram

SHIFT

121

DAC

LATCH

REF

40KΩ 40KΩ

3 TO 7

DECODE

167

DAC

– +

OUT

The operational amplifier is a rail-to-rail input, rail-to-rail output CMOS amplifier. It is capable of supplying 5mA of load current in the ±3 volt output range. The initial offset voltage is lasertrimmed to improve accuracy. Settling time is 30µs for a full scale output transition to 0.024% accuracy.

The bipolar voltage output of the SP9601 is created on chip from the DAC output voltage (V

) by using an operational amplifier and

DAC

two feedback resistors connected as shown in Figure 2. This configuration produces a ±4.5V bipolar output range with standard offset binary coding, Table 1.

USING THE SP9601

External Reference

The DAC input resistance is code dependent and is minimum at code 1877 and nearly infinite at code 0. Because of the code-dependent nature of the reference a high quality, low output impedance amplifier should be used to drive the V

input.

REF

Serial Clock and Update Rate

The SP9601 maximum serial clock rate (SCLK) is given by 1/(tCH+tCL) which is approximately

12.5 MHz. The digital word update rate is limited by the chip select period, which is 12 X SCLK periods plus the CS high pulse width t This is equal to a 1 µs or 1 MHz update rate.

CSW

However, the DAC settling time to 12–Bits is 30 µs, which for full scale output transitions would limit the update rate to 33 kHz.

Logic Interface

The SP9601 is designed to be compatible with TTL and CMOS logic levels. However, driving the digital inputs with TTL level signals will increase the power consumption of the part by 300 µA. In order to achieve the lowest power consumption use rail-to-rail CMOS levels to drive the digital inputs.

Midscale Preset

By holding CS pin low during Power-up, the DAC output can be forced to 0V. Following Power-up, the CS pin should be kept low as the first digital word is shifted into the shift register. When CS pin is set high, the digital word in the shift register (loaded by the last 12 clock cycles) is latched into the DAC register. Thus, the DAC can be forced to go from midscale (1000 0000 0000, on Power-up) to any digital state, without entering an unknown state.

WHERE

REF

–

DAC

Figure 2. Transfer Function

OUT

DAC

()

2048

()

4096

– 1

x V

REF

Page 6

CSHO

SCLK

DIN

Figure 3. Timing Diagram

DB11

DB9

DB8

DB0

CSH1

CSS

DB10

CSW

Figure 4. Microwire Connection

Figure 5. SPI Connection

SCLK

SP9601

SCLK

SP9601

DIN

N/C

SK SO I/O SI

MICROWIRE

PORT

SK SO I/O SI

SPI

PORT

CPOL = 0, CPHA = 0

+0.25 lsb DNLE

-0.25 lsb +0.25 lsb INLE

-0.25 lsb

0 CODE 4095

DNLE, INLE Plots

Page 7

D1 = 0.005" min.

(0.127 min.)

e = 0.100 BSC

(2.540 BSC)

(BOTH ENDS)

ALTERNATE

END PINS

PACKAGE: PLASTIC

DUAL–IN–LINE (NARROW)

A1 = 0.015" min.

(0.381min.)

A = 0.210" max.

(5.334 max).

eA = 0.300 BSC

(7.620 BSC)

DIMENSIONS (Inches)

Minimum/Maximum

(mm) A2

0.115/0.195

(2.921/4.953)

0.014/0.022

(0.356/0.559)

0.045/0.070

(1.143/1.778)

0.008/0.014

(0.203/0.356)

0.355/0.400

(9.017/10.160)

0.300/0.325

(7.620/8.255)

0.240/0.280

(6.096/7.112)

0.115/0.150

(2.921/3.810)

0°/ 15°

(0°/15°)

0.115/0.195

(2.921/4.953)

0.014/0.022

(0.356/0.559)

0.045/0.070

(1.143/1.778)

0.008/0.014

(0.203/0.356)

0.735/0.775

(18.669/19.685)

0.300/0.325

(7.620/8.255)

0.240/0.280

(6.096/7.112)

0.115/0.150

(2.921/3.810)

0°/ 15°

(0°/15°)

0.115/0.195

(2.921/4.953)

0.014/0.022

(0.356/0.559)

0.045/0.070

(1.143/1.778)

0.008/0.014

(0.203/0.356)

0.780/0.800

(19.812/20.320)

0.300/0.325

(7.620/8.255)

0.240/0.280

(6.096/7.112)

0.115/0.150

(2.921/3.810)

0°/ 15°

(0°/15°)

18–PIN

0.115/0.195

(2.921/4.953)

0.014/0.022

(0.356/0.559)

0.045/0.070

(1.143/1.778)

0.008/0.014

(0.203/0.356)

0.880/0.920

(22.352/23.368)

0.300/0.325

(7.620/8.255)

0.240/0.280

(6.096/7.112)

0.115/0.150

(2.921/3.810)

0°/ 15°

(0°/15°)

20–PIN

0.115/0.195

(2.921/4.953)

0.014/0.022

(0.356/0.559)

0.045/0.070

(1.143/1.778)

0.008/0.014

(0.203/0.356)

0.980/1.060

(24.892/26.924)

0.300/0.325

(7.620/8.255)

0.240/0.280

(6.096/7.112)

0.115/0.150

(2.921/3.810)

0°/ 15°

(0°/15°)

22–PIN8–PIN 14–PIN 16–PIN

0.115/0.195

(2.921/4.953)

0.014/0.022

(0.356/0.559)

0.045/0.070

(1.143/1.778)

0.008/0.014

(0.203/0.356)

1.145/1.155

(29.083/29.337)

0.300/0.325

(7.620/8.255)

0.240/0.280

(6.096/7.112)

0.115/0.150

(2.921/3.810)

0°/ 15°

(0°/15°)

Page 8

DIMENSIONS (Inches)

Minimum/Maximum

(mm) A

8–PIN

0.053/0.069

(1.346/1.748)

0.004/0.010

(0.102/0.249

0.014/0.019 (0.35/0.49)

0.189/0.197 (4.80/5.00)

0.150/0.157

(3.802/3.988)

0.050 BSC

(1.270 BSC)

0.228/0.244

(5.801/6.198)

0.010/0.020

(0.254/0.498)

0.016/0.050

(0.406/1.270)

0°/8°

(0°/8°)

PACKAGE: PLASTIC

h x 45°

14–PIN

0.053/0.069

(1.346/1.748)

0.004/0.010

(0.102/0.249)

0.013/0.020

(0.330/0.508)

0.337/0.344

(8.552/8.748)

0.150/0.157

(3.802/3.988)

0.050 BSC

(1.270 BSC)

0.228/0.244

(5.801/6.198)

0.010/0.020

(0.254/0.498)

0.016/0.050

(0.406/1.270)

0°/8°

(0°/8°)

16–PIN

0.053/0.069

(1.346/1.748)

0.004/0.010

(0.102/0.249)

0.013/0.020

(0.330/0.508)

0.386/0.394

(9.802/10.000)

0.150/0.157

(3.802/3.988)

0.050 BSC

(1.270 BSC)

0.228/0.244

(5.801/6.198)

0.010/0.020

(0.254/0.498)

0.016/0.050

(0.406/1.270)

0°/8°

(0°/8°)

SMALL OUTLINE (SOIC) (NARROW)

Page 9

ORDERING INFORMATION

Model .................................................................................. Temperature Range .......................................................................................Package

Monolithic 12-Bit DAC Voltage Output:

SP9601JN ................................................................................ 0˚C to +70˚C........................................................................ 8-pin, 0.3" Plastic DIP

SP9601KN ............................................................................... 0˚C to +70˚C........................................................................ 8-pin, 0.3" Plastic DIP

SP9601JS ................................................................................0˚C to +70˚C ...............................................................................8–pin, 0.15" SOIC

SP9601KS ...............................................................................0°C to +70°C ................................................................................ 8–pin, 0.15" SOIC

SP9601AN ............................................................................... –40˚C to +85˚C ................................................................... 8-pin, 0.3" Plastic DIP

SP9601BN ............................................................................... –40˚C to +85˚C ................................................................... 8-pin, 0.3" Plastic DIP

SP9601AS ...............................................................................–40˚C to +85˚C .......................................................................... 8–pin, 0.15" SOIC

SP9601BS ...............................................................................–40°C to +85 °C ............................................................................8–pin, 0.15" SOIC

Corporation

SIGNAL PROCESSING EXCELLENCE

Sipex Corporation Headquarters and

Sales Office

22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com

Sales Office

233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.

Datasheet SP9601AN, SP9601AS, SP9601BN, SP9601BS, SP9601JN Datasheet (Sipex Corporation)

Specifications and Main Features

Frequently Asked Questions

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