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SP8401
Very Low Phase Noise 300MHz ÷10/11
Supersedes February 1992 edition DS3230 - 3.1 April 1994
The SP8401 is a very low phase noise variable modulus
divider. Special circuit techniques have been used to reduce
the phase noise considerably below that produced by standard
dividers. The modulus control input is CMOS or TTL
compatible.
The SP8401 is packaged in a 28 pin plastic SO package to
be compatible with the SP8400 and SP8402 devices.
FEATURES
■ Very low Phase Noise (Typically -160dBc/Hz at 1kHz
offset)
■ Supply Voltage 5V
ABSOLUTE MAXIMUM RATINGS
Supply Voltage 6.5V
Output Current 20mA
Storage Temperature Range -55°C to +125°C
Maximum Clock Input Voltage 2.5V p-p
N/C
N/C
N/C
V
+5V
CC
GND
INPUT
CLOCK
CLOCK INPUT
CLOCK INPUT
INPUT
CLOCK
GND
V
+5V
CC
V
+5V
CC
N/C
MODULUS CONTROL
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
28
N/C
27
N/C
26
N/C
25
N/C
24
N/C
23
N/C
22
N/C
21
OUTPUT
20
OUTPUT
19
N/C
18
V
+5V
17
16
CC
N/C
N/C
N/C
MP28
ORDERING INFORMATION
SP8401 KG MPES(Commercial Grade)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
(f) (dBc/Hz) –3dB
–110
–120
–130
–140
–150
–160
–170
1 10 100 1k 10k 100k
Fig.1 Pin connections - top view
Frequency (Hz)
Fig.2 Typical single sideband phase noise measured at 300MHz
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SP8400
ELECTRICAL CHARACTERISTICS
Guaranteed over: Supply voltage VCC = +4.75V to +5.25V Temperature T
Tested at +4.75V and +5.25V at T
= +25°C
amb
= -10°C to +75°C
amb
Characteristic
Supply current
Output voltage swing
Input sensitivity 50MHz to 300MHz
Modulus Control Inputs
Logic high voltage
Low low voltage
Input current
Set up time t
Release time t
s
r
400
300
RMS
mV
200
IN
V
100
Pin
4, 11, 12, 18
20, 21
7, 8
14
14
14
14
14
Value
Min. Typ. Max.
57
50
340
440
64
140
(-4)
2.2
0.8
180
4
4
OPERATING WINDOW
Units
mA
mV
mV
dBm
V
µA
ns
ns
Conditions
Output loaded with 300R See Fig.5
p-p @ 330MHz input ÷ 11 mode
Output loaded with 300R
RMS Sine wave into 50 Ohms
(dBm equivalent) See Fig.3
÷ 10 mode
÷ 11 mode
Modulus control input voltage 5V
355mV
140mV
0 50 100 150 200 250 300 350
INPUT FREQUENCY (MHz)
Fig.3 Typical input sensitivity
CLOCK INPUT
MODULUS
CONTROL
INPUT
OUTPUT
r
t
65
t
s
5
Fig.4 Timing diagram
2
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SP8400
V
CC
50R
GENERATOR
TTL/CMOS
MODULUS
CONTROL
RF
SIGNAL
1nF
1
2
3
4
5
6
7
SP8401 220nF
8
9
10
11
12
13
14 15
28
27
26
25
24
23
22
21
20
19
18
17
16
2x330R
10nF10nF1nF 1nF
OUTPUT
50R
Fig.4 Test circuit
3
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