Datasheet SP8121JP, SP8121JS, SP8121KP, SP8121KS Datasheet (Sipex Corporation)

Download

Page 1

SP8121

Monolithic, 12–Bit Data Acquisition System

■ Complete Monolithic 8-Channel, 12-Bit DAS

■ 100kHz Throughput

■ 16-Bit Microprocessor Bus Interface

■ Parallel 12-Bit Output

■ Latched MUX Address

■ Tri-State Latched Output

■ No Missing Codes to 12-Bits

■ 32-pin SOIC and PDIP Available

■ 200mW Power Dissipation Maximum

* Formerly part of the SP410 Series.

DESCRIPTION

The SP8121 is a complete data acquisition systems, featuring 8-channel multiplexer, internal reference and 12-bit sampling A/D converter implemented as a single monolithic IC. The analog multiplexer accepts 0V to +5V unipolar full scale inputs. Output data is formatted in 12-bit parallel. The SP8121 is available in 32-pin plastic DIP or SOIC packages, operating over the commercial temperature range.

MULTIPLEXER

MUX DECODE

REFERENCE

12-BIT A/D

CONVERTER

CONTROL

LOGIC

CLOCK

LATCH

TRI-STATE

Page 2

ABSOLUTE MAXIMUM RATINGS

VCC to Common Ground .............................................. 0V to +16.5V

to Common Ground ............................................... 0V to +7V

LOGIC

Analog Common to Digital Common Ground ...............-0.5V to +1V

Digital Inputs to Common Ground ....................-0.5V to V

Digital Outputs to Common Ground ................. -0.5V to V

Multiplexer Analog Inputs......................................-16.5V to +31.5V

Gain and Offset Adjustment ................................ -0.5V to VCC+0.5V

Analog Input Maximum Current ........................................... 100mA

Temperature with Bias Applied ............................. -55°C to +125°C

Storage Temperature ............................................ -65°C to +150°C

Lead Temperature, Soldering .................................... 300°C, 10sec

LOGIC LOGIC

+0.5V +0.5V

CAUTION:

ESD (ElectroStatic Discharge) sensitive

device. Permanent damage may occur on

unconnected devices subject to high energy

electrostatic fields. Unused devices must be

stored in conductive foam or shunts. Personnel should be properly grounded prior to handling this device. The protective foam should be discharged to the destination

socket before devices are removed.

SPECIFICATIONS

(TA= 25°C and nominal supply voltages unless otherwise noted)

MIN. TYP. MAX. UNIT CONDITIONS

ANALOG INPUTS

Input Voltage Range 0 to +5 V Multiplexer Inputs 8

Configuration Single-ended Input Impedance ON Channel 10 OFF Channel 10

Input Bias Current/Channel +10 nA 25°C Crosstalk

OFF to ON Channel -90 dB 10kHz, 0V to +5V

ACCURACY

Resolution 12 Bits Linearity Error

–K +0.5 LSB –J +1 LSB

Differential Non-Linearity

–K +1 LSB

–J +2 LSB Offset Error +0.5 +4 LSB Adjustable to zero Gain Error +0.3 +1 %FSR Adjustable to zero No Missing Codes

–K Guaranteed

TRANSFER CHARACTERISTICS

Throughput Rate 100 kHz MUX Settling/Acquisition 1.9 µs A/D Conversion 8.1 µs

STABILITY

Linearity +0.5 +2.5 ppm/°C Offset +5 +25 ppm/°C Gain +10 +50 ppm/°C

DIGITAL INPUTS

Capacitance 5 pF Logic Levels

+2.4 +5.5 V

-0.5 +0.8 V

Ω Parallel with 30pF Ω Parallel with 5pF

+250 nA -55°C to +125°C

-80 dB 50kHz, 0V to +5V

-70 dB 100kHz, 0V to +5V

+5 µA +5 µA

Pk-to-pk Pk-to-pk

Pk-to-pk

Page 3

SPECIFICATIONS (continued)

(TA= 25°C and nominal supply voltages unless otherwise noted)

MIN. TYP. MAX. UNIT CONDITIONS

DIGITAL OUTPUTS

Capacitance 5 pF Logic Levels

Leakage Current ±40 µA High impedance, data bits only

Data Output Positive true binary

POWER REQUIREMENTS

LOGIC

Power Dissipation 140 200 mW

ENVIRONMENTAL AND MECHANICAL

Operating Temperature

Commercial (–J, –K) 0 +70 °C Storage Temperature -65 +150 °C Packages

–_P 32–pin Plastic DIP

–_S 32–pin SOIC

+2.4 V IOH ≤ 500µA

+0.4 V IOL ≤ 1.6mA

+4.5 +5.5 V

0.8 4 mA

+11.4 +16.5 V

912 mA

Page 4

SP8121 PINOUT

DB11 (MSB)

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0 (LSB)

MA2

MA1

MA0

LATCH

1723 22 21 20 19 182430 29 28 27 26 2532 31

REF

R/C

12-BIT ADC

GAIN ADJ.

OFFSET ADJ.

ANA. GND.

ANA. IN. CH0

DECODE

8-CHANNEL

MULTIPLEXER

ANA. IN. CH1

ANA. IN. CH2

ANA. IN. CH3

ANA. IN. CH4

ANA. IN. CH5

ANA. IN. CH6

ANA. IN. CH7

CLOCK

CONTROL

LOGIC

11623456789101112131415

LOGIC

STATUS

SP8121 PINOUT

STATUS — Identifies valid data output; goes to logic high during conversion; goes to logic low when conversion is completed and data is valid

R/C — Read/Convert — Initiates conversion on the high-to-low transition; logic low disconnects data bus; logic high initiates read

SP8121 CONTROL TRUTH TABLE

CE R/C OPERATION

L->H 0 Start Conversion

1 0 Start Conversion 1 H ->L Start Conversion 1 1 Enable 12-bit Output

(when STATUS=0)

SP8121 MULTIPLEXER TRUTH TABLE

LATCH MA2MA1MA0OPERATION

H -> L 0 0 0 CHO Selected H -> L 0 0 1 CH1 Selected H -> L 0 1 0 CH2 Selected H -> L 0 1 1 CH3 Selected H -> L 1 0 0 CH4 Selected H -> L 1 0 1 CH5 Selected H -> L 1 1 0 CH6 Selected H -> L 1 1 1 CH7 Selected

0 X X X Prev. CH “n” Held 1 X X X Prev. CH “n” Held

CE — Chip Enable — Logic low disables read or convert; logic high enables read or convert

LATCH — MUX Address Latch — Logic high to low transition captures MUX address on MUX address lines

MA0, MA1, MA2 — MUX Address 0, 1 & 2 — Selects analog input channels CH0 through CH

DB0 through DB11 — Data Outputs — Logic high is binary true; logic low binary false

Page 5

FEATURES

Linearity errors of +0.5 and +1.0 LSB, and Differential Non-linearity to 12-bits is guaranteed, with no missing codes over temperature. Channel-to-channel crosstalk is typically -85dB. Multiplexer settling plus acquisition time is 1.9µs maximum; A/D conversion time is 8.1µs maximum.

The SP8121 is available in a 32-pin plastic DIP or SOIC packages. Operating temperature range is 0°C to +70°C commercial.

CIRCUIT OPERATION

The SP8121 is a complete 8-channel data acquisition systems (DAS), with on-board multiplexer, voltage reference, sample-and-hold, clock and tri-state outputs. The digital control architecture is very similar to the industry-standard 574-type A/D, and uses identical control lines and digital states.

The multiplexer for the SP8121 is identical in operation to many discrete devices available today, except that it has been integrated into the single-chip DAS. The appropriate channel is selected using the MUX address lines MA0, MA1, and MA2 per the truth table. The selected analog input is fed through to the ADC. The input impedance into any MUX channel will be on the order to 109 ohms, since it is connected to the integral sampling structure of the capacitor DAC. Crosstalk is kept to -85dB at 0V to 5V

over an

p-p

input frequency range of 10kHz to 50kHz. When the control section of the SP8121 initiates a

conversion command the internal clock is enabled, and the successive approximation register (SAR) is reset to all zeros. Once the conversion has been started it cannot be stopped or restarted. Data is not available at the output buffers until the conversion has been completed.

The SAR, timed by the clock, sequences through the conversion cycle and returns an end–of–convert flag to the control section of the ADC. The clock is then disabled by the control section, which puts the STATUS output line low. The control section is enabled to allow the data to be read by external command (R/C).

MULTIPLEXER CONTROL

On the SP8121 the address lines MA0, MA1, and MA2 are latched into the internal address decode circuitry with the falling edge of LATCH. Data set-up time for these inputs is >=50nS. The MUX address data must remain valid for the current conversion for a minimum of 3.0 µS after the conversion is initiated. This is the time required for the MUX and Sample and Hold to settle. However it is advisable that the MUX not be changed at all during the full 10µS conversion time due to capacitive coupling effects of digital edges through the silicon.

The SP8121 multiplexer inputs have been designed to allow substantial overvoltage conditions to occur without any damage. The inputs are diode-clamped and further protected with a 200Ω series resistor. As a result, momentary (10 seconds) input voltages can be as low as -16.5V or as high as +31.5V with no change or degradation in multiplexer performance or crosstalk. This feature allows the output voltage of an externally connected op amp to swing to +15V supply levels with no multiplexer damage. Complicated power-up sequencing is not required to protect the SP8121. The multiplexer inputs may be damaged, however, if the inputs are allowed to either source or sink greater than 100mA.

INITIATING A CONVERSION

The SP8121 was designed to require a minimum of control to perform a 12-bit conversion. The control input used are R/C which tri-states the outputs when high and starts the conversion when low, in combination with CE. The last of the control inputs to reach the correct state starts the conversion, therefore either may be dynamically controlled. The nominal delay from each is the same and they may change state simultaneously. In order to ensure that a particular input controls the conversion, the other should be set up at least 50ns earlier. The STATUS line indicates when a conversion is in process and when it is complete.

Page 6

+15V

100K

SP8121

OFFSET ADJUST

Figure 1. Offset Adjust

–1.5mV to +3mV

The conversion cycle is started when R/C is brought low and must be held low for a minimum of 50ns. The R/C signal will also put the output latches in a tri-state mode when low. Approximately 200ns after R/C is low, STATUS will change from low to high. This output signal will stay high while the SP8121 is performing a conversion. Valid data will be latched to the output bus, through internal control, 500ns prior to the STATUS line transitioning from a high to low.

READING THE DATA

Please refer to Figure 4. To read data from the SP8121, the R/C and CE control lines are used. R/C must be high a minimum of 50ns prior to reading the data to allow time for the output latches to come out of the high impedance tri-state mode. CE is used to access the data. The first 8 MSBs will be on pins 32 through 25, with pin 32 being the MSB. The remaining 4 LSBs will be on pins 21 through 24 with pin 21 being the LSB. When CE is switched from one state to the next, there is a 50ns output latch propagation delay between the MSBs and LSBs being present on the output pins.

SP8121

GAIN ADJUST

Figure 2. Gain Adjust

±0.3% Trim Range

125K

10K

19K

Center pot for zero correction

Gain Adjustment

With the offset adjusted, the gain error can now be trimmed to zero. (Please refer to Figure 2.) The ideal input voltage corresponding to 1.5 LSB’s below the nominal full scale input value, or +4.988V, is applied to any multiplexer input. The gain potentiometer is adjusted so that the output code alternates evenly between 111…111 and 111…110. Again, only the lower eight LSB’s need be observed during this procedure. With the above adjustment made, the converter is now calibrated.

CALIBRATION

The calibration procedure for the SP8121 consists of adjusting the most negative input voltage (0V) to the ideal output code for offset adjustment, and then adjusting the most positive input voltage (5.0V) to its ideal output code for gain adjustment.

Offset Adjustment

The offset adjustment must be completed first. Please refer to Figure 1. Apply an input voltage of 0.5LSB or 610µV to any multiplexer input. Adjust the offset potentiometer so that the output code fluctuates evenly between 000…000 and 000…001. It is only necessary to observe the lower eight LSB’s during this procedure.

Page 7

SRC

HEC

R/C

STATUS

- DB

HRC

DSC

HIGH IMPEDANCE

CONVERT MODE DYNAMIC CHARACTERISTICS

VCC = +15V; V

= +5V; TA = 25°C

LOGIC

PARAMETER MIN. TYP. MAX. UNIT CONDITIONS

CE Pulse Width 50 ns

HEC

R/C to CE Setup 50 ns

SRC

R/C Low during CE High 50 ns

HRC

Status Delay from CE 200 ns

DSC

Figure 3. Convert Mode Timing

SRR

HRR

R/C

STATUS

- DB

HIGH IMPEDANCE

DATA VALID

READ MODE DYNAMIC CHARACTERISTICS

VCC = +15V; V

= +5V; TA = 25°C

LOGIC

PARAMETER MIN. TYP. MAX. UNIT CONDITIONS

R/C to CE Setup 0 0 ns

SRR

R/C High after CE Low 0 50 ns

HRR

tHDData Valid after CE Low 25 ns tDDAccess Time from CE 150 ns tHLOutput Float Delay 150 ns

Figure 4. Read Mode Timing

Page 8

R/C

HRH

STATUS

- DB

DDR

HIGH–Z HIGH–Z

HDR

DATA VALID

HIGH PULSE FOR R/C DYNAMIC CHARACTERISTICS

VCC = +15V; V

= +5V; TA = 25°C

LOGIC

PARAMETER MIN. TYP. MAX. UNIT CONDITIONS

High R/C Pulse Width 25 ns

HRH

tDSSTATUS Delay from R/C 200 ns tCConversion Time 13 25 µsT t

Data Access Time 150 ns

DDR

Data Valid after R/C Low 25 ns

HDR

MIN

to T

Figure 5. High Pulse for R/C — Outputs Enabled While R/C is High, Otherwise High Impedance

MDH

MA0 - MA

MDS

HRL

R/C

MAX

STATUS

- DB

HDR

DATA VALID DATA VALID

LOW PULSE FOR R/C DYNAMIC CHARACTERISTICS

VCC = +15V; V

= +5V; TA = 25°C

LOGIC

PARAMETER MIN. TYP. MAX. UNIT CONDITIONS

Low R/C Pulse Width 50 ns

HRL

tDSStatus Delay from R/C 200 ns t

Data Valid after R/C 25 ns

HDR

tHSStatus Delay after Data Valid 500 ns t

MUX Data Setup 50 ns

MDS

MUX Data Valid 3 10 µs

MDH

Figure 6. Low Pulse for R/C

Page 9

Figure 7. FFT; 6kHz, 5V (0dB) Full Scale Input; FS = 100kHz

Figure 8. FFT; 12kHz, 5V (0dB) Full Scale Input; FS = 100kHz

Figure 9. FFT; 24kHz, 5V (0dB) Full Scale Input; FS = 100kHz

Figure 10. FFT; 48kHz, 5V (0dB) Full Scale Input; FS = 100kHz

Figure 11. FFT; 48kHz, 1V (–14dB) Input; FS = 100kHz

Page 10

+1 LSB

INLE

-1. LSB

+1. LSB

DNLE

Figure 12. Non-Linearity

0 2048 4095

-1. LSB

Page 11

D1 = 0.005" min.

(0.127 min.)

e = 0.100 BSC

(2.540 BSC)

DIMENSIONS (Inches)

Minimum/Maximum

(mm) A2

32–PIN

0.125/0.195

(3.175/4.953)

0.014/0.022

(0.366/0.559

0.030/0.070

(0.762/1.778)

0.008/0.015

(0.203/0.381)

1.645/1.655

(41.78/42.04)

0.600/0.625

(15.24/15.87)

0.485/0.580

(12.31/14.73)

0.115/0.200

(2.921/5.080)

0°/ 15°

(0°/15°)

PACKAGE: PLASTIC

DUAL–IN–LINE (WIDE)

A1 = 0.015" min.

(0.381min.)

A = 0.25" max.

(6.350 max).

eA = 0.600 BSC

(15.240 BSC)

Page 12

DIMENSIONS (Inches)

Minimum/Maximum

(mm)

32–PIN

0.090/0.104 (2.29/2.649)

0.004/0.012

(0.102/0.300)

0.013/0.020

(0.330/0.508)

0.810/0.822

(20.57/20.88)

0.291/0.299

(7.402/7.600)

0.050 BSC

(1.270 BSC)

0.394/0.419

(10.00/10.64)

0.016/0.050

(0.406/1.270)

0°/8°

(0°/8°)

PACKAGE: PLASTIC

SMALL OUTLINE (SOIC)

Page 13

ORDERING INFORMATION

12-Bit Data Acquisition System with 12-Bit Parallel Data Output and latched MUX Address Inputs:

Commercial Temperature Range (0°C to +70°C) .................................... Linearity ................................................................................ Package

SP8121JP ............................................................................................... +1.0LSB INL ...................................................... 32–pin, 0.6" Plastic DIP

SP8121KP .............................................................................................. +0.5LSB INL ...................................................... 32–pin, 0.6" Plastic DIP

SP8121JS ............................................................................................... +1.0LSB INL ................................................................ 32–pin, 0.3" SOIC

SP8121KS .............................................................................................. +0.5LSB INL ................................................................32–pin, 0.3" SOIC

Please consult the factory for pricing and availability on a Tape-On-Reel option.

Corporation

SIGNAL PROCESSING EXCELLENCE

Sipex Corporation Headquarters and

Sales Office

22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com

Sales Office

233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.

Datasheet SP8121JP, SP8121JS, SP8121KP, SP8121KS Datasheet (Sipex Corporation)

Specifications and Main Features

Frequently Asked Questions

User Manual