Datasheet SP320ACF Datasheet (Sipex Corporation)

®

SP320

Complete +5V-Only V.35 Interface

with RS-232 (V.28) Control Lines

■ 10Mbps Data Throughput

■ +5V-Only, Single Supply Operation

■ 3 Drivers, 3 Receivers – V.35

■ 4 Drivers, 4 Receivers – RS-232

■ 80-pin QFP Surface Mount Packaging

■ Pin Compatible with SP319

DESCRIPTION

The SP320 is a complete V.35 interface transceiver offering 3 drivers and 3 receivers of V.35, and 4 drivers and 4 receivers of RS-232 (V.28). A Sipex patented charge pump allows +5V only low power operation. RS-232 drivers and receivers are specified to operate at 120kbps, all V.35 drivers and receivers operate up to 5Mbps.

+5V

+

0.1µF

+

0.1µF

+5V

RCA1 70 RCOUT 1

RCB1 71 RCA2 37

RCOUT2 20

RCB2 38

R1IN 66

R1OUT 80

R2IN 68

R2OUT 78

R3IN 35

R3OUT 19

R4IN 39

R4OUT 21

RCA3 76

RCOUT3 79

RTEN 7

RCB3 77

26

30 28

31

3 TS000 9 ENV35

C1+

C1C2+

C2-

25, 33, 41, 62, 73

VCC

SP320

400kΩ

100Ω

400kΩ

100Ω

400kΩ

5kΩ

400kΩ

5kΩ

400kΩ

5kΩ

400kΩ

5kΩ

400kΩ

100Ω

VDD

VSS

Vcc

29, 34, 43, 60, 64, 72

27

32

+

0.1µF +

14 DRIN1 61 DRA1

59 DRB1 13 T1IN

58 T1OUT 16 T2IN

54 T2OUT 17 T3IN 47 T3OUT

24 T4IN 51 T4OUT

22 DRIN2 42 DRA2 44 DRB2

23 STEN

15 DRIN3

63 DRA3 65 DRB3

6 TTEN

0.1µF

1

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

VCC.....................................................................................................+7V

Input Voltages

Output Voltages

Storage Temperature.......................................................-65˚C to +150˚C

Power Dissipation..........................................................................1500mW

Package Derating

Logic........................................................-0.3V to (VCC+0.5V)

Drivers..................................................-0.3V to (VCC+0.5V)

Receivers..................................................±30V at ≤100mA

Logic........................................................-0.3V to (VCC+0.5V)

Drivers.......................................................................±14V

Receivers..............................................-0.3V to (VCC+0.5V)

ØJC.......................................................................16 •C/W

ØJA.......................................................................46 •C/W

SPECIFICATIONS

T

to T

and VCC = 5V±5% unless otherwise noted.

MIN

MAX

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS

V.35 DRIVER

TTL Input Levels V

IL

V

IH

2.0 Volts

Voltage Outputs Differential Outputs ±0.44 ±0.55 ±0.66 Volts RL=100Ω from A to B Source Impedance 50 100 150 Ohms Short Circuit Impedance 135 150 165 Ohms Measured from A=B to Gnd,

Voltage Output Offset -0.6 +0.6 Volts V AC Characteristics

Transition Time 40 ns Rise/fall time, 10% to 90%

Maximum Transmission Rate

5 Mbps RL=100Ω, V Propagation Delay t

t

PHL

PLH

150 250 ns Measured from 1.5V of V 150 250 ns Measured from 1.5V of V

V.35 RECEIVER

TTL Output Levels V

OL

V

OH

Receiver Inputs

2.4 Volts I

Differential Input Threshold -0.3 +0.3 Volts Input Impedance 90 100 110 Ohms Short Circuit Impedance 135 150 165 Ohms Measured from A=B to Gnd

0.8 Volts

0.4 Volts I

V

=-2V to +2V

OUT

={[|VA|+|VB|]/2}

Offset

DIFF OUT

to 50% of V to 50% of V

OUT OUT

OUT

=-3.2mA =1.0mA

VIN=-2V to +2V

= 0.55V±20%

IN

AC Characteristics

Maximum Transmission Rate

5 Mbps VIN = ±0.55V ±20% Propagation Delay t

PHL

t

PLH

150 250 ns Measured from 50% of VIN to 150 250 ns Measured from 50% of VIN to

1.5V of R

OUT

2

SPECIFICATIONS (CONTINUED)

T

to T

and VCC = 5V±5% unless otherwise noted.

MIN

MAX

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS RS-232 DRIVER

TTL Input Levels V

IL

V

IH

2.0 Volts

Voltage Outputs High Level Output +5.0 +15.0 Volts RL= 3kΩ to Gnd Low Level Output -15.0 -5.0 Volts RL= 3kΩ to Gnd Open Circuit Output -15 +15 Volts RL= ∞ Short Circuit Current -100 +100 mA RL= Gnd Power Off Impedance 300 Ohms VCC= 0V; V

AC Characteristics Slew Rate 30 V/µs

Maximum Transmission Rate

120 kbps RL= 3kΩ, CL= 2500pF

0.8 Volts

RL= 3kΩ, CL= 50pF; From +3V to -3V or -3V to +3V, TA = 25˚C, VCC = +5V

OUT

= ±2V

Transition Time 1.56 µs Rise/fall time, between ±3V

RL= 3kΩ, CL= 2500pF Propagation Delay t

t

PHL

PLH

28µsR 28µsR

= 3kΩ, CL= 2500pF; From 1.5V

L

of T

to 50% of V

IN

= 3kΩ, CL= 2500pF; From 1.5V

L

of T

to 50% of V

IN

OUT

RS-232 RECEIVER

TTL Output Levels V V

OL OH

2.4 Volts

0.4 Volts

Receiver Input Input Voltage Range -15 +15 Volts High Threshold 1.7 3.0 Volts Low Threshold 0.8 1.2 Volts

Hysteresis 0.2 0.5 1 Volts VCC= 5V; TA= +25˚C

Receiver Input Circuit Bias +2.0 Volts

Input Impedance 3 5 7 kOhms VIN= ±15V

AC Characteristics

Maximum Transmission Rate

120 kbps Propagation Delay t t

PHL PLH

0.1 1 µs From 50% of R

to 1.5V of R

IN

to 1.5V of R

IN

OUT OUT

POWER REQUIREMENTS

No Load VCC Supply Current 35 70 mA No load; VCC= 5.0V; TA= 25˚C Full Load VCC Supply Current 60 mA RS-232 drivers RL= 3kΩ to Gnd;

DC Input V.35 drivers RL= 100Ω from A to B; DC Input

Shutdown Current 1.5 mA TS000 = ENV35 = 0V

3

THEORY OF OPERATION

The SP320 is a single chip +5V-only serial transceiver that supports all the signals necessary to implement a full V.35 interface. Three V.35 drivers and three V.35 receivers make up the clock and data signals. Four RS-232 (V.28) drivers and four RS-232 (V.28) receivers are used for control line signals for the interface.

V.35 Drivers

The V.35 drivers are +5V-only, low power voltage output transmitters. The drivers do not require any external resistor networks, and will meet the following requirements:

1. Source impedance in the range of 50Ω to 150Ω.

2. Resistance between short-circuited terminals and ground is 150Ω ±15Ω.

3. When terminated with a 100Ω resistive load the terminal to terminal voltage will be 0.55 Volts ±20% so that the A terminal is positive to the B terminal when binary 0 is transmitted, and the conditions are reversed to transmit binary 1.

4. The arithmetic mean of the voltage of the A terminal with respect to ground, and the B terminal with respect to ground will not exceed

0.6 Volts when terminated as in 3 above. The V.35 drivers can operate at data rates as

high as 5Mbps. The driver outputs are protected against short-circuits between the A and B outputs and short circuits to ground.

Two of the V.35 drivers, DRIN2 and DRIN3 are equipped with enable control lines. When the enable pins are high the driver outputs are disabled, the output impedance of a disabled driver will nominally be 300Ω. When the enable pins are low, the drivers are active.

V.35 Receivers

The V.35 receivers are +5V only, low power differential receivers which meet the following requirements:

1. Input impedance in the range of 100Ω ±10Ω.

2. Resistance to ground of 150Ω ±15Ω, measured from short-circuited terminals.

All of the V.35 receivers can operate at data rates as high as 5Mbps. The sensitivity of the V.35 receiver inputs is ±300mV.

RS-232 (V.28) Drivers

The RS-232 drivers are inverting transmitters, which accept either TTL or CMOS inputs and output the RS-232 signals with an inverted sense relative to the input logic levels. Typically, the RS-232 output voltage swing is ±9V with no load, and ±5V minimum with full load. The transmitter outputs are protected against infinite short-circuits to ground without degradation in reliability.

In the power off state, the output impedance of the RS-232 drivers will be greater than 300Ω over a ±2V range. Should the input of a driver be left open, an internal 400kΩ pullup resistor to VCC forces the input high, thus committing the output to a low state. The slew rate of the transmitter output is internally limited to a maximum of 30V/µs in order to meet the EIA standards. The RS-232 drivers are rated for 120kbps data rates.

RS-232 (V.28) Receivers

The RS-232 receivers convert RS-232 input signals to inverted TTL signals. Each of the four receivers features 500mV of hysteresis margin to minimize the effects of noisy transmission lines. The inputs also have a 5kΩ resistor to ground; in an open circuit situation the input of the receiver will be forced low, committing the output to a logic high state. The input resistance will maintain 3kΩ-7kΩ over a ±15V range. The maximum operating voltage range for the receiver is ±30V, under these conditions the input current to the receiver must be limited to less than 100mA. The RS-232 receivers can operate to beyond 120kbps.

CHARGE PUMP

The charge pump is a Sipex patented design (U.S. 5,306,954) and uses a unique approach compared to older less-efficient designs. The charge pump still requires four external capacitors, but uses a four-phase voltage shifting technique to attain symmetrical ±10V power supplies. The capacitors can be as low as 0.1µF with a 16 Volt rating. Polarized or non-polarized capacitors can be used.

4

+10V

+

a) C

2

GND GND

–

b) C

2

–10V

Figure 1. Charge Pump Waveforms

Figure 1a shows the waveform found on the positive side of capacitor C2, and Figure 1b shows the negative side of capacitor C2. There is a free-running oscillator that controls the four phases of the voltage shifting. A description of each phase follows.

Phase 1

-Vss charge storage- During this phase of the clock cycle, the positive side of capactors C1 and C2 are initially charged to +5V. C1+ is then switched to ground and the charge in C1- is transferred to C2-. Since C2+ is connected to +5V, the voltage potential across capacitor C2 is now 10V.

Phase 2

-Vss transfer- Phase two of the clock connects the negative terminal of C2 to the Vss storage capacitor and the positive terminal of C2 to ground, and transfers the generated -10V to C3. Simultaneously, the positive side of capacitor C1 is switched to +5V and the negative side is connected to ground.

Phase 3

-Vdd charge storage- The third phase of the clock is identical to the first phase- the transferred charge in C1 produces -5V in the negative terminal of C1, which is applied to the negative side of capacitor C2. Since C2+ is at +5V, the voltage potential across C2 is +10V.

Phase 4

-Vdd transfer- The fourth phase of the clock connects the negative terminal of C2 to ground and transfers the generated +10V across C2 to C4, the Vdd storage capacitor. Again, simultaneously with this, the positive side of capacitor C1 is switched to +5V and the negative side is connected to ground, and the cycle begins again.

Since both V+ and V- are separately generated from Vcc in a no load condition, V+and V- will be symmetrical. Older charge pump approaches that generate V- from V+ will show a decrease in the magnitude of V- compared to V+ due to the inherent inefficiencies in the design.

The clock rate for the charge pump typically operates at 15kHz. The external capacitors must be 0.1µF with a 16V breakdown rating.

Shutdown Mode

The SP320 can be put into a low power shutdown mode by bringing both TS000 (pin 3) and ENV35 (pin 9) low. In shutdown mode, the SP320 will draw less than 2mA of supply current. For normal operation, both pins should be connected to +5V.

External Power Supplies

For applications that do not require +5V only, external supplies can be applied at the V+ and V- pins. The value of the external supply voltages must be no greater than ±10V. The current drain from the ±10V supplies is used for the RS-232 drivers. For the RS-232 driver the current requirement will be 3.5mA per driver. It is critical the external power supplies provide a power supply sequence of : +10V, +5V, and then -10V.

Applications Information

The SP320 is a single chip device that can implement a complete V.35 interface. Three (3) V.35 drivers and three (3) V.35 receivers are used for clock and data signals and four (4) RS-232 (V.28) drivers and four (4) RS-232 (V.28) receivers can be used for the control signals of the interface. The following examples show the SP320 configured in either a DTE or DCE application.

5

VCC = +5V

V

= +5V

CC

++

C

1

C

2

––

Figure 2. Charge Pump Phase 1

+10V

VCC = +5V

++

C

1

C

2

––

–10V

Figure 4. Charge Pump Phase 3

V

CC1

5V

1µF1µF

C

4

+

–

Storage Capacitor

V

DD

+

–

V

Storage Capacitor

SS

C

3

++

C

1

–5V –5V

Figure 3. Charge Pump Phase 2

V

= +5V

CC

C

4

+

–

Storage Capacitor

V

DD

+

–

V

Storage Capacitor

SS

C

3

++

C

1

–5V

Figure 5. Charge Pump Phase 4

1µF

V.35 V.35

DX

RX

T

50Ω

=

T

50Ω

TXD (103)

P

S

SCTE (113)

U

W

TXC (114)

AA

Y

RXC (115)

X

V TRTXD (104)

125Ω

1µF

P

T

S U

T

W AA

T

Y X

T

V T

T

R

+5V

C

2

––

+5V

C

2

––

–5V

1µF

RX

DX

C

4

+

–

Storage Capacitor

V

DD

+

–

V

Storage Capacitor

SS

C

3

C

4

+

–

Storage Capacitor

V

DD

+

–

V

Storage Capacitor

SS

C

3

V

CC2

5V

GND (102)

DTR (108)

RTS (105)

DSR (107)

CTS (106)

DCD (109)

TM (142)

RDL (140)

LLB (141)

B

A

H

C

E

D

F

NN

N

L

ISO 2593

34-PIN DTE/DCE

INTERFACE

CONNECTOR

V

CC2

1µF

1µF1µF

RX

DX

RX

B

V

CC1

1µF

1µF1µF

RS-232 RS-232

DX

RX

DX

OPTIONAL SIGNALS

CABLE SHIELD

A

H

C

E

D

F

NN

N

L

ISO 2593

34-PIN DTE/DCE

INTERFACE

CONNECTOR

Figure 6. A Competitor’s Typical V.35 Solution Using Six Components.

6

RC

DR

R2

R1

R3

R4

14

IN

15

IN

22

OUT

79

OUT

20

OUT

1

T2

16

T1

13

T3

17

T4

24

OUT

78

OUT

80

OUT

19

OUT

21

0.1µF

28 31

C2+

IN

1

3

2

3

2

1

IN

+5V

0.1µF

25 272630

V

C2-

CC

SP320CF

1N5819

V

C1+

DD

0.1µF

C1V

+5V

1N5819

25 27

V

CC

V

DD

0.1µF

26 30

C1+

0.1µF

C1-

32

V

SS

RC

OUT

1

14

RC

OUT

2

20

0.1µF

31

0.1µF

32

SS

P

TxD (103)

S

U

TxC (113)

W

P S

U

W

28

C2+

C2-

SP320CF

AA

RC

OUT

3

79

DR 22

DR 15

14

R2 78

R1 80

DR

R4

R3

IN

2

IN

3

IN

1

OUT

21

OUT

19

IN

T2

16

IN

T1

13

IN

T3

17

IN

T4

24

Y

AA

X V

T R

H

C

N

L

E

D

F

NN

B

TxCC (114)

RxC (115)

RxD (104)

DTR (108)

RTS (105)

RL (140)

LL (141)

DSR (107)

CTS (106)

DCD (109)

TM (142)

Y

AA

X V

T R

H

C

N

L

E

D

F

NN

B

29, 34, 43, 60, 64, 72 29, 34, 43, 60, 64, 72

ISO2593

34-PIN DTE/DCE

INTERFACE CONNECTOR

ISO2593

34-PIN DTE/DCE

INTERFACE CONNECTOR

Figure 7. Typical DTE-DCE V.35 Connection with the SP320

7

ISO-2593 connector pin out

Signal Ground B Clear to Send D Data Carrier Detect F Ring Indicator J Local Loopback L Remote Loopback N Receive Data (A) R Receive Data (B) T Receive Timing (A) V Receive Timing (B) X Unassigned--- Z Unassigned--- BB Unassigned--- DD Unassigned--- FF Unassigned--- JJ Unassigned--- LL Test Mode NN

Typical DCE V.35 interface

0.1µF

+5V

103(A)

TXD

103(B) 113(A)

TXC

113(B)

105

RTS

108

DTR

140

RLPBK

141

LLPBK

SPARE

RCOUT2 20

R1OUT 80

R2OUT 78

R3OUT 19

R4OUT 21

RCOUT3 79

+

RCA1 70

RCOUT 1

RCB1 71 RCA2 37

RCB2 38

R1IN 66

R2IN 68

R3IN 35

R4IN 39

RCA3 76

RTEN 7

RCB3 77

26

C1+

30

C1-

28

C2+

31

C2-

3 TS000

ENV35

9

+5V

25, 33, 41, 62, 73

VCC

SP320

400KΩ

100Ω

400kΩ

100Ω

400kΩ

5kΩ

400kΩ

5kΩ

400kΩ

5kΩ

400kΩ

5kΩ

400kΩ

100Ω

A Chasis Ground C Request to Send E DCE Ready (DSR) H DTE Ready (DTR) K Unassigned--M Unassigned--P Transmitted Data (A) S Transmitted Data (B) U Terminal Timing (A) } 113(A) W Terminal Timing (B) } 113(B) Y Transmit Timing (A) } 114(A) AA Transmit Timing (B) } 114(B) CC Unassigned--EE Unassigned--HH Unassigned--KK Unassigned--MM Unassigned---

VDD

VSS

Vcc

29, 34, 43, 60, 64, 72

27

32

+

0.1µF

+

14 DRIN1 61 DRA1

59 DRB1 13 T1IN

58 T1OUT 16 T2IN

54 T2OUT

17 T3IN 47 T3OUT

24 T4IN 51 T4OUT

22 DRIN2

42 DRA2 44 DRB2

23 STEN

15 DRIN3 63 DRA3

65 DRB3

6 TTEN

0.1µF

RXD

CTS

DSR

DCD

RI

TXCC

RXC

104(A) 104(B)

106

107

109

125

114(A)

114(B)

115(A) 115(B)

8

ISO-2593 connector pin out

Signal Ground B Clear to Send D Data Carrier Detect F Ring Indicator J Local Loopback L Remote Loopback N Receive Data (A) R Receive Data (B) T Receive Timing (A) V Receive Timing (B) X Unassigned--- Z Unassigned--- BB Unassigned--- DD Unassigned--- FF Unassigned--- JJ Unassigned--- LL Test Mode NN

Typical DTE V.35 interface

0.1µF

+5V

104(A)

RXD

104(B) 114(A)

TXCC

114(B)

106

CTS

107

DSR

109

DCD

125

RI

115(A)

RXC

115(B)

RCOUT2 20

R1OUT 80

R2OUT 78

R3OUT 19

R4OUT 21

RCOUT3 79

+

RCA1 70

RCOUT 1

RCB1 71 RCA2 37

RCB2 38

R1IN 66

R2IN 68

R3IN 35

R4IN 39

RCA3 76

RTEN 7

RCB3 77

26

C1+

30

C1-

28

C2+

31

C2-

3 TS000

ENV35

9

+5V

25, 33, 41, 62, 73

VCC

SP320

400kΩ

100Ω

400kΩ

100Ω

400kΩ

5kΩ

400kΩ

5kΩ

400kΩ

5kΩ

400kΩ

5kΩ

400kΩ

100Ω

29, 34, 43, 60, 64, 72

A Chasis Ground C Request to Send E DCE Ready (DSR) H DTE Ready (DTR) K Unassigned--M Unassigned--P Transmitted Data (A) S Transmitted Data (B) U Terminal Timing (A) } 113(A) W Terminal Timing (B) } 113(B) Y Transmit Timing (A) } 114(A) AA Transmit Timing (B) } 114(B) CC Unassigned--EE Unassigned--HH Unassigned--KK Unassigned--MM Unassigned---

0.1µF

+

27

VDD

32

VSS

Vcc

0.1µF

+

14 DRIN1 61 DRA1

59 DRB1 13 T1IN

58 T1OUT 16 T2IN

54 T2OUT

17 T3IN 47 T3OUT

24 T4IN 51 T4OUT

22 DRIN2

42 DRA2 44 DRB2

23 STEN

15 DRIN3 63 DRA3

65 DRB3

6 TTEN

TXD

103(A) 103(B)

RTS

105

DTR

108

RLPBK

140

LLPBK

141

TXCT

113(A)

113(B)

SPARE

SPARE SPARE

9

4 5

8

Pin configuration

80 R1OUT

79 RCOUT3

78 R2OUT

75 NC

77 RCB3

76 RCA3

74 NC

73 VCC

72 GND

71 RCB1

69 NC

68 R2IN

70 RCA1

67 NC

66 R1IN

64 GND

65 DRB3

63 DRA3

62 VCC

61 DRA1

Typical application circuit

RCOUT1 1

NC 2

TS000 3

NC

NC TTEN 6 RTEN 7

NC

ENV35 9

NC 10 NC 11 NC 12

T1IN 13

DRIN1 14 DRIN3 15

T2IN 16 T3IN 17

NC 18

R3OUT 19

RCOUT2 20

+

0.1µF

+

0.1µF

+5V

RCA1 70 RCOUT 1

RCB1 71 RCA2 37

RCOUT2 20

RCB2 38

R1IN 66

R1OUT 80

R2IN 68

R2OUT 78

R3IN 35

R3OUT 19

R4IN 39

R4OUT 21

RCA3 76

RCOUT3 79

RTEN 7

RCB3 77

STEN 23

DRIN2 22

ROUT4 21

26

C1+

30

C1-

28

C2+

31

C2-

3 TS000 9 ENV35

SP320

C1- 30

C2+ 28

VDD 27

GND 29

+5V

25, 33, 41, 62, 73

VCC

Vcc

400kΩ

Vcc

400kΩ

Vcc

400kΩ

Vcc

400kΩ

Vcc

400kΩ

Vcc

400kΩ

Vcc

400kΩ

29, 34, 43, 60, 64, 72

C2- 31

T4IN 24

VCC 25

C1+ 26

SP320

100Ω

5kΩ

100Ω

VSS 32

VCC 33

VDD

VSS

R3IN 35

GND 34

27

32

14 DRIN1 61 DRA1

59 DRB1 13 T1IN

58 T1OUT 16 T2IN

54 T2OUT

17 T3IN 47 T3OUT

24 T4IN 51 T4OUT

22 DRIN2 42 DRA2 44 DRB2

23 STEN

15 DRIN3

63 DRA3

65 DRB3

6 TTEN

NC 36

RCA2 37

+

0.1µF +

NC 40

R4IN 39

RCB2 38

0.1µF

60 GND 59 DRB1 58 T1OUT 57 NC 56 NC 55 NC 54 T2OUT 53 NC 52 NC 51 T4OUT 50 NC 49 NC 48 NC 47 T3OUT 46 NC 45 NC 44 DRB2 43 GND 42 DRA2 41 VCC

10

PIN 1

PACKAGE: QUAD FLATPACK

JEDEC "BE-2" OUTLINE

D D1

0.3" RAD. TYP.

0.2" RAD. TYP.

C

L

0.009"/0.015" (0.220/0.380)

C

L

0.02559"/– (0.65/–)

DIMENSIONS in Inches

A1

Minimum/Maximum

(mm)

A

A1

D

D1

E

E1

L

E1

E

0°–7°

AA

Seating

Plane

JEDEC BE-2 Outline

80–PIN

–/0.0925 (–/2.350)

–/0.010

(–/0.250)

0.667/0.687

(16.950/17.450)

0.547/0.555

(13.900/14.100)

0.667/0.687

(16.950/17.450)

0.547/0.555

(13.900/14.100)

0.0255/0.0375 (0.650/0.950)

0.005/0.009" (0.13/0.23)

10°-16°

6°±4°

10°-16°

L

11

ORDERING INFORMATION

Model Temperature Range Package Types

SP320ACF ...................................................0˚C to +70˚C......................... 80-pin JEDEC (BE-2 Outline) QFP

Please consult the factory for pricing and availability on a Tape-On-Reel option.

Corporation

SIGNAL PROCESSING EXCELLENCE

Sipex Corporation Headquarters and

Sales Office

22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com

Sales Office

233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.

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Datasheet SP320ACF Datasheet (Sipex Corporation)

Specifications and Main Features

Frequently Asked Questions

User Manual