Datasheet SNJ54LVT646FK, SNJ54LVT646JT, SNJ54LVT646W Datasheet (Texas Instruments)

SN54LVT646...JT OR W PACKAGE

SN74LVT646. . . DB, DW, OR PW PACKAGE

(TOP VIEW)

5
6
7
8
9
10
11

25
24
23
22
21
20
19

432128

12 13 14 15

16

OE
B1
B2
NC
B3
B4
B5

A1
A2
A3

NC

A4
A5
A6

SN54LVT646. . . FK PACKAGE

(TOP VIEW)

DIR

SAB

CLKAB

B8

B7

A8

GND

NC

NC

CLKBA

SBA

V

A7

B6

17 18

27 26

NC – No internal connection

CC

CLKAB

SAB

DIR

A1
A2
A3
A4
A5
A6
A7
A8

GND

V

CC

CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
B8

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

SN54LVT646, SN74LVT646

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS140D – MA Y 1992 – REVISED JULY 1995

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static Power
Dissipation

D

Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)

D

Support Unregulated Battery Operation
Down to 2.7 V

D

T ypical V

OLP

(Output Ground Bounce)

< 0.8 V at V

CC

= 3.3 V, TA = 25°C

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17

D

Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors

D

Support Live Insertion

D

Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and and Thin Shrink Small-Outline
(PW) Packages, Ceramic Chip Carriers
(FK), Ceramic Flat (W) Packages, and
Ceramic (JT) DIPs

description

These bus transceivers and registers are
designed specifically for low-voltage (3.3-V) V

CC

operation, but with the capability to provide a TTL
interface to a 5-V system environment.

The ’LVT646 consist of bus transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high
transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental
bus-management functions that can be performed with the ′LVT646.

Output-enable (OE

) and direction-control (DIR) inputs are provided to control the transceiver functions. In the

transceiver mode, data present at the high-impedance port may be stored in either register or in both.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The

direction control (DIR) determines which bus receives data when OE is low. In the isolation mode (OE high),
A data may be stored in one register and/or B data may be stored in the other register.

When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.

Copyright  1995, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54LVT646, SN74LVT646

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS140D – MA Y 1992 – REVISED JULY 1995

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74L VT646 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count

and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54L VT646 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74LVT646 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

DATA I/Os

OE DIR CLKAB CLKBA SAB SBA A1–A8 B1–B8

OPERATION OR FUNCTION

X X ↑ X X X Input Unspecified

†

Store A, B unspecified

†

X XX ↑ X X Unspecified

†

Input Store B, A unspecified

†

H X ↑ ↑ X X Input Input Store A and B data
H X H or L H or L X X Input disabled Input disabled Isolation, hold storage
L L X X X L Output Input Real-time B data to A bus
L L X H or L X H Output Input Stored B data to A bus
L H X X L X Input Output Real-time A data to B bus
L H H or L X H X Input Output Stored A data to B bus

†

The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled;
i.e., data at the bus pins is stored on every low-to-high transition of the clock inputs.

SN54LVT646, SN74LVT646

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS140D – MA Y 1992 – REVISED JULY 1995

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

21

L

3

DIR

L

1

CLKAB

X

23

CLKBA

X

2

SAB

X

22

SBA

L

REAL-TIME TRANSFER

BUS B TO BUS A

21

L

3

DIR

H

1

CLKAB

X

23

CLKBA

X

2

SAB

L

22

SBA

X

REAL-TIME TRANSFER

BUS A TO BUS B

21

X

3

DIR

X

1

CLKAB23CLKBA

X

2

SAB

X

22

SBA

X

STORAGE FROM
A, B, OR A AND B

21

L

3

DIR

L

1

CLKAB

X

23

CLKBA

H or L

2

SAB

X

22

SBA

H

TRANSFER STORED DATA

TO A AND/OR B

X
H

X
X

XX

X

X
X

L H H or L X H X

↑

↑
↑↑

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

OE

OE

OEOE

Figure 1. Bus-Management Functions

Pin numbers shown are for the DB, DW, JT, PW, and W packages.

SN54LVT646, SN74LVT646

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS140D – MA Y 1992 – REVISED JULY 1995

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol

†

OE

G3

21

3 EN2 [AB]

G5

22

SBA

A2

5

A3

6

A4

7

A5

8

A6

9

A7

10

A8

11

A1

4

B1

20

4D

B2

19

B3

18

B4

17

B5

16

B6

15

B7

14

B8

13

3 EN1 [BA]

3

DIR

23

CLKBA

1

CLKAB

G7

2

SAB

5

7

7

5

1

1

6D ≥1

≥1

1

2

C6

C4

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DB, DW, JT, PW , and W packages.

SN54LVT646, SN74LVT646

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS140D – MA Y 1992 – REVISED JULY 1995

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

A1

B1

1D

C1

1D

C1

One of Eight

Channels

20

4

2

1

22

23

21

3

SAB

CLKAB

SBA

CLKBA

DIR

OE

To Seven Other Channels

Pin numbers shown are for the DB, DW, JT, PW , and W packages.

SN54LVT646, SN74LVT646

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS140D – MA Y 1992 – REVISED JULY 1995

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

CC

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high state or power-off state, V

O

(see Note 1) –0.5 V to 7 V. . . .

Current into any output in the low state, IO: SN54LVT646 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74LVT646 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current into any output in the high state, I

O

(see Note 2): SN54LVT646 48 mA. . . . . . . . . . . . . . . . . . . . . . . . .

SN74LVT646 64 mA. . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

IK

(V

I

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

OK

(V

O

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum power dissipation at TA = 55°C (in still air) (see Note 3):DB package 0.65 W. . . . . . . . . . . . . . . . . . .

DW package 1.7 W. . . . . . . . . . . . . . . . . . .

PW package 0.7 W. . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and VO > VCC.

3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the

Package Thermal Considerations

application note in the 1994

ABT Advanced BiCMOS T echnology

Data Book

, literature number SCBD002B.

recommended operating conditions (see Note 4)

SN54LVT646 SN74LVT646

MIN MAX MIN MAX

UNIT

V

CC

Supply voltage 2.7 3.6 2.7 3.6 V

V

IH

High-level input voltage 2 2 V

V

IL

Low-level input voltage 0.8 0.8 V

V

I

Input voltage 5.5 5.5 V

I

OH

High-level output current –24 –32 mA

I

OL

Low-level output current 48 64 mA
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
T

A

Operating free-air temperature –55 125 –40 85 °C

NOTE 4: Unused control inputs must be held high or low to prevent them from floating.

SN54LVT646, SN74LVT646

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS140D – MA Y 1992 – REVISED JULY 1995

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

SN54LVT646 SN74LVT646

PARAMETER

TEST CONDITIONS

MIN TYP†MAX MIN TYP†MAX

UNIT

V

IK

VCC = 2.7 V, II = –18 mA –1.2 –1.2 V
VCC = MIN to MAX‡, IOH = –100 µA VCC–0.2 VCC–0.2
VCC = 2.7 V, IOH = – 8 mA 2.4 2.4

V

OH

IOH = – 24 mA 2

V

V

CC

=

3 V

IOH = –32 mA 2
IOL = 100 µA 0.2 0.2

V

CC

= 2.7

V

IOL = 24 mA 0.5 0.5
IOL = 16 mA 0.4 0.4

V

OL

IOL = 32 mA 0.5 0.5

V

V

CC

= 3

V

IOL = 48 mA 0.55
IOL = 64 mA 0.55

VCC = 3.6 V, VI = VCC or GND

Control

±1 ±1

VCC = 0 or MAX‡, VI = 5.5 V

inputs

10 10

I

I

VI = 5.5 V

100 20

µA

VCC = 3.6 V

VI = V

CC

A or B ports

§

1 1

VI = 0 –5 –5

I

off

VCC = 0, VI or VO = 0 to 4.5 V ±100 µA

VI = 0.8 V

p

75 75

I

I(hold)

V

CC

= 3

V

VI = 2 V

A or B ports

–75 –75

µ

A

I

OZH

VCC = 3.6 V, VO = 3 V 1 1 µA

I

OZL

VCC = 3.6 V, VO = 0.5 V –1 –1 µA

Outputs high 0.13 0.39 0.13 0.19

VCC = 3.6 V, IO = 0,

Outputs low 8.8 14 8.8 12

I

CC

VI = VCC or GND

Outputs
disabled

0.13 0.39 0.13 0.19

mA

∆I

CC

¶

VCC = 3 V to 3.6 V , One input at VCC – 0.6 V,
Other inputs at VCC or GND

0.3 0.2 mA

C

i

VI = 3 V or 0 4.5 4.5 pF

C

io

VO = 3 V or 0 11 11 pF

†

All typical values are at VCC = 3.3 V, TA = 25°C.

‡

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

§

Unused terminals at VCC or GND

¶

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

SN54LVT646, SN74LVT646

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS140D – MA Y 1992 – REVISED JULY 1995

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 2)

SN54LVT646 SN74LVT646

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

MIN MAX MIN MAX MIN MAX MIN MAX

f

clock

Clock frequency 0 150 0 150 0 150 0 150 MHz

t

w

Pulse duration, CLK high or low 3.3 3.3 3.3 3.3 ns
Setup time, A or B before CLKAB↑ or

Data high 1.5 1.5 1.3 1.3

t

su

Setu time, A or B before CLKAB↑ or

CLKBA↑

Data low

2.5 3.0 2 2.4

ns

t

h

Hold time, A or B after
CLKAB↑ or CLKBA↑

0.9 0.9 0.4 0.4 ns

switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 2)

SN54LVT646 SN74LVT646

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

MIN MAX MIN MAX MIN TYP†MAX MIN MAX

f

max

150 150 MHz

t

PLH

CLKBA or

1.2 5.9 6.9 1.8 3.8 5.7 6.7

t

PHL

CLKAB

A or B

1.2 5.9 6.6 2.1 3.8 5.7 6.4

ns

t

PLH

0.8 4.9 5.6 1.3 2.8 4.7 5.4

t

PHL

A or B

B or A

0.6 4.8 5.5 1 2.7 4.6 5.3

ns

t

PLH

1 6.4 7.4 1.4 3.7 6.2 7.2

t

PHL

SBA

or

SAB

‡

A or B

1 6.4 7 1.4 3.8 6.2 6.8

ns

t

PZH

0.6 6 7.4 1 3 5.8 7.2

t

PZL

OE

A or B

0.6 6.2 7.5 1 3.2 6 7.3

ns

t

PHZ

1.4 6.7 7.1 2.3 4.3 6.5 6.9

t

PLZ

OE

A or B

1.4 6.4 6.5 2.2 3.8 5.8 5.9

ns

t

PZH

0.6 6.7 7.7 1 3.4 6.5 7.5

t

PZL

DIR

A or B

0.8 6.5 7.3 1.2 3.4 6.3 7.1

ns

t

PHZ

0.8 7.4 8.3 1.7 4.1 7.2 8.1

t

PLZ

DIR

A or B

1 6.7 7 1.5 3.5 5.8 6.3

ns

†

All typical values are at VCC = 3.3 V, TA = 25°C.

‡

These parameters are measured with the internal output state of the storage register opposite to that of the bus input.

SN54LVT646, SN74LVT646

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS140D – MA Y 1992 – REVISED JULY 1995

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

1.5 V

t

h

t

su

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT FOR OUTPUTS

S1

6 V

Open

GND

500 Ω

500 Ω

Data Input

Timing Input

1.5 V

2.7 V

0 V

1.5 V 1.5 V

2.7 V

0 V

2.7 V

0 V

1.5 V 1.5 V

t

w

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

t

PLH

t

PHL

t

PHL

t

PLH

V

OH

V

OH

V

OL

V

OL

1.5 V 1.5 V

2.7 V

0 V

1.5 V1.5 V

Input

1.5 V

Output

Control

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

V

OL

V

OH

t

PZL

t

PZH

t

PLZ

t

PHZ

1.5 V

1.5 V

3 V

0 V

1.5 V
VOL + 0.3 V

1.5 V

VOH – 0.3 V

[

0 V

2.7 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

6 V

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

Figure 2. Load Circuit and Voltage Waveforms

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