Datasheet SN54CDC586WD, SNJ54CDC586WD Datasheet (Texas Instruments)

SN54CDC586

3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS

SGBS311 – FEBRUAR Y 1997

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Low Output Skew for Clock-Distribution
and Clock-Generation Applications

D

Operates at 3.3-V V

CC

D

Distributes One Clock Input to Twelve
Outputs

D

Two Select Inputs Configure Up to Nine
Outputs to Operate at One-Half or Double
the Input Frequency

D

No External RC Network Required

D

External Feedback Pin (FBIN) Is Used to
Synchronize the Outputs to the Clock Input

D

Application for Synchronous DRAM,
High-Speed Microprocessor

D

TTL-Compatible Inputs and Outputs

D

Outputs Drive Parallel 50-Ω Terminated
Transmission Lines

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Distributed VCC and Ground Pins Reduce
Switching Noise

D

Packaged in 56-Pin Ceramic Flat Package

description

The SN54CDC586 is a high-performance,
low-skew, low-jitter clock driver. It uses a
phase-lock loop (PLL) to precisely align, in both
frequency and phase, the clock output signals to
the clock input (CLKIN) signal. It is specifically
designed for use with popular microprocessors
operating at speeds from 50 MHz to 100 MHz, or
down to 25 MHz on outputs configured as
half-frequency outputs. The SN54CDC586
operates at 3.3-V V

CC

and is designed to drive a

properly terminated 50-W transmission line.
The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to CLKIN. One of

the 12 output clocks must be fed back to FBIN for the PLL to maintain synchronization between the CLKIN input
and the outputs. The output used as the feedback pin is synchronized to the same frequency as the CLKIN input.

The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. Select inputs
(SEL1, SEL0) configure up to nine Y outputs, in banks of three, to operate at one-half or double the CLKIN
frequency , depending on which pin is fed back to FBIN (see Tables 1 and 2). All output-signal duty cycles are
adjusted to 50%, independent of the duty cycle at CLKIN.

NC

AV

CC

AGND

FBIN

AGND

SEL0
SEL1

GND
GND

1Y1

V

CC

GND

1Y2

V

CC

GND

1Y3

V

CC

GND
GND

2Y1

V

CC

GND

2Y2

V

CC

GND

2Y3

V

CC

NC

NC
CLKIN
NC
AV

CC

OE
TEST
CLR
V

CC

4Y3
GND
V

CC

4Y2
GND
V

CC

4Y1
GND
GND
V

CC

3Y3
GND
V

CC

3Y2
GND
V

CC

3Y1
GND
GND
NC

WD PACKAGE

(TOP VIEW)

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NC – No internal connection

Copyright  1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54CDC586

3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS

SGBS311 – FEBRUAR Y 1997

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

Output-enable (OE) is provided for output control. When OE is high, the outputs are in the high-impedance state.
When OE

is low, the outputs are active. CLR is negative-edge triggered and can be used to reset the outputs
operating at half frequency . TEST is used for factory testing of the device and can be used to bypass the PLL.
TEST should be strapped to GND for normal operation.

Unlike many products containing PLLs, the SN54CDC586 does not require external RC networks. The loop filter
for the PLL is included on chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the SN54CDC586 requires a stabilization time to achieve phase lock of
the feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLKIN, as well as following any changes to the PLL reference or
feedback signals. Such changes occur upon change of the select inputs, enabling of the PLL via TEST , and upon
enable of all outputs via OE

.

The SN54CDC586 is characterized for operation over the full military temperature range of –55°C to 125°C.

detailed description of output configurations

The voltage-controlled oscillator (VCO) used in the SN54CDC586 PLL has a frequency range of 100 MHz to
200 MHz, twice the operating frequency range of the SN54CDC586 outputs. The output of the VCO is divided
by two and by four to provide reference frequencies with a 50% duty cycle of one-half and one-fourth the VCO
frequency. SEL0 and SEL1 select which of the two signals are buffered to each bank of device outputs.

One device output must be externally wired to FBIN to complete the PLL. The VCO operates such that the
frequency and phase of this output match that of CLKIN. In the case in which a VCO/2 output is wired to FBIN,
the VCO must operate at twice the CLKIN frequency , resulting in device outputs that operate at either the same
or one-half the CLKIN frequency . If a VCO/4 output is wired to FBIN, the device outputs operate at twice or the
same frequency as the CLKIN frequency.

SN54CDC586

3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS

SGBS311 – FEBRUAR Y 1997

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

output configuration A

Output configuration A is valid when any output configured as a 1x frequency output in Table 1 is fed back to
FBIN. The input frequency range for CLKIN is 50 MHz to 100 MHz when using output configuration A. Outputs
configured as 1/2x outputs operate at one-half the CLKIN frequency, while outputs configured as 1x outputs
operate at the same frequency as CLKIN.

Table 1. Output Configuration A

INPUTS

OUTPUTS

SEL1 SEL0

1/2X

FREQUENCY1XFREQUENCY

L L None All
L H 1Yn 2Yn, 3Yn, 4Yn
H L 1Yn, 2Yn 3Yn, 4Yn
H H 1Yn, 2Yn, 3Yn 4Yn

NOTE: n = 1, 2, 3

output configuration B

Output configuration B is valid when any output configured as a 1x frequency output in Table 2 is fed back to
FBIN. The input frequency range for CLKIN is 25 MHz to 50 MHz when using output configuration B. Outputs
configured as 1x outputs operate at the CLKIN frequency, while outputs configured as 2x outputs operate at
double the frequency of CLKIN.

Table 2. Output Configuration B

INPUTS

OUTPUTS

SEL1 SEL0

1X

FREQUENCY2XFREQUENCY

L L All None
L H 1Yn 2Yn, 3Yn, 4Yn

H L 1Yn, 2Yn 3Yn, 4Yn
H H 1Yn, 2Yn, 3Yn 4Yn

NOTE: n = 1, 2, 3

SN54CDC586

3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS

SGBS311 – FEBRUAR Y 1997

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Phase-Lock Loop

One of Three Identical

Outputs – 1Yn

One of Three Identical

Outputs – 2Yn

One of Three Identical

Outputs – 3Yn

One of Three Identical

Outputs – 4Yn

CLR

CLKIN

TEST

SEL1

SEL0

FBIN

OE

Select

Logic

1Y1–1Y3

2Y1–2Y3

3Y1–3Y3

4Y1–4Y3

CLR

B

2

52

50

4

55

51

6

7

B

2

10, 13, 16

20, 23, 26

32, 35, 38

42, 45, 48

SN54CDC586

3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS

SGBS311 – FEBRUAR Y 1997

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

CLKIN 55 I

Clock input. CLKIN is the clock signal distributed by the SN54CDC586 clock-driver circuit. CLKIN provides
the reference signal to the integrated PLL that generates the clock output signals. CLKIN must have a fixed
frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLKIN
signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference
signal.

CLR 50 I

Clear. CLR resets the VCO/4 reference frequency . CLR is negative-edge triggered and should be strapped
to GND or VCC for normal operation.

FBIN 4 I

Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hardwired to one of
the 12 clock outputs to provide frequency and phase lock. The internal PLL adjusts the output clocks to
obtain zero phase delay between FBIN and CLKIN.

OE 52 I

Output enable. OE is the output enable for all outputs. When OE is low, all outputs are enabled. When OE
is high, all outputs are in the high-impedance state. Since the feedback signal for the PLL is taken directly
from an output terminal, placing the outputs in the high-impedance state interrupts the feedback loop;
therefore, when a high-to-low transition occurs at OE

, enabling the output buffers, a stabilization time is

required before the PLL obtains phase lock.

SEL1, SEL0 7, 6 I

Output configuration select. SEL0 and SEL1 select the output configuration for each output bank
(e.g., 1×, 1/2×, or 2×). (see Tables 1 and 2).

TEST 51 I

TEST is used to bypass the PLL circuitry for factory testing of the device. When TEST is low, all outputs
operate using the PLL circuitry. When TEST is high, the outputs are placed in a test mode that bypasses
the PLL circuitry. TEST should be strapped to GND for normal operation.

1Y1–1Y3
2Y1–2Y3
3Y1–3Y3

10, 13, 16
20, 23, 26
32, 35, 38

O

Output ports. These outputs are configured by SEL1 and SEL0 to transmit one-half or one-fourth the
frequency of the VCO. The relationship between the CLKIN frequency and the output frequency is
dependent on SEL1 and SEL0 and the frequency of the output being fed back to FBIN. The duty cycle of
the Y -output signals is nominally 50%, independent of the duty cycle of CLKIN.

4Y1–4Y3 42, 45, 48 O

Output ports. 4Y1–4Y3 transmit one-half the frequency of the VCO regardless of the state of SEL1 and
SEL0. The relationship between the CLKIN frequency and the output frequency is dependent on the
frequency of the output being fed back to FBIN. The duty cycle of the Y-output signals is nominally 50%,
independent of the duty cycle of CLKIN.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

CC

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high or power-off state,

V

O

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current into any output in the low state, I

O

64 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

IK

(V

I

< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

OK

(V

O

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

SN54CDC586

3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS

SGBS311 – FEBRUAR Y 1997

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 2)

MIN MAX UNIT

V

CC

Supply voltage 3 3.6 V

V

IH

High-level input voltage 2 V

V

IL

Low-level input voltage 0.8 V

V

I

Input voltage 0 5.5 V

I

OH

High-level output current –32 mA

I

OL

Low-level output current 32 mA

T

A

Operating free-air temperature –55 125 °C

NOTE 2: Unused inputs must be held high or low to prevent them from floating.

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

TA = 25°C

PARAMETER

TEST CONDITIONS

MIN MAX

UNIT

V

IK

VCC = 3 V, II = –18 mA –1.2 V
VCC = MIN to MAX†, IOH = –100 µA VCC–0.2

V

OH

VCC = 3 V, IOH = – 32 mA 2

V

IOL = 100 µA 0.2

V

OL

V

CC

= 3

V

IOL = 32 mA 0.5

V

VCC = 0 or MAX†, VI = 3.6 V ±10

I

I

VCC = 3.6 V, VI = VCC or GND ±1

µ

A

I

OZH

VCC = 3.6 V, VO = 3 V 10 µA

I

OZL

VCC = 3.6 V, VO = 0 –10 µA

Outputs high 1

I

CC

VCC = 3.6 V, IO = 0,

Outputs low 1

mA

V

I

=

V

CC

or

GND

Outputs disabled 1

C

i

VI = VCC or GND 4 pF

C

o

VO = VCC or GND 8 pF

†

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

SN54CDC586

3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS

SGBS311 – FEBRUAR Y 1997

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirements over recommended ranges of supply voltage and operating free-air
temperature

MIN MAX UNIT

VCO is operating at four times the CLKIN frequency 25 50

f

clock

Clock frequenc

y

VCO is operating at double the CLKIN frequency

50 100

MH

z

Input clock duty cycle 40% 60%

After SEL1, SEL0 50
After OE↓ 50

Stabilization time

†

After power up 50

µ

s

After CLKIN 50

†

Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency , fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for propagation delay
and skew parameters given in the switching characteristics table are not applicable.

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

L

= 30 pF, unless otherwise noted (see Note 3 and Figures 1 through 3)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

MIN MAX UNIT

f

max

100 MHz
Duty cycle Y 42% 58%
t

phase error

‡

CLKIN↑ Y –900 200 ps

Jitter

(pk-pk)

*

CLKIN↑ Y 200 ps

t

sk(o)

‡

0.75 ns

t

sk(pr)

‡*

1.1 ns

t

r

1.4 ns

t

f

1.4 ns

* On products compliant to MIL-PRF-38535, this parameter is not production tested.
‡

The propagation delay, t

phase error

, is dependent on the feedback path from any output to FBIN. The t

phase error

, t

sk(o)

, and t

sk(pr)

specifications

are valid only for equal loading of all outputs.

NOTE 3: The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.

SN54CDC586

3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS

SGBS311 – FEBRUAR Y 1997

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

LOAD CIRCUIT

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

t

phase error

1.5 V 1.5 V

3 V

0 V

1.5 V

V

OH

V

OL

Input

0.8 V

2 V

t

r

t

f

0.8 V

2 V

Output

Output

Under Test

C

L

V

TH

I

OL

I

OH

NOTES: A. CL includes probe and jig capacitance.

B. The outputs are measured one at a time with one transition per measurement.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.

t

phase error

tr, t

f

32 mA
16 mA

PARAMETER I

OL

32 mA
16 mA

I

OH

1.5 V

1.5 V

V

TH

20 pF
20 pF

CL (typical)

Figure 1. Load Circuit and Voltage Waveforms

SN54CDC586

3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS

SGBS311 – FEBRUAR Y 1997

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

t

phase error 1

t

phase error 2

t

phase error 3

t

phase error 4

t

phase error 5

t

phase error 6

CLKIN

Outputs

Operating

at 1/2 CLKIN

Frequency

Outputs

Operating

at CLKIN

Frequency

t

phase error 9

t

phase error 8

t

phase error 7

NOTES: A. Output skew, t

sk(o)

, is calculated as the greater of:

– The difference between the fastest and slowest of t

phase error n

(n = 1, 2,...6)

– The difference between the fastest and slowest of t

phase error n

(n = 7, 8, 9)

B. Process skew, t

sk(pr)

, is calculated as the greater of:

– The difference between the maximum and minimum t

phase error n

(n = 1, 2, . .. 6) across multiple

devices under identical operating conditions.

– The difference between the maximum and minimum t

phase error n

(n = 7, 8, 9) across multiple devices

under identical operating conditions.

Figure 2. Waveforms for Calculation of t

sk(o)

SN54CDC586

3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS

SGBS311 – FEBRUAR Y 1997

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

t

phase error 10

t

phase error 11

t

phase error 12

t

phase error 15

CLKIN

Outputs

Operating

at CLKIN

Frequency

Outputs

Operating

at 2X CLKIN

Frequency

t

phase error 13

t

phase error 14

NOTES: A. Output skew, t

sk(o)

, is calculated as the greater of:

– The difference between the fastest and slowest of t

phase error n

(n = 10, 11,...15)

B. Process skew, t

sk(pr)

, is calculated as the greater of:

– The difference between the maximum and minimum t

phase error n

(n = 10, 11,. . . 15) across multiple devices

under identical operating conditions.

Figure 3. Waveforms for Calculation of t

sk(o)

and t

sk(pr)

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Copyright  1998, Texas Instruments Incorporated