SNAD01B
8-CHANNEL 8-BIT ADC
======== CONTENTS ========
1. GENERAL DESCRIPTION....................................................................................................................................... 3
2. FEATURES....................................................................................................................................................................3
3. APPLICATIONS .......................................................................................................................................................... 3
4. BLOCK DIAGRAM.....................................................................................................................................................4
5. PIN ASSIGNMENT......................................................................................................................................................4
6. FUNCTIONAL DESCRIPTIONS ............................................................................................................................. 5
NTERFACE FORMAT
I
HANNEL SETTING
C
ONTROL REGISTER SETTING
C
EAD TIMING
ADC R
IMING OF DIGITAL INPUT READING
T
OWER DOWN
P
ANDGAP REFERENCE
B
NPUT CHANNEL
I
ATTERY MONITORING (CHANNEL 7 ONLY
B
.............................................................................................................................................................5
...............................................................................................................................................................7
..............................................................................................................................................7
..............................................................................................................................................................8
...................................................................................................................................9
HANNEL WAKE-UP
& C
.............................................................................................................................10
........................................................................................................................................................11
PAD (C
HANNEL
0~6) ............................................................................................................................12
) ....................................................................................................................13
7. ELECTRICAL CHARACTERISTICS ..................................................................................................................14
8. APPLICATION CIRCUITS.....................................................................................................................................15
XAMPLE CIRCUIT
E
: SNAD01B
WORKS WITH SONIX 4-BIT SERIES CONTROLLER
..........................................................15
9. EXAMPLE PROGRAMS:........................................................................................................................................16
10.
P
P
P
P
P
ROGRAM
ROGRAM
ROGRAM
ROGRAM
ROGRAM
ET CONFIGURATION OF
1: S
EAD
2: R
EAD DIGITAL INPUT DATA FROM CH
3: R
OWER-DOWN
4: P
ATTERY LOW DETECTION
5: B
RESULT FROM CHANNEL
ADC
SNAD01B
SNAD01B..........................................................................................................27
1 ......................................................................................................27
4, CH3, CH2 ..................................................................................28
AND HOST, AND WAKE-UP
..............................................................................28
.........................................................................................................................29
PAD DIAGRAM...................................................................................................................................30
Version: 1.3 July 31, 2003
1
SNAD01B
8-CHANNEL 8-BIT ADC
AMENDMENT HISTORY
Version Date Description
Ver 1.1 February 12, 2003 First issue.
Ver 1.3 July 31, 2003 1. Add the version code “B” of chip no.
2. This spec is modified form SNAD01_V1.3
3. Add standby current more than 50 uA in page 10
Note: This document is used to identify the different version “B” & “C” of SNAD01, the most
important is standby current and power down setting between version “B” & “C”. For the detail
please refer to related section.
Version: 1.3 July 31, 2003
2
SNAD01B
8-CHANNEL 8-BIT ADC
1. GENERAL DESCRIPTION
SNAD01B is a low cost serial 8-bits ADC with 8 individual input channels. Each channel can
be independently programmed to a digital or analog input mode. In the analog input mode, this
single-ended channel accepts an analog input signal from 0 to V
12-
bit digital codes (with 8-bit accuracy guaranteed). In the digital input mode, the channel can be
treated as digital input port and the logic level appears at the channel can be acquired. SNAD01B
has a synchronous 3-wires serial interface. Through this interface, the host CPU can easily control
SNAD01B.
During A-to-D conversion, the typical current consumption is 500uA at 25kHz throughput-rate
and +3V power supply. SNAD01B includes a power-down mode, which reduces maximum current
consumption to less than 1uA.
and converts the signal into
REF
The reference voltage can be varied between 1V and +V
voltage range of 0V to V
. SNAD01B also has an on-chip 1.17V bandgap reference that can be
REF
, providing a corresponding input
CC
utilized for constant voltage input (especially for battery monitoring applications). The bandgap
reference circuitry consumes 300µA@3v and can be enabled and disabled.
2. FEATURES
♦
Single Supply: 2.7V ~ 5.25V
♦
Eight Analog/Digital Input Channels.
♦
Internal 1.17v Bandgap Reference for Battery Monitoring. (Channel 7)
♦
Low Power Consumption: typical operating current: 500uA @ 3V, Standby current <1uA.
♦
Up to 25kHz Conversion Rate.
♦
8-bits Resolution with (8-bits) No Missing Code.
♦
3-Wire Serial Interface.
3. APPLICATIONS
♦
Battery-Powered Systems
♦
Instrumentation
♦
Portable Data Logging
♦
Test Equipment
♦
Data Acquisition
♦
Process-Control Monitoring
Version: 1.3 July 31, 2003
3
Digital Input Bus Extender ♦
4. BLOCK DIAGRAM
1.2V Bandgap
Reference
VRH
SNAD01B
8-CHANNEL 8-BIT ADC
AVDD VDDD
CH0/DI0
CH1/DI1
CH2/DI2
CH3/DI3
CH4/DI4
CH5/DI5
CH6/DI6
CH7(BAT)/DI7
8-Channels
Analog/Digital
Input MUX
8-bit SAR
ADC
AVSS VSSD
Figure1 Block diagram of ADC.
5. PIN ASSIGNMENT
Pin Name I/O Description
CH[7] ~ CH[0] I Analog input / digital input
REF I Reference voltage of analog signal
VDD I Positive power
Serial
Interface
and
Control
Logic
START
CLK
DIO
VSS I Negative power
AVDD I Positive power of analog circuit
AVSS I Negative power of analog circuit
START I Command initialization signal (from host
controller)
CLK I Clock of data communication and AD
conversion (from host controller)
DIO IO Data input and output of data communication
Version: 1.3 July 31, 2003
4
6. Functional Descriptions
SNAD01B
8-CHANNEL 8-BIT ADC
VDD
Host CPU
SNAD01
VDD
Output Port1
Output Port2
I/O port
START
CLK
DIO
START
CLK
DIO
AVDD
REF
0.1uF
VSS
`
AVSS
CH[0]
CH[1]
Analog/Digital
Signal
CH[7]
Figure2 Interface with Host CPU
Interface Format
START
CLK
annel Setting
Ch
DIO
Contr
DIO
ADC
DIO
Digital Input Reading
DIO
Power Down
DIO
HiZ
ol Register Setting
HiZ
Reading
HiZ
HiZ
Port Input
HiZ
Port Input
Figure3 Timing Diagram of Whole Commands
CM1 CM0CM2 CH[7] CH[6] CH[5] CH[4] CH[3] CH[2] CH[1] CH[0]
CM1 CM0CM2 PH PL RF MB xx xx xx xx
CM1 CM0 ID2 ID1 ID0CM2
Port Input
CM1 CM0CM2 DI[6] DI[5] DI4] DI[3] DI[2] DI[1] DI[0]
CM1 CM0CM2
DI[7]
xx
PDS
Port Input
Port Input
D6 D5D7
Port Output
Port Output
Port Output
xxx
xxx
D3 D2D4 D0D1
DI[7] DI[6] DI[5] DI4] DI[3]
~PDS
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SNAD01B
8-CHANNEL 8-BIT ADC
1. DIO is HiZ while START is HIGH.
2. The interface logic begins to interpret a command at the falling edge of the START signal.
3. The command ID (sent by Host) is received in the first three clock cycles from DIO.
4. The operations include Channel setting, ADC Reading, Digital Input Reading and Power
Down.
5. DIO becomes to HiZ while START returns to HIGH.
Command ID Operation
000 Power Down (0)
001 Channel Attribute Setting (1:Analog, 0:Digital)
010 Channel Wakeup Function Setting
(1:Enable, 0:Disable)
011 Control Register Setting
100 ADC Conversion
101 Digital Input Reading
110 Reserved
111 Power Down (1)
Table1 Command Description Table
1. 000/111: ADC enters into power down after receiving this command.
2. 001: Set the attribute each channel to be an analog or a digital input with the sequence of
channel 7 to 0. (1:Analog; 0:Digital)
3. 010: Set the wakeup function of each channel to be enabled or disabled with the sequence
of channel 7 to 0. (1:Enable; 0:Disable)
4. 011: Setting the values of control registers.
5. 100: ADC starts to convert the analog signal of the selected channel after receiving this
command.
6. 101: ADC starts to read the digital input of every channel with the sequence of channel 7 to
0.
7. 110: ADC enters into testing mode.
Version: 1.3 July 31, 2003
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SNAD01B
8-CHANNEL 8-BIT ADC
Channel Setting
START
CLK
DIO 0/1 1/00/0 CH[7] CH[6] CH[5] CH[4] CH[3] CH[2] CH[1] CH[0] xxx
HiZ
Port Input
Figure3 The timing diagram of channel attribute/wakeup setting
Command 001: channel attribute setting. Command 010: wakeup function setting.
In attribute setting, “1” means analog and “0” means digital. In wakeup setting, “1” means
enable and “0” means disable. After all of the channels are set, the DIO port remains input
mode and all the following data are ignored.
Control Register Setting
START
CLK
DIO 1 10 PH PL RF MB xxx
HiZ
xxx xxx xxx xxx
Port Input
Figure4 The timing diagram of control registers setting
1. Command ID: (011)
2. 4-bit data behind command ID are loaded into control registers with the sequence of PH,
PL, RF and MB.
3. The function of each control registers are as Table2.
Version: 1.3 July 31, 2003
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SNAD01B
8-CHANNEL 8-BIT ADC
Name Function
PH Set the pull-up resistor of the channel in digital input mode. 1:ON,
0:OFF.
PL Set the pull-down resistor of the channel in digital input mode. 1:ON,
0:OFF.
RF Set the Bandgap reference. 1:ON, 0:OFF.
MB For testing chip only, always set MB=0 in system power-on initialization
routine.
Table2 The function table of control registers
Note:
1. The condition of both PH=1 and PL=1 is prohibited.
2. Pull-up and pull-down resistors are not activated while the corresponding channel is set
as analog input mode.
ADC Read Timing
START
CLK
t
ACQ
xx
D7 D6 D4 D3D5 D1 D0D2
xx PDS
DIO
HiZ
0 0 ID2 ID1 ID01
Port Input Port Output
Figure5 The timing diagram of ADC reading
1. Command ID: (100)
2. 3-bit channel number data behind command ID.
3. The analog signal of the selected channel is sampled to ADC. ADC refers the reference
voltage and converts the sampled analog signal to digital domain by successive-
approximation method.
4. The 8-bit output data (result of conversion) of ADC is sent to DIO port from MSB and is
triggered by CLK. The maximum clock frequency is 500kHz @ 2.7v. (Maximum conversion
rate=25KHz)
Version: 1.3 July 31, 2003
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SNAD01B
8-CHANNEL 8-BIT ADC
5. After the 8-bits ADC data has been sent out, if the START is kept in LOW and CLK is kept
in High/Low transition, then the data with uncertain value are kept appearing on DIO. These
data can just be ignored.
Channel ID[2:0] Selected Channel
000 CH0
001 CH1
010 CH2
011 CH3
100 CH4
101 CH5
110 CH6
111 CH7
Table3 Channel Selection Table.
Timing of Digital Input Reading
START
CLK
HiZ
DIO 0 11 DI[6] DI[5] DI4] DI[3] DI[2] DI[1] DI[0] DI[7] DI[6] DI[5] DI4] DI[3] DI[2] DI[1] DI[0] DI[7]
Port Input Port Output
Figure6 The timing diagram of the digital input reading
1. Command ID: (101).
2. The digital data of each channel is sent to the DIO port with the sequence of channel 7 to 0.
DI[7]
3. After all of the channels are read, if the START is kept in LOW and CLK is kept in
HIGH/LOW transition, the digital data of each channel is sent to the DIO port again with the
sequence of channel 7 to 0 cyclically.
4. Pulling START to HIGH terminates this digital input reading.
Note: Once a channel is programmed as analog type, the corresponding data is “0” in digital
input reading command.
Version: 1.3 July 31, 2003
9
SNAD01B
8-CHANNEL 8-BIT ADC
Power Down & Channel Wake-Up
START
CLK
SNAD01 enters into
DIO
000
power-down mode
DIO
111
Figure7 The timing diagram of power down command
START
Wake-Up
CLK
CH n
CH n
DIO
Wake-Up
Host CPU
DIO
Procedure Ending
HiZ
HiZ
Figure8 The timing diagram of power down command
1. The power down command (000/111) is sent to SNAD01B in the first three cycles, and
then SNAD01B enters into power down mode at the 5
th
clock cycle, consuming almost no
current (less than 1uA).
2. After SNAD01B enters power down (mode 0: command 000), SNAD01B sends “0” out to
DIO until a valid logic transition appears on any wakeup-enabled digital input channel. Once
the transition occurs, SNAD01B toggles DIO to “1” to inform host controller. After receiving
“1” from DIO, host controller should turn START back to “1” to inform SNAD01B that the
power-down stage is over. Otherwise, SNAD01B keeps sending out “1” to DIO and does not
recognize any other transitions on any channels.
Version: 1.3 July 31, 2003
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SNAD01B
8-CHANNEL 8-BIT ADC
3. After SNAD01B enters power down (mode 1: command 111), SNAD01B sends “1” out to
DIO until a valid logic transition appears on any wakeup-enabled digital input channel. Once
the transition occurs, SNAD01B toggles DIO to “0” to inform host controller. After receiving
“0” from DIO, host controller should turn START back to “1” to inform SNAD01B that the
power-down stage is over. Otherwise, SNAD01B keeps sending out “1” to DIO and does not
recognize any other transitions any the channels.
4. The CLK may stop but START ought to remain at LOW level in the whole power down
mode.
Note:
1. Wakeup function is only dedicated to the channel which is digital input type AND
wakeup-enabled.
2. In SNAD01B version, the standby current will more than 50uA in AD conversion
reference voltage use “REF” pin connected external voltage.
Bandgap reference
ON CHIP OFF CHIP
REF
PAD
1.2v
bandgap
reference
Figure8 Circuit diagram of ADC bandgap reference selection
VDD
VSS
to reference
high of the ADC
RF
RF+RF MB
If the internal bandgap reference is turned ON (RF=1), the reference voltage of ADC is
supplied by output voltage of the internal bandgap reference circuit. This bandgap
consumes about 300 µA. The output voltage of bandgap reference is around 1.17V
typically.
Note: MB for chip test only. Always set MB=0 with command (011) in System Power-On
Initialization Routine.
Version: 1.3 July 31, 2003
11
SNAD01B
8-CHANNEL 8-BIT ADC
Input Channel PAD (Channel 0~6)
VDD
ENCH[x]: 1: Analog In / 0: Digital In
PH&ENCH[x]
CH[x]
PL&ENCH[x]
Pull-high resistor
Pull-low resistor
VSS
ENCH[x]
to ADC
DI[x]
ENCH[x]
Figure9 Circuit diagram of the Input Channel PAD
1. If a channel is programmed to analog input mode, then the corresponding internal signal,
ENCH[x],=1. As in Figure9, pull-high and pull-low are disabled. And the path to digital input is
blocked. All digital reading operation of this channel will get the result “0”.
2. If a channel is programmed to digital input mode, then the corresponding internal signal,
ENCH[x],=0. As in Figure9, the path to ADC is removed.
3. While in digital input mode, this input port can be configured to be floating, weak pull up, or
pull down by setting the control register PH and PL as Figure9, where PH&PL=1 is forbidden.
The weak pull resistance is about 500KΩ@3v.
4. The default status (digital/analog, pull up/down) of the channels are not defined after power
on, so initialization of each channel to define a correct state should be done.
5. Mode of each channel (ENCH[x]) can be set by command 001.
Version: 1.3 July 31, 2003
12
SNAD01B
8-CHANNEL 8-BIT ADC
Battery Monitoring (Channel 7 only)
VDD
ENCH[7]
PH&ENCH[x]
DI[7]
20k
to ADC
10k
ENCH[7]
VSS
Battery
CH[7]
VSS
30k
PL&ENCH[x]
VSS
Figure10 The circuit of the Input pad of Channel 7
1. While read ADC command is sent and channel 7 is selected, ADC can be used to monitor
the battery voltage.
The circuit of battery voltage monitoring is shown in Battery Monitoring (Channel7 only)
2.
3. The battery voltage is six times ADC measuring voltage. Thus, the measured result equals
to 1/6*battery voltage.
4. While channel 7 is set to the analog input mode, an input resistor (60kΩ) exists from CH[7]
to VSS. To save unnecessary power consumption, CH[7] should be switch to digital input
type when CH[7] is not measured.
Note: CH[7] is different from the other 7 channels. The input voltage is reduced to 1/6 before it is sent
into ADC.
Version: 1.3 July 31, 2003
13
7. ELECTRICAL CHARACTERISTICS
SNAD01B
8-CHANNEL 8-BIT ADC
Typical values apply for VDD=V
Symbol Parameter min typ max Uni
=3.0 V, T
REF
=25 °C unless otherwise noted.
AMB
Conditions
t
Analog-to-Digital Converter
VDD Operating voltage 2.7 3.0 5.25 V
IDD Operating current 400 650
µA
Excluding
bandgap reference
I
Power Down Current 0.1 2 µA
PDN
F
Conversion Rate
SMP
30
VDD=3.0V
kHz
(Throughput Rate)
40
VDD=5.0V
DNL Differential Nonlinearity ±0.5 LSB
INL Integral Nonlinearity ±-0.5 LSB
NMC No Missing Code 8 Bits VDD=2.7~5.25V
SINAD Signal to Noise and
Distortion
50
dB
ENOB Effective Number of Bits 8 Bits
Bandgap reference
VBG Bandgap reference
1.14 1.17 1.20
V
output voltage
IBG Operating current of
BGR
400
µA
Digital Interface
Weak pull up/down
resistance
500
k
Ω
V
VIL Input low voltage -0.3 0.8 V
VIH Input high voltage VDD-0.7 VDD+0.3 V
VOL Output low voltage 0 0.4 V
VOH Output high voltage VDD-0.5 VDD V
Output drive/sink current of
3
VOP=VDD-0.5v/VSS+0.5v
mA
DIO
DD
=3V
Version: 1.3 July 31, 2003
14
8. APPLICATION CIRCUITS
Example Circuit: SNAD01B works with Sonix 4-bit Series Controller
CH[0], CH[1], CH[2]: Analog Input
CH[6]: Digital Input
CH[7]: Battery Voltage Detect
REF=VDD+
SNAD01B
8-CHANNEL 8-BIT ADC
VDD
0.1uF
`
Analog Signal
Analog Signal
Analog Signal
VDD
4-bit Voice chip
P22
P21
P20
VSS
SN300/500
SN65/66/67/68/6A
VDD
START
CLK
DIO
SNAD01
VDD
AVDD
REF
VSS
AVSS
CH[0]
CH[1]
CH[2]
CH[6]
CH[7]
Figure11
SNAD01B works with Sonix 4-bit Series Controller
Version: 1.3 July 31, 2003
15
9. Example Programs:
Host Controller: SNC500. Application circuit is identical to Figure11. P22: START.
P21: CLK. P20: DIO.
Macro Programs: (def.h) ♦
p2State equ m0
port_l equ m1
port_h equ m2
ad_out_l equ m3
ad_out_h equ m4
tmp equ m5
tmp1 equ m6
;;********************************
@ON_START macro ;;SET START=0
mov a #1011b
and a p2state
mov p2state a
mov p2 a
endm
;;********************************
@OFF_START macro ;;SET START=1
mov a #0100b
or a p2state
mov p2state a
mov p2 a
endm
;;********************************
@CLOCK macro
mov a #0010b ;;SET CLK LÆ H AND HÆ L
or a p2state
mov p2 a
mov a #1101b
and a p2state
mov p2state a
mov p2 a
endm
;;********************************
@Send_0 macro
mov a #1110b ;;HOST SEND 0 Æ DIO
and a p2state
SNAD01B
8-CHANNEL 8-BIT ADC
Version: 1.3 July 31, 2003
16
SNAD01B
8-CHANNEL 8-BIT ADC
mov p2state a
mov p2 a
endm
;;********************************
@Send_1 macro
mov a #0001b ;;HOST SEND 1 Æ DIO
or a p2state
mov p2state a
mov p2 a
endm
;;********************************
@Send macro data; ;HOST SEND 1-BIT CONSTANT (#1 OR #0) Æ DIO
mov tmp data
mov a #1110b
and a p2state
or a tmp
mov p2state a
mov p2 a
endm
;;********************************
@Read_DIO macro ;;READ DIO Æ A.0 (1-BIT)
mov a p2
mov tmp #0001b
and a tmp
endm
;;********************************
@P20_Out_Mode macro ;;SWITCH ALL 4-BIT OF P2 TO OUTPUT MODE
mov a #0000b
mov p2s a
endm
;;********************************
@P20_In_Mode macro ;;SWITCH P2.0 (DIO) TO INPUT MODE
mov a #0001b
mov p2s a
mov a #1110b
and a p2state
mov p2state a
mov p2 a
endm
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SNAD01B
8-CHANNEL 8-BIT ADC
;;**************************************************************************
;; Set Analog/Digital Mode to each channel (1:Analog, 0:Digital) *
;; y7 Æ Ch7. y6 Æ Ch6. y5 Æ Ch5, … *
;;**************************************************************************
@Set_Attrib macro y7,y6,y5,y4,y3,y2,y1,y0
@P20_Out_mode ;; SWITCH P2 TO OUTPUT MODE
@ON_START ;; SET START=0
@Send_0 ;; SEND COMMAND (001)
@Clock
@Send_0
@Clock
@Send_1
@Clock
@Send y7 ;; SEND y7 TO y0
@Clock
@Send y6
@Clock
@Send y5
@Clock
@Send y4
@Clock
@Send y3
@Clock
@Send y2
@Clock
@Send y1
@Clock
@Send y0
@Clock
@OFF_START ;; SET START=1
@P20_In_mode ;; SWITCH P2.0 TO INPUT MODE
endm
;;*************************************************************************
;; Set Wakeup function Enable/Disable (1:Enable, 0:Disable) *
;; y7 Æ Ch7. y6 Æ Ch6. y5 Æ Ch5, … *
;;*************************************************************************
@Set_Wakeup macro y7,y6,y5,y4,y3,y2,y1,y0
@P20_Out_mode ;; SWITCH P2 TO OUTPUT MODE
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SNAD01B
8-CHANNEL 8-BIT ADC
@ON_START ;; SET START=0
@Send_0 ;; SEND COMMAND (010)
@Clock
@Send_1
@Clock
@Send_0
@Clock
@Send y7 ;; SEND y7 TO y0
@Clock
@Send y6
@Clock
@Send y5
@Clock
@Send y4
@Clock
@Send y3
@Clock
@Send y2
@Clock
@Send y1
@Clock
@Send y0
@Clock
@OFF_START ;; SET START=1
@P20_In_mode ;; SWITCH P2.0 TO INPUT MODE
endm
;;**********************************************************************
;; Setup Control Register *
;; ph: PULL-HIGH register. pl:PULL-LOW register. *
;; rf: BANDGAP reference enable *
;; mb: Set 0 always *
;;**********************************************************************
@Set_Control_Reg macro ph,pl,rf,mb
@P20_Out_mode ;; SWITCH P2 TO OUTPUT MODE
@ON_START ;; SET START=0
@Send_0 ;; SEND COMMAND (011)
@Clock
@Send_1
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SNAD01B
8-CHANNEL 8-BIT ADC
@Clock
@Send_1
@Clock
@Send ph ;; SEND ph, pl, rf, mb
@Clock
@Send pl
@Clock
@Send rf
@Clock
@Send mb
@Clock
@OFF_START ;; SET START=1
@P20_In_mode ;; SWITCH P2.0 TO INPUT MODE
endm
;;*******************************************************************
;; Let SNAD01B Enter Power-Down mode 0 *
;;*******************************************************************
@Power_Down_0 macro
@P20_Out_mode ;; SWITCH P2 TO OUTPUT MODE
@ON_START ;; SET START=0
@Send_0 ;; SEND COMMAND (000)
@Clock
@Send_0
@Clock
@Send_0
@Clock
@P20_In_mode ;; SWITCH P2.0 TO INPUT MODE
@Clock
@Clock
@Clock
@Clock
@Clock ;; SNAD01B ENTERS POWER-DOWN AT THE 8-th CLOCK EDGE.
Endm
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SNAD01B
8-CHANNEL 8-BIT ADC
;;*****************************************************************
;; Let SNAD01B Enter Power-Down mode 1 *
;;*****************************************************************
@Power_Down_1 macro
@P20_Out_mode ;; SWITCH P2 TO OUTPUT MODE
@ON_START ;; SET START=0
@Send_1 ;; SEND COMMAND (111)
@Clock
@Send_1
@Clock
@Send_1
@Clock
@P20_In_mode ;; SWITCH P2.0 TO INPUT MODE
@Clock
@Clock
@Clock
@Clock
@Clock ;; SNAD01B ENTERS POWER-DOWN AT THE 8-th CLOCK EDGE.
endm
;;*****************************************************************
;; Read ADC from Channel n (n=n2,n1,n0) *
;; e.g.: Ch 5 (n2, n1, n0= #1, #0, #1 *
;; 8-bit Data Æ (ad_out_h, ad_out_l) *
;;*****************************************************************
@Read_ADC macro n0, n1, n2
@P20_Out_mode ;; SWITCH P2 TO OUTPUT MODE
@ON_START ;; SET START=0
@Send_1 ;; SEND COMMAND (100)
@Clock
@Send_0
@Clock
@Send_0
@Clock
@Send n2 ;; SEND CHANNEL NUMBER
@Clock
@Send n1
@Clock
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SNAD01B
8-CHANNEL 8-BIT ADC
@Send n0
@Clock
@p20_in_mode ;; SWITCH P2.0 TO INPUT MODE
@Clock ;; WAIT FOR 2 MORE CLOCKS
@Clock
mov ad_out_l #0
mov ad_out_h #0
;;***************************************
@Clock ;; READ DIO and SAVE 1-bit DATA in ad_out_h.3
mov tmp1 #1000b
@Read_DIO
caje #0 @f
mov a ad_out_h
or a tmp1
mov ad_out_h a
@@:
;;***************************************
@Clock ;; READ DIO and SAVE 1-bit DATA in ad_out_h.2
mov tmp1 #0100b
@Read_DIO
caje #0 @f
mov a ad_out_h
or a tmp1
mov ad_out_h a
@@:
;;***************************************
@Clock ;; READ DIO and SAVE 1-bit DATA in ad_out_h.1
mov tmp1 #0010b
@Read_DIO
caje #0 @f
mov a ad_out_h
or a tmp1
mov ad_out_h a
@@:
;;***************************************
@Clock ;; READ DIO and SAVE 1-bit DATA in ad_out_h.0
mov tmp1 #0001b
@Read_DIO
caje #0 @f
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SNAD01B
8-CHANNEL 8-BIT ADC
mov a ad_out_h
or a tmp1
mov ad_out_h a
@@:
;;***************************************
@Clock ;; READ DIO and SAVE 1-bit DATA in ad_out_l.3
mov tmp1 #1000b
@Read_DIO
caje #0 @f
mov a ad_out_l
or a tmp1
mov ad_out_l a
@@:
;;***************************************
@Clock ;; READ DIO and SAVE 1-bit DATA in ad_out_l.2
mov tmp1 #0100b
@Read_DIO
caje #0 @f
mov a ad_out_l
or a tmp1
mov ad_out_l a
@@:
;;***************************************
@Clock ;; READ DIO and SAVE 1-bit DATA in ad_out_l.1
mov tmp1 #0010b
@Read_DIO
caje #0 @f
mov a ad_out_l
or a tmp1
mov ad_out_l a
@@:
;;***************************************
@Clock ;; READ DIO and SAVE 1-bit DATA in ad_out_l.0
mov tmp1 #0001b
@Read_DIO
caje #0 @f
mov a ad_out_l
or a tmp1
mov ad_out_l a
@@:
;;***************************************
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SNAD01B
8-CHANNEL 8-BIT ADC
@Clock
@OFF_START ;; SET START=1
endm
;;*****************************************************************
;; Read Digital Input: *
;; 8-bit Data Æ (port_h, port_l) *
;;*****************************************************************
@Read_Port macro
@P20_Out_mode ;; SWITCH P2 TO OUTPUT MODE
@ON_START ;; SET START=0
@Send_1 ;; SET COMMAND (101)
@Clock
@Send_0
@Clock
@Send_1
@Clock
@P20_In_mode ;; SWITCH P2.0 TO INPUT MODE
mov port_l #0
mov port_h #0
;;***************************************
@Clock ;; READ DIO and SAVE 1-bit DATA in port_h.3
mov tmp1 #1000b
@Read_DIO
caje #0 @f
mov a port_h
or a tmp1
mov port_h a
@@:
;;***************************************
@Clock ;; READ DIO and SAVE 1-bit DATA in port_h.2
mov tmp1 #0100b
@Read_DIO
caje #0 @f
mov a port_h
or a tmp1
mov port_h a
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SNAD01B
8-CHANNEL 8-BIT ADC
@@:
;;***************************************
@Clock ;; READ DIO and SAVE 1-bit DATA in port_h.1
mov tmp1 #0010b
@Read_DIO
caje #0 @f
mov a port_h
or a tmp1
mov port_h a
@@:
;;***************************************
@Clock ;; READ DIO and SAVE 1-bit DATA in port_h.0
mov tmp1 #0001b
@Read_DIO
caje #0 @f
mov a port_h
or a tmp1
mov port_h a
@@:
;;***************************************
@Clock ;; READ DIO and SAVE 1-bit DATA in port_l.3
mov tmp1 #1000b
@Read_DIO
caje #0 @f
mov a port_l
or a tmp1
mov port_l a
@@:
;;***************************************
@Clock ;; READ DIO and SAVE 1-bit DATA in port_l.2
mov tmp1 #0100b
@Read_DIO
caje #0 @f
mov a port_l
or a tmp1
mov port_l a
@@:
;;***************************************
@Clock ;; READ DIO and SAVE 1-bit DATA in port_l.1
mov tmp1 #0010b
@Read_DIO
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SNAD01B
8-CHANNEL 8-BIT ADC
caje #0 @f
mov a port_l
or a tmp1
mov port_l a
@@:
;;***************************************
@Clock ;; READ DIO and SAVE 1-bit DATA in port_l.0
mov tmp1 #0001b
@Read_DIO
caje #0 @f
mov a port_l
or a tmp1
mov port_l a
@@:
;;***************************************
@Clock
@OFF_START ;; SET START=1
endm
;;***************************************
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8-CHANNEL 8-BIT ADC
Program 1: Set Configuration of SNAD01B
;; Setup Configuration of SNAD01B
;;
;; With Pull-Low, Bandgap ON. (PH=0, PL=1, RF=0,MB=0)
;;
;; CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
;; Analog/Digital: B A A D D D A A :B, battery detect
;; Wakeup: X X X NO YES YES X X
;;
SNC520
program
include def.h
START:
mov a #1111b
mov p2s a
mov a #0000b
mov p2 a
mov p2State #0
@Set_Control_Reg #0, #1, #0, #0 ;; Set Control Registers
@Set_Attrib #0, #1, #1, #0, #0, #0, #1, #1 ;; Set Chan Analog/Digital
@Set_Wakeup #0, #0, #0, #0, #1, #1, #0, #0 ;; Setup Wakeup function
SNAD01B
Program 2: Read ADC result from Channel 1
;; Inherit from program 1
;; 8-bit ADC result of channel 1 in ( ad_out_h, ad_out_l)
@Read_ADC #0, #0, #1 ;;get ADC result from Ch1 in ( ad_out_h, ad_out_l)
…
…
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…
…
SNAD01B
8-CHANNEL 8-BIT ADC
Program 3: Read Digital Input data from Ch4, Ch3, CH2
;; Inherit from program 1
;; After Reading,
;; Port_h.0 = Input of Ch4
;; Port_l.3 = Input of Ch3
;; Port_l.2 = Input of Ch2
@Read_Port ;;get ADC result in ( ad_out_h, ad_out_l)
Program 4: Power-down SNAD01B and Host, and Wake-up
;; Inherit from program 1
;; Enter Power-down Mode (0)
@Power_Down_0 ;;SNAD01B enters power-down Mode (0)
end ;; HOST (SNC520) enter power-down
…
…
TRIGGER:
@OFF_START ;; SET START=1
…
@Read_Port ;; READ Trigger condition or Debounce Procedure starting from here
…
…
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SNAD01B
8-CHANNEL 8-BIT ADC
Program 5: Battery Low Detection
P22
P21
P20
VDD
SNAD01B
START
CLK
DIO
VDD
AVDD
REF
VSS
AVSS
CH[7]
SNC520
VDD
VSS
An application uses three 1.5V batteries for power supply. During operation, the
power of batteries keeps consumed and the voltage of battery keeps going down.
Now, voltage lower than 3.6V is treated as “Battery Low”. The ADC and bandgap
reference circuit in SNAD01B can be utilized to detect “Battery Low”.
The voltage through channel 7 to ADC is reduced to 1/6*VDD (Figure10). Thus, when
VDD=3.6V, the voltage into ADC is around 0.6V. And bandgap is chosen for
reference voltage (approximately 1.17V within the whole operation voltage range).
The value acquired from ADC is about (0.6/1.17)*256=131. For simplification
consideration, we choose “ADC’s readout < 128” as “Battery Low” condition.
;; Inherit from program 1
;; Enter Power-down Mode (0)
CheckBattery:
@Set_Control_Reg #0, #1, #1, #0 ;; Set rf=1, turn-on bandgap
@Set_Attrib #1, #1, #1, #0, #0, #0, #1, #1 ;; Switch Ch7 to Analog
mov m15 #0
CheckAgain:
@Read_ADC #1, #1, #1 ;; Read Ch7
mov a #1000b
and a ad_out_h
caje #1000b Battery_Low_No ;; if (Value>=128) then Not Battery Low
mov a m15
inca
mov m15 a
caje #3 Battery_Low_Yes ;; if (Value<128) for 3 times, then
jmp CheckAgain ;; battery low.
Battery_Low_Yes:
mov m14 #1
VDD
0.1uF
VDD
VDD
Battery:
1.5Vx3
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SNAD01B
8-CHANNEL 8-BIT ADC
Battery_Low_No:
@Set_Control_Reg #0, #1, #0, #0 ;; Set rf=0, turn-off bandgap
@Set_Attrib #0, #1, #1, #0, #0, #0, #1, #1 ;; Switch Ch7 to Digital
;; To save operating current
10. PAD DIAGRAM
Dice Form
NO PAD NAME X(um) Y(um) NO PAD NAME X(um) Y(um)
1 CH0 -623.50 352.50 9 VSS 623.50 -417.50
2 CH1 -623.50 242.50 10 VDD 623.50 -307.50
3 CH2 -623.50 132.50 11 DIO 623.50 -197.50
4 CH3 -623.50 22.50 12 CLK 623.50 -87.50
5 CH4 -623.50 -87.50 13 START 623.50 22.50
6 CH5 -623.50 -197.50 14 AVDD 623.50 132.50
7 CH6 -623.50 -307.50 15 VSS 623.50 242.50
8 CH7 -623.50 -417.50 16 REF 623.50 352.50
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
1
2
3
4
(0,0)
5
6
7
8
CHIP SIZE=1350 x 950um
SNAD01B
Note: The substrate MUST be connected to Vss in PCB layout
16
REF
15 AVSS
14
13
AVDD
START
12 CLK
11
10
DIO
VDD
9
VSS
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SNAD01B
8-CHANNEL 8-BIT ADC
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offerings available. Integrated circuits sold by SONiX are covered by the warranty and
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The application circuits illustrated in this document are for reference purposes only.
SONIX DISCLAIMS ALL WARRANTIES, INCLUDING THE WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SONIX reserves the right to
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Products listed at any time without notice. Accordingly, the reader is cautioned to verify
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Products described herein are intended for use in normal commercial applications.
Applications involving unusual environmental or reliability requirements, e.g. military
equipment or medical life support equipment, are specifically not recommended without
additional processing by SONIX for such application.
Version: 1.3 July 31, 2003
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