Page 1
SN75LVDS88
TFT LCD PANEL TIMING CONTROLLER
WITH LVDS INTERFACE
SLLS344 – OCTOBER 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Flatlink Interface Utilizes Low Power
Differential Signalling(LVDS)
D
Suitable for Notebook Application
D
XGA Resolution
D
Six Bit System Interface
D
Support Mainstream Data and Gate Drivers
D
Optional Configurable Pins
D
Low Voltage CMOS 3.3 V Technology
D
65 MHz Phase-Lock Input
D
100-pin TQFP Package for Compact LCD
Module
D
Tolerates 4 kV HBM ESD for LVDS Pins and
2 kV HBM for Others
D
Improved Jitter Tolerance
description
The SN75LVDS88 (LVDS panel timing controller) integrates a Flatlink signal interface with a TFT LCD timing
controller. It resides in the LCD panel and provides interface between the graphic controller and a TFT LCD
panel.
The SN75LVDS88 accepts host data through 3 pairs of inputs (18-bits) making up the LVDS bus, which is a
low-EMI high-throughput interface. SN75L VDS88 then reformats the received image data into a specific data
format and synchronous timing suitable for driving LCD panel column and row drivers. This device supports
XGA resolution.
The SN75LVDS88 is easily configured by several selection terminals and is equipped with default timing
specifications to support mainstream gate and source drivers on the market.
block diagram
Flat Link
(18-bit)
Timing
Signal
Generator
SYNC
Data Alignment
CTRL
Interface
Source
Data
Format
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Page 2
SN75LVDS88
TFT LCD PANEL TIMING CONTROLLER
WITH LVDS INTERFACE
SLLS344 – OCTOBER 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
pin assignment
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
TEST1
MODE1
MODE0
VSS
POLEN
VDDA
RSTZ
GNDANCCLKP
A2M
A1P
A1M
A0P
A0M
GNDD
SHTDN
VDDDNCNC
EG4
EG3
VDDIO
EG2
EG1
VSSIO
EG0
VDDIO
EB4(ER4)
VSSIO
EB2(ER2)
EB1(ER1)
VDDIO
EB0(ER0)
VSSIO
CLK
SP
VSSIO
OR4(OB4)
OR3(OB3)
EPOL
TQFP PACKAGE
(TOP VIEW)
CLKM
GND1
NC
EB5(ER5)
VDDIO
MODE2
TP1
CPV
VSS
STV
OE1
REV_E
VDD
REV_O
OE2
TP2
VSSIO
CLK
VDDIO
TEST2
ER5(EB5)
VSSIO
ER4(EB4)
ER3(EB3)
VDDIO
ER2(EB2)
ER1(EB1)
VSSIO
ER0(EB0)
EG5
VDD
OPOL
VSS
OB0(OR0)
VDD
OB1(OR1)
OB2(OR2)
VSSIO
OB3(OR3)
OB4(OR4)
VDDIO
OB5(OR5)
OG0
VSSIO
OG1
OG2
VDDIO
OG3
OG4
VSSIO
OG5
OR0(OB0)
VDDIO
OR1(OB1)
OR2(OB2)
EB3(ER3)
OR5(OB3)
DBS
A2P
SN75LVDS88
Page 3
SN75LVDS88
TFT LCD PANEL TIMING CONTROLLER
WITH LVDS INTERFACE
SLLS344 – OCTOBER 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
A0M/A0P 81,82 I Flatlink 1st data pair
A1M/A1P 83, 84 I Flatlink 2nd data pair
A2M/A2P 85, 86 I Flatlink 3rd data pair
CLK 44 O CD bus clock
CLK 13 O CD bus clock (180 degree out of phase)
CLKM/CLKP 87, 88 I Flatlink clock pair
CPV 3 O Gate driver clock
DBS 97 I Data bus sequence
EPOL 42 O Even RGB data stream polarity indicator
ER0..ER5
(EB0)..(EB5)
24,22,21
19,18,16
O Even red (blue) data bus, controlled by DBS Pin, 0 = red, 1 = blue
(ER0)..(ER5)
EB0..EB5
41,39,38
36,35,33
O Even blue (red) data bus, controlled by DBS Pin, 0 = blue, 1 = red
GND1 91 P PLL ground for LVDS
MODE0 98 I Default timing selection pin 0
MODE1 99 I Default timing selection pin 1
MODE2 1 I Default timing selection pin 2
NC 76, 77,
89, 90
NC NC terminals
†
OE1, OE2 6, 10 O Gate driver output enable
OG0..OG5 63,61,60
58,57,55
O Odd green data bus
OPOL 74 O Odd RGB data stream polarity indicator
OR0..OR5
(OB0)..(OB5)
54,52,51
50,49,47
O Odd red (blue) data bus, controlled by DBS Pin, 0 = red, 1 = blue
(OR0)..(OR5)
OB0..OB5
72,70,69
67,66,64
O Odd blue (red) data bus, controlled by DBS Pin, 0 = blue, 1 = red
POLEN 95 I Output data polarity control enable /disable
REV_E 7 O CD line/dot inversion control signal
REV_O 9 O CD line/dot inversion control signal (180 degree of phase)
RSTZ 93 I Reset, active low
SHTDN 79 I System shutdown control, active low
SP 46 O Data bus starting pulse
STV 5 O Gate driver starting pulse
TEST1, TEST2 100, 15 I T est points
†
TP1, TP2 2, 11 O CD output control signal
VDDA 94 P PLL power for LVDS
GNDA 92 P Analog ground for LVDS
VDDD 78 P Digital power supply for LVDS
GNDD 80 P Digital power ground for LVDS
VDD 8,71,75 P Digital power
VSS 4,73,96 P Digital ground
VDDIO P I/O power
VSSIO P I/O ground
†
Terminals must be connected to ground.
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SN75LVDS88
TFT LCD PANEL TIMING CONTROLLER
WITH LVDS INTERFACE
SLLS344 – OCTOBER 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
options
output control
INTERNAL CONNECTION
PIN NAME
PIN NO
.
REQUIRED SUGGESTED
DESCRIPTION
MODE0
MODE1
MODE2
98
99
1
Pull-up
Pull-up
Pull-down
Default timing selection pin 0
Default timing selection pin 1
Default timing selection pin 2
POLEN Pull-down 0 = Output data reverse disable
1 = Output data reverse enable
DBS 97 Pull-down Data bus sequence
0 = normal (RGB)
1 = reverse (BGR)
NOTE: DBS and POLEN functions must not be enabled together. The option pins must be connected to ground or VDD.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage range, V
CC
‡
–0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at any terminal –0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge: Class 3 A 4 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Class 2 B 200 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡
All voltage values are with respect to the GND terminals unless otherwise noted.
DISSIPATION RATING T ABLE
PACKAGE
TA ≤ 25°C
POWER RATING
OPERATING FACTOR
§
ABOVE TA = 25°C
TA = 70°C
POWER RATING
PFD 1.548 W 12 mW 1.012 W
§
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with
no air flow.
Page 5
SN75LVDS88
TFT LCD PANEL TIMING CONTROLLER
WITH LVDS INTERFACE
SLLS344 – OCTOBER 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
CC
3 3.3 3.6 V
High-level input voltage, V
IH
2
Low-level input voltage, V
IL
SHTDN
0.8
V
Magnitude of differential input voltage, VID 0.1 0.6 V
Common–mode input voltage, V
IC
|VID|
2
2.4 –
|VID|
2
V
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IT+
Positive-going differential input voltage threshold 100 mV
V
IT–
Negative-going differential input voltage threshold –100 mV
Disabled, all inputs to ground 360 µA
Enabled, AnP at 1 V and
AnM at 1.4 V, tC = 15.38 ns
80
I
CC
Quiescent current (average)
Enabled, CL = 8 pF,
Grayscale pattern , tC = 15.38 ns
100
mA
Enabled, CL = 8 pF,
Worst-case pattern , tC = 15.38 ns
120
I
IH
High-level input current (SHTDN) VIH = V
CC
±20 µA
I
IL
Low-level input current (SHTDN) VIL = 0 V ±20 µA
I
IN
Input current (A inputs) 0 V < VI < 2.4 V ±20 µA
I
OZ
High-impendance output current VO = 0 V or V
CC
±10 µA
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the negative-going
input voltage threshold only.
timing requirements
MIN TYP MAX UNIT
t
c
§
Input clock period 14.7 31.25 ns
tsu/t
h
Input set up or hold time 550 ps
§
tc is defined as the mean duration of a minimum of 32,000 clock periods.
output buffer rating
MIN TYP MAX UNIT
STV, SP 4 mA
CLK, CLK 12 mA
Data bus and remaining outputs 8 mA
Page 6
SN75LVDS88
TFT LCD PANEL TIMING CONTROLLER
WITH LVDS INTERFACE
SLLS344 – OCTOBER 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
dr1
Input clock rising to output clock rising delay
p
10 40 ns
t
df1
Input clock rising to output clock falling delay
C
L
=
100 pF
10 40 ns
t
su1
Data set up time, E/O RGB to CLK↑
p
10 20 ns
t
h1
Data hold time, CLK↑ to E/O RGB
C
L
=
100 pF
10 20 ns
t
(RSKM)
Receiver input skew margin, See Note 4
tc = 15.38 ns (+0.2%),
Input clock jitter < 50 ps, See Note 5
550 700 ps
t
en
Enable time, SHTDN to phase lock 1 ms
t
dis
Disable time, SHTDN to off state 250 ns
t
su2
SP setup time
p
10 20 ns
t
h2
SP pulse hold time
C
sp
= 15
pF
10 20 ns
NOTES: 1. t
RSKM
is the timing margin available to allocate to the transmitter and interconnection skews and clock jitter. The value of this
parameter at clock periods other than 15.38 ns can be calculated from
t
RSKM
+
t
c
14
–300 ps.
2. |Input clock jitter| is the magnitude of the change in the input clock period.
PARAMETER MEASUREMENT INFORMATION
CLKM/P
CLK
RGB
SP
t
dr1
t
h
t
h2
t
su2
t
dr1
t
su1
Figure 1. Output Setup and Hold Time
Page 7
SN75LVDS88
TFT LCD PANEL TIMING CONTROLLER
WITH LVDS INTERFACE
SLLS344 – OCTOBER 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
REFERENCE TIMING DIAGRAM
DE
E/OSP
O/ERGB
CPV
TP1
TP2
OE1
OE2
REV
Figure 2. Typical Output Waveform
Page 8
SN75LVDS88
TFT LCD PANEL TIMING CONTROLLER
WITH LVDS INTERFACE
SLLS344 – OCTOBER 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
functional description
Flatlink
The core of the Flatlink is TIs original 86A L VDS receiver which has three data channels for the 18-bit color plus
one clock channel.
data alignment
The data alignment block supports dual bus dual port column driver configuration. When interfacing a 2-port
column driver, the controller arranges pixels in odd and even order , then distributes them to odd and even buses
and each connects to either of the driver ports. Under this setup, the controller outputs one clock, one or two
data polarities (depends on driver), and one inverse ( support line inversion) signal to the drivers.
output formatting
The output formatting provides several functions to reduce EMI, noise, and timing delay arrangement. These
functions are controllable through some optional pins. See the registers and options section for reference.
D
Reverse Polarity Generation
When enable this function generates polarity indication signals. This occurs when the number of transitions
in the output data bus exceeds 18-bits compared to the previous output under normal polarity. The polarity
signal will be active and the output will be the opposite polarity to reduce transition
D
Line Inversion
When enabled, the REV_O and REV_E terminals will output the same line inversion control signals but in
opposite polaritys.
timing control
D
Source Shifted Clock( SSC)
The master data clock could be arranged to have an intentional phase delay relative to the output data,
which helps the system engineer tune the clock to latch the data correctly regardless of the characteristics
presented by the PCB and the layout.
D
Horizontal Starting pulses
ESP and OSP terminals are used as the horizontal starting pulses outputs pins. Their output are one HCLK
period ahead of the RGB data stream
D
Horizontal Clock
ECLK and OCLK terminals are responsible for the clock pulses, based on the XGA resolution when its
frequency is at 32.5 MHz.
D
CD Data Latch Pulse
TP1 and TP2 provide the column driver input latch and output enable signals.
D
Gate Driver Clock
The CPV terminal output the clock pulses to the gate drivers as the horizontal sync timing in its CRT counter
part.
D
Gate Driver Starting Pulse
The vertical starting pulse automatically generates at the start of every frame.
D
Gate Driver Output Enable
The OE1 and OE2 terminals provide the gate output enabale signals.
Page 9
SN75LVDS88
TFT LCD PANEL TIMING CONTROLLER
WITH LVDS INTERFACE
SLLS344 – OCTOBER 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
functional description (continued)
vertical/horizontal reference generator
This block provides vertical and horizontal reference points for timing control. Vsync, Hsync, and ENAB signals
along with the auto detection function determine when the video from the host is valid.
power-up procedure
Due to the uncertainty of registers and counters in the driver, SN75LVDS88 combines the input from both reset
and Vsync to blank the output and simultaneously resets the content of drivers (see Figure 3).
V
SYNC
RSTZ
OE
Figure 3. Reset Waveform
It is recommended that the following circuit be used to ensure the device is reset for more than 5 ms after power
up.
RSTZ
10 kΩ
4.7 µF
Page 10
SN75LVDS88
TFT LCD PANEL TIMING CONTROLLER
WITH LVDS INTERFACE
SLLS344 – OCTOBER 1999
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
SN75LVDS88
ERGB
SP
CLK
REV_E/O
ORGB
CD1 CD2CD3CD4
Figure 4. Application Block Diagram
CLK
SP
ORGB
ERGB
7135 911
8246 1012
Figure 5. Data Output Format
Page 11
SN75LVDS88
TFT LCD PANEL TIMING CONTROLLER
WITH LVDS INTERFACE
SLLS344 – OCTOBER 1999
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
PFD (S-PQFP-G100) PowerPAD PLASTIC QUAD FLATPACK (DIE DOWN)
0,13 NOM
50
26
Thermal Pad
(see Note D)
0,75
0,45
0,25
Seating Plane
4146930/A 12/97
Gage Plane
0,27
75
0,17
76
100
SQ
SQ
1
15,80
16,20
14,20
13,80
12,00 TYP
1,05
0,95
1,20 MAX
51
25
0,50
0,08
M
0,08
0°–7°
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. The package thermal performance may be enhanced by attaching an external heatsink to the thermal pad.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MS-026
PowerPAD is a trademark of Texas Instruments Incorporated.
Page 12
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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