Datasheet SN75LVDS83DGG, SN75LVDS83DGGR Datasheet (Texas Instruments)

SN75LVDS83

FLATLINK TRANSMITTER

SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

28:4 Data Channel Compression at up to

227.5 Million Bytes per Second Throughput

D

Suited for SVGA, XGA, or SXGA Display
Data Transmission From Controller to
Display With Very Low EMI

D

28 Data Channels and Clock-In Low-Voltage
TTL

D

4 Data Channels and Clock-Out
Low-Voltage Differential

D

Operates From a Single 3.3-V Supply With
250 mW (Typ)

D

ESD Protection Exceeds 6 kV

D

5-V Tolerant Data Inputs

D

Selectable Rising or Falling Edge-Triggered
Inputs

D

Packaged in Thin Shrink Small-Outline
Package With 20-Mil Terminal Pitch

D

Consumes Less Than 1 mW When Disabled

D

Wide Phase-Lock Input Frequency
Range . . . 31 MHz to 68 MHz

D

No External Components Required for PLL

D

Outputs Meet or Exceed the Requirements
of ANSI EIA/TIA-644 Standard

D

Improved Replacement for the DS90C581

description

The SN75LVDS83 FlatLink transmitter contains
four 7-bit parallel-load serial-out shift registers, a
7× clock synthesizer, and five low-voltage
differential-signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of
single-ended low-voltage TTL (L VTTL) data to be synchronously transmitted over five balanced-pair conductors
for receipt by a compatible receiver, such as the SN75LVDS82. The SN75LVDS83 can also be used in 21-bit
links with the SN75LVDS86 receiver.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock
signal (CLKIN). The rising or falling edge of the clock can be selected by way of the clock select (CLKSEL)
terminal. The frequency of CLKIN is multiplied seven times (7×) and then used to unload the data registers in
7-bit slices and serially . The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS
output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN75LVDS83 requires no external components and little or no control. The data bus appears the same
at the input to the transmitter and output of the receiver with the data transmission transparent to the user. The
only user intervention is the possible use of the shutdown/clear (SHTDN

) active-low input to inhibit the clock
and shut off the LVDS output drivers for lower power consumption. A low-level signal on SHTDN clears all
internal registers to a low level.

The SN75LVDS83 is characterized for operation over free-air temperature ranges of 0_C to 70_C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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26
27
28

56
55
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53
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51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

V

CC

D5
D6
D7

GND

D8
D9

D10

V

CC

D11
D12
D13

GND

D14
D15
D16

CLKSEL

D17
D18
D19

GND

D20
D21
D22
D23

V

CC

D24
D25

D4
D3
D2
GND
D1
D0
D27
LVDSGND
Y0M
Y0P
Y1M
Y1P
LVDSV

CC

LVDSGND
Y2M
Y2P
CLKOUTM
CLKOUTP
Y3M
Y3P
LVDSGND
PLLGND
PLLV

CC

PLLGND
SHTDN
CLKIN
D26
GND

DGG PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1999, Texas Instruments Incorporated

FlatLink is a registered trademark of Texas Instruments Incorporated.

SN75LVDS83
FLATLINK TRANSMITTER

SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

A,B, ...G
SHIFT/LOAD

CLK

Parallel-Load 7-Bit

Shift Register

7

A,B, ...G
SHIFT/LOAD

CLK

Parallel-Load 7-Bit

Shift Register

7

A,B, ...G
SHIFT/LOAD

CLK

Parallel-Load 7-Bit

Shift Register

7

A,B, ...G
SHIFT/LOAD

CLK

Parallel-Load 7-Bit

Shift Register

7

Control Logic

7×CLK

CLK

CLKINH

7× Clock/PLL

SHTDN

CLKIN

D5, D10, D11, D16,

D17, D23, D27

D19, D20, D21, D22,

D24, D25, D26

D8, D9, D12, D13,

D14, D15, D18

D0, D1, D2, D3,

D4, D6, D7

Y0P
Y0M

Y1P
Y1M

Y2P
Y2M

Y3P
Y3M

CLKOUTP
CLKOUTM

Input Bus

CLKSEL

RISING/FALLING EDGE

SN75LVDS83

FLATLINK TRANSMITTER

SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999

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CLKOUT

CLKIN

or

CLKIN

D0

Y0

Y1

Y2

Y3

D0–1 D7 D6 D4 D3 D2 D1 D0 D7+1

D8–1 D18 D15 D14 D13 D12 D9 D8 D18+1

D19–1 D26 D25 D24 D22 D21 D20 D19 D26+1

D27–1 D23 D17 D16 D11 D10 D5 D27 D23+1

ÉÉÉ

Current Cycle

Next
Cycle

Previous Cycle

Figure 1. SN75LVDS83 Load and Shift Timing Sequences

equivalent input and output schematic diagrams

V

CC

50 Ω

300 kΩ

7 V

Dn or

SHTDN

V

CC

7 V

10 kΩ

5 Ω

YnP or YnM

INPUT OUTPUT

SN75LVDS83
FLATLINK TRANSMITTER

SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range, VCC (see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

O

(all terminals) –0.5 V to V

CC

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

(all terminals) –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to the GND terminals.

DISSIPATION RATING T ABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

‡

ABOVE TA = 25°C

TA = 70°C

POWER RATING

DGG 1377 mW 11.0 mW/°C 822 mW

‡

This is the inverse of the junction-to-ambient thermal resistance when board mounted and
with no air flow.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

CC

3 3.3 3.6 V

High-level input voltage, V

IH

2 V

Low-level input voltage, V

IL

0.8 V

Differential load impedance, Z

L

90 132 Ω

Operating free-air temperature, T

A

0 70 °C

timing requirements

MIN NOM MAX UNIT

t

c

Cycle time, input clock 14.7 32.4 ns

t

w

Pulse duration, high-level input clock 0.4t

c

0.6t

c

ns

t

t

Transition time, input signal 5 ns

t

su

Setup time, data, D0 – D27 valid before CLKIN↑ or CLKIN↓ (See Figure 2) 3 ns

t

h

Hold time, data, D0 – D27 valid after CLKIN↑ or CLKIN↓ (See Figure 2) 1.5 ns

SN75LVDS83

FLATLINK TRANSMITTER

SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IT

Input threshold voltage 1.4 V

|VOD| Differential steady-state output voltage magnitude

247 454 mV

∆|VOD|

Change in the steady-state differential output
voltage magnitude between opposite binary states

R

L

=

100 Ω

,

See Figure 3

50 mV

V

OC(SS)

Steady-state common-mode output voltage

1.125 1.375 V

V

OC(PP)

Peak-to-peak common-mode output voltage

See Figure 3

150 mV

I

IH

High-level input current VIH = V

CC

25 µA

I

IL

Low-level input current VIL = 0 ±10 µA

p

V

O(Yn)

= 0 ±24 mA

IOSShort-circuit output current

VOD = 0 ±12 mA

I

OZ

High-impedance state output current VO = 0 to V

CC

±10 µA

Disabled,
All inputs at GND

280 µA

I

CC

Quiescent supply current

Enabled,
RL = 100 Ω,
Gray-scale pattern (see Figure 4),
VCC = 3.3 V,
tc = 15.38 ns

72 90 mA

Enabled,
RL = 100 Ω,
Worst-case pattern (see Figure 5),
tc = 15.38 ns

85 110 mA

C

I

Input capacitance 3 pF

†

All typical values are at VCC = 3.3 V, TA = 25°C.

SN75LVDS83
FLATLINK TRANSMITTER

SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

†

MAX UNIT

t

d0

Delay time, CLKOUT↑ to serial bit
position 0

–0.2 0 0.2 ns

t

d1

Delay time, CLKOUT↑ to serial bit
position 1

1
7

tc*

0.2

1
7

tc)

0.2

ns

t

d2

Delay time, CLKOUT↑ to serial bit
position 2

2
7

tc*

0.2

2
7

tc)

0.2

ns

t

d3

Delay time, CLKOUT↑ to serial bit
position 3

tc = 15.38 ns (± 0.2%),
|Input clock jitter| < 50 ps‡,

3
7

tc*

0.2

3
7

tc)

0.2

ns

t

d4

Delay time, CLKOUT↑ to serial bit
position 4

See Figure 6

4
7

tc*

0.2

4
7

tc)

0.2

ns

t

d5

Delay time, CLKOUT↑ to serial bit
position 5

5
7

tc*

0.2

5
7

tc)

0.2

ns

t

d6

Delay time, CLKOUT↑ to serial bit
position 6

6
7

tc*

0.2

6
7

tc)

0.2

ns

t

sk(o)

Output skew,

tn*

n
7

t

c

–0.2 0.2 ns

t

d7

Delay time, CLKIN↓ to CLKOUT↑

tc = 15.38 ns (± 0.2%),
|Input clock jitter| < 50 ps‡,
See Figure 6

4.2 ns

tc = 15.38 ± 0.75 sin (2π500E3t) + 0.05 ns,
See Figure 7

±70 ps

∆t

c(o)

Cycl

e time, output clock jitter

§

tc = 15.38 ± 0.75 sin (2π3E6t) + 0.05 ns,
See Figure 7

±187 ps

t

w

Pulse duration, high-level output clock

4
7

t

c

ns

t

t

Transition time, differential output
(tr or tf)

See Figure 3 260 700 1500 ps

t

en

Enable time, SHTDN↑ to phase lock (Yn
valid)

See Figure 8 1 ms

t

dis

Disable time, SHTDN↓ to off state
(CLKOUT low)

See Figure 9 250 ns

†

All typical values are at VCC = 3.3 V, TA = 25°C.

‡

|Input clock jitter| is the magnitude of the change in the input clock period.

§

Output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 15000 cycles.

SN75LVDS83

FLATLINK TRANSMITTER

SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

Dn

t

su

CLKIN

t

h

CLKSEL LOW
CLKSEL HIGH

NOTE A: All input timing is defined at 1.4 V on an input signal with a 10%-to-90% rise or fall time of less than 5 ns.

Figure 2. Setup and Hold Time Waveforms

CL = 10 pF Max
(2 Places)

49.9 Ω ± 1% (2 Places)

V

OC

V

OD

YP

YM

V

OD(H)

V

OC(SS)

V

OC(SS)

V

OD(L)

100%
80%

20%
0%

0 V

V

OC(PP)

t

r

t

f

0 V

(a) SCHEMATIC

(b) WAVEFORMS

NOTE A: The lumped instrumentation capacitance for any

single-ended voltage measurement is less than or equal
to 10 pF . When making measurements at YP or YM, the
complementary output is similarly loaded.

Figure 3. Test Load and Voltage Waveforms for LVDS Outputs

SN75LVDS83
FLATLINK TRANSMITTER

SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

CLKIN

D0, 8, 16

D1, 9, 17

D2, 10, 18

D3, 11, 19

D4–7, 12–15, 20–23

D24–27

NOTE A: The 16-grayscale test-pattern test device power consumption for a typical display pattern. Pattern with CLKSEL low shown.

Figure 4. 16-Grayscale Test-Pattern Waveforms

t

c

NOTE A: The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs. Pattern with

CLKSEL low shown.

CLKIN

Even Dn

Odd Dn

Figure 5. Worst-Case Test-Pattern Waveforms

SN75LVDS83

FLATLINK TRANSMITTER

SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

Yn

V

OD(H)

V

OD(L)

0.00 V

td0 – t

d6

t

d2

t

d3

t

d4

t

d5

t

d6

t

d7

CLKOUT

CLKIN

(see Note B)

t

d1

t

d0

≈ 0.5 V

1.4 V

t

d7

CLKIN

≈ 2.5 V

CLKOUT

or

Yn

CLKIN

(see Note A)

NOTES: A. This wave form is valid when CLKSEL is low.

B. This wave form is valid when CLKSEL is high.

Figure 6. SN75LVDS83 Timing Waveforms

SN75LVDS83
FLATLINK TRANSMITTER

SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

Reference

VCO

Device

Under

Test

Modulation

∑

+

+

V(t) = A sin (2 π f

(mod)

t)

HP8656B

Signal Generator

0.1 MHz – 990 MHz

HP8665A

Synthesized Signal

Generator

0.1 MHz – 4200 MHz

RF Output Modulation Input

Device Under Test DTS2070C

Digital Time Scope

OUTPUT

CLKIN CLKOUT Input

Figure 7. Output Clock Jitter Testing

CLKIN

t

en

SHTDN

Dn

Yn

ValidInvalid

Figure 8. Enable Time Waveforms

CLKIN

CLKOUT

t

dis

SHTDN

Figure 9. Disable Time Waveforms

SN75LVDS83

FLATLINK TRANSMITTER

SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

AVERAGE SUPPLY CURRENT

vs

CLOCK FREQUENCY

80

70

60

50

40

30

30 40 50 60 70

f

clk

– Clock Frequency – MHz

Grayscale Data Pattern
RL = 100 Ω
TA = 25°C

VCC = 3.6 V

VCC = 3.3 V

– Average Supply Current – mA

I

CC

VCC = 3 V

Figure 10

60

40

0

0 0.5 1 1.5

Zero-to-Peak Output Jitter – ps

200

ZERO-TO-PEAK OUTPUT JITTER

vs

MODULATION FREQUENCY

2 2.5 3

100

f

(mod)

– Modulation Frequency – MHz

Input jitter = 750 sin (6.28 f

(mod)

t) ps
VCC = 3.3 V
TA = 25°C

20

80

120

140

160

180

Figure 11

SN75LVDS83
FLATLINK TRANSMITTER

SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

RED0 RED0 RED0
RED1 RED1 RED1
RED2 RED2 RED2
RED3 RED3 RED3
RSVD RED4 RED4
RSVD RED5 RED5
NA NA RED6
NA NA RED7
GREEN0 GREEN0 GREEN0
GREEN1 GREEN1 GREEN1
GREEN2 GREEN2 GREEN2
GREEN3 GREEN3 GREEN3
RSVD GREEN4 GREEN4
RSVD GREEN5 GREEN5
NA NA GREEN6
NA NA GREEN7
BLUE0 BLUE0 BLUE0
BLUE1 BLUE1 BLUE1
BLUE2 BLUE2 BLUE2
BLUE3 BLUE3 BLUE3
RSVD BLUE4 BLUE4
RSVD BLUE5 BLUE5
NA NA BLUE6
NA NA BLUE7
H_SYNC H_SYNC H_SYNC
V_SYNC V_SYNC V_SYNC
ENABLE ENABLE ENABLE
NA NA RSVD
CLOCK CLOCK CLOCK

12-BIT

18-BIT 24-BIT

Graphic Controller

SN75LVDS83 SN75LVDS82

D0
D1
D2
D3
D4
D6
D27
D5
D7
D8
D9
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
CLKSEL

51
52
54
55
56

3

50

2
4
6
7

11
12
14

8
10
15
19
20
22
23
24
16
18
27
28
30
25
31
17

100 Ω

9

10

48

47

100 Ω

11

12

46

45

100 Ω

15

16

42

41

100 Ω

19

20

38

37

100 Ω

17

18

40

39

Cable Flat Panel DisplayHost

A0M

A0P

A1M

A1P

A2M

A2P

A3M

A3P

CLKINM

CLKINP

Y0M

Y0P

Y1M

Y1P

Y2M

Y2P

Y3M

Y3P

CLKOUTM

CLKOUTP

See Note A

NOTES: A. Connect this terminal to VCC for triggering to the rising edge of the input clock and to GND for the falling edge.

B. The five 100-Ω terminating resistors are recommended to be 0603 types.

Figure 12. 24-Bit Color Host To 24-Bit LCD Panel Display Application

SN75LVDS83

FLATLINK TRANSMITTER

SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

RED0 RED0 RED0
RED1 RED1 RED1
RED2 RED2 RED2
RED3 RED3 RED3
RSVD RED4 RED4
RSVD RED5 RED5
NA NA RED6
NA NA RED7
GREEN0 GREEN0 GREEN0
GREEN1 GREEN1 GREEN1
GREEN2 GREEN2 GREEN2
GREEN3 GREEN3 GREEN3
RSVD GREEN4 GREEN4
RSVD GREEN5 GREEN5
NA NA GREEN6
NA NA GREEN7
BLUE0 BLUE0 BLUE0
BLUE1 BLUE1 BLUE1
BLUE2 BLUE2 BLUE2
BLUE3 BLUE3 BLUE3
RSVD BLUE4 BLUE4
RSVD BLUE5 BLUE5
NA NA BLUE6
NA NA BLUE7
H_SYNC H_SYNC H_SYNC
V_SYNC V_SYNC V_SYNC
ENABLE ENABLE ENABLE
NA NA RSVD
CLOCK CLOCK CLOCK

12-BIT

18-BIT 24-BIT

Graphic Controller

SN75LVDS83 SN75LVDS86

D0
D1
D2
D3
D4
D6
D27
D5
D7
D8
D9
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
CLKSEL

51
52
54
55
56

3

50

2
4
6

7
11
12
14

8
10
15
19
20
22
23
24
16
18
27
28
30
25
31
17

100 Ω

8

9

48

47

100 Ω

10

11

46

45

100 Ω

14

15

42

41

38

37

100 Ω

16

17

40

39

Cable Flat Panel DisplayHost

A0M

A0P

A1M

A1P

A2M

A2P

CLKINM

CLKINP

Y0M

Y0P

Y1M

Y1P

Y2M

Y2P

Y3M

Y3P

CLKOUTM

CLKOUTP

See Note A

NOTES: A. Connect this terminal to VCC for triggering to the rising edge of the input clock and to GND for the falling edge.

B. The four 100-Ω terminating resistors are recommended to be 0603 types.

Figure 13. 24-Bit Color Host To 18-Bit LCD Panel Display Application

SN75LVDS83
FLATLINK TRANSMITTER

SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL INFORMATION

DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

4040078/F 12/97

48 PIN SHOWN

0,25

0,15 NOM

Gage Plane

6,00

6,20

8,30
7,90

0,75
0,50

Seating Plane

25

0,27
0,17

24

A

48

1

1,20 MAX

M

0,08

0,10

0,50

0°–8°

56

14,10

13,90

48

DIM

A MAX

A MIN

PINS **

12,40

12,60

64

17,10

16,90

0,15
0,05

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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