Datasheet SN75LBC176, SN75LBC176D Specification





SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176

DIFFERENTIAL BUS TRANSCEIVERS



SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010

D Bidirectional Transceiver

D Meets or Exceeds the Requirements of

ANSI Standard TIA/EIA−485−A and
ISO 8482:1987(E)

D High-Speed Low-Power LinBiCMOS™

Circuitry

D Designed for High-Speed Operation in Both

Serial and Parallel Applications

D Low Skew

D Designed for Multipoint Transmission on

Long Bus Lines in Noisy Environments

D Very Low Disabled Supply Current ...200

μA Maximum

D Wide Positive and Negative Input/Output

Bus Voltage Ranges

D Thermal-Shutdown Protection

D Driver Positive-and Negative-Current

Limiting

D Open-Circuit Failsafe Receiver Design

D Receiver Input Sensitivity . . . ±200 mV Max

D Receiver Input Hysteresis . . . 50 mV Typ

D Operates From a Single 5-V Supply

D Glitch-Free Power-Up and Power-Down

Protection

D Available in Q-Temp Automotive

HighRel Automotive Applications
Configuration Control / Print Support
Qualification to Automotive Standards

description

D, JG, OR P PACKAGE

(TOP VIEW)

R

1

RE

2

DE

3

D

4

FK PACKAGE

(TOP VIEW)

NCRNC

NC
RE
NC
DE
NC

3212019

4
5
6
7
8

910111213

NCDNC

NC−No internal connection

V

GND

Function Tables

DRIVER

INPUT

D

H

L

X

ENABLE

DE

H
H

L

8
7
6
5

CC

V

CC

B
A
GND

NC

18
17
16
15
14

NC

OUTPUTS

A B

H L
L H
Z Z

NC
B
NC
A
NC

The SN55LBC176, SN65LBC176,
SN65LBC176Q, and SN75LBC176 differential
bus transceivers are monolithic, integrated
circuits designed for bidirectional data communi­cation on multipoint bus-transmission lines. They
are designed for balanced transmission lines and
meet ANSI Standard TIA/EIA−485−A (RS-485)
and ISO 8482:1987(E).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

LinBiCMOS and LinASIC are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DIFFERENTIAL INPUTS

VID = VIA−V

VID ≥ 0.2 V

−0.2 V < VID < 0.2 V
VID ≤ − 0.2 V

X

Open

H = high level,
X = irrelevant,

L =

low level,

Z =

high impedance (off)

Copyright © 2000−2006, Texas Instruments Incorporated

RECEIVER

ENABLE

IB

? =

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

RE

L
L
L
H
L

indeterminate,

OUTPUT

R

H

?

L

Z

H

1

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176
DIFFERENTIAL BUS TRANSCEIVERS


SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010

description (continued)

The SN55LBC176, SN65LBC176, SN65LBC176Q, and SN75LBC176 combine a 3-state, differential line driver
and a differential input line receiver, both of which operate from a single 5-V power supply. The driver and
receiver have active-high and active-low enables, respectively, which can externally connect together to
function as a direction control. The driver differential outputs and the receiver differential inputs connect
internally to form a differential input/output (I/O) bus port that is designed to offer minimum loading to the bus
whenever the driver is disabled or VCC = 0. This port features wide positive and negative common-mode voltage
ranges, making the device suitable for party-line applications. Very low device supply current can be achieved
by disabling the driver and the receiver.

These transceivers are suitable for ANSI Standard TIA/EIA−485 (RS-485) and ISO 8482 applications to the
extent that they are specified in the operating conditions and characteristics section of this data sheet. Certain
limits contained in TIA/EIA−485−A and ISO 8482:1987 (E) are not met or cannot be tested over the entire military
temperature range.

The SN55LBC176 is characterized for operation from − 55°C to 125°C. The SN65LBC176 is characterized for
operation from −40°C to 85°C, and the SN65LBC176Q is characterized for operation from −40°C to 125°C.
The SN75LBC176 is characterized for operation from 0°C to 70°C.



logic symbol

3

DE

2

RE

4

D

1

R

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.

†

EN1

EN2

2

−40°C to 125°C

−55°C to 125°C

1

1

T

A

0°C to 70°C

−40°C to 85°C

6

A

7

B

PACKAGE PART NUMBER PART MARKING

SOP SN75LBC176D 7LB176

PDIP SN75LBC176P 75LBC176

SOP SN65LBC176D 6LB176

PDIP SN65LBC176P 65LBC176

SOP SN65LBC176QD LB176Q

SOP SN65LBC176QDR LB176Q

LCCC SNJ55LBC176FK SNJ55LBC176FK

CDIP SNJ55LBC176JG SNJ55LBC176

logic diagram (positive logic)

AVAILABLE OPTIONS

DE

RE

3

4

D

2

6

1

R

A

7

Bus

B

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265



schematics of inputs and outputs

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176

DIFFERENTIAL BUS TRANSCEIVERS



SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010

EQUIVALENT OF D, RE, and

DE INPUTS

Input

absolute maximum ratings

TYPICAL OF A AND B I/O PORTS

V

CC

V

CC

100 kΩ NOM
A Port Only

A or B

18 kΩ
NOM

100 kΩ NOM
B Port Only

3 kΩ
NOM

1.1 kΩ
NOM

†

TYPICAL OF RECEIVER OUTPUT

V

CC

Output

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range at any bus terminal −10 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage, VI (D, DE, R, or RE) −0.3 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receiver output current, IO $10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values, except differential I/O bus voltage, are with respect to network ground terminal.

−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

DISSIPATION RATING TABLE

PACKAGE

D

P 840 mW 8.0 mW/°C 480 mW 360 mW —

JG 1050 mW 8.4 mW/°C 672 mW 546 mW 210 mW

FK 1375 mW 11.0 mW/°C 880 mW 715 mW 440 mW

†

In accordance with the low effective thermal conductivity metric definitions of EIA/JESD 51−3.

‡

In accordance with the high effective thermal conductivity metric definitions of EIA/JESD 51−7.

THERMAL

MODEL

†

Low K

‡

High K

TA < 25°C

POWER RATING

526 mW 5.0 mW/°C 301 mW 226 mW —

882 mW 8.4 mW/°C 504 mW 378 mW —

DERATING FACTOR

ABOVE TA = 25°C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

TA = 110°C

POWER RATING

3

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176
DIFFERENTIAL BUS TRANSCEIVERS


SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

Voltage at any bus terminal (separately or common mode), VI or V

High-level input voltage, V

Low-level input voltage, V

Differential input voltage, VID (see Note 2) −12 12 V

High-level output current, I

Low-level output current, I

Junction temperature, T

Operating free-air temperature, T

NOTE 2: Differential input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.

CC

IC

IH

IL

OH

OL

J

A

D, DE, and RE 2 V

D, DE, and RE 0.8 V

Driver −60 mA

Receiver −400 μA

Driver 60

Receiver 8

SN55LBC176 −55 125

SN65LBC176 −40 85

SN65LBC176Q −40 125

SN75LBC176 0 70

4.75 5 5.25 V

−7 12 V

140 °C



mA

°C

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265



,

,

,

55LBC176

RL = 54 Ω

See Figure 1

65LBC176

1.1

See Note 3

See Note 3

RL 54 Ω or 100 Ω,

See Figure 1
Output disabled

Receiver disabled

VI = 0 or V

CC

Receiver and driver

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176

DIFFERENTIAL BUS TRANSCEIVERS



SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010

DRIVER SECTION

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

V

IK

V

O

| V

OD1

| V

OD2

V

OD3

Δ| VOD |

V

OC

Δ| VOC |

I

O

I

IH

I

IL

I

OS

I

CC

†

Δ | VOD | and Δ | VOC | are the changes in magnitude of VOD and VOC, respectively, that occur when the input changes from a high level to a
low level.

NOTES: 3. This device meets the VOD requirements of TIA/EIA−485−A above 0°C only.

Input clamp voltage II = − 18 mA −1.5 V

Output voltage IO = 0 0 6 V

| Differential output voltage IO = 0 1.5 6 V

55LBC176

R

= 54 Ω

| Differential output voltage

Differential output voltage

Change in magnitude of differential
output voltage

Common-mode output voltage

Change in magnitude of
common-mode output voltage

Output current

High-level input current VI = 2.4 V −100 μA

Low-level input current VI = 0.4 V −100 μA

Short-circuit output current

Supply current

4. This applies for both power on and off; refer to TIA/EIA−485−A for exact conditions.

†

See Note 3

V
See Note 3

RL = 54 Ω or 100 Ω, See Figure 1

†

Output disabled,
See Note 4

VO = − 7 V −250

VO = 0 −150

VO = V

VO = 12 V

VI = 0 or VCC,
No load

,

= − 7 V to 12 V,

test

CC

,

,

See Figure 1

See Figure 2,

VO = 12 V 1

VO = − 7 V −0.8

Receiver disabled
and driver enabled

Receiver and driver
disabled

,

65LBC176,
65LBC176Q

75LBC176 1.5 5

55LCB176,
65LCB176,
65LBC176Q

75LBC176 1.5 5

55LBC176,
65LBC176Q

65LBC176,
75LBC176

55LBC176,
65LBC176Q

65LBC176,
75LBC176

,
,

1.1

1.1

−0.2 0.2 V

−1 3 V

−0.2 0.2 V

mA

mA

250

1.75

1.5
mA

0.25

0.2

V

V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176

PARAMETER

TEST CONDITIONS

UNIT

See Fi

3


DIFFERENTIAL BUS TRANSCEIVERS


SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature

PARAMETER TEST CONDITIONS

t

d(OD)

t

t(OD)

t

sk(p)

t

PZH

t

PZL

t

PHZ

t

PLZ

†

All typical values are at VCC = 5 V, TA = 25°C.

Differential output delay time

Differential output transition time

Pulse skew (| t

d(ODH)

− t

d(ODL)

Output enable time to high level RL = 110 Ω, See Figure 4 65 35 ns

Output enable time to low level RL = 110 Ω, See Figure 5 65 35 ns

Output disable time from high level RL = 110 Ω, See Figure 4 105 60 ns

Output disable time from low level RL = 110 Ω, See Figure 5 105 35 ns

DATA SHEET PARAMETER RS-485

RL = 54 Ω,

CL = 50 pF,

gure

|)

SYMBOL EQUIVALENTS

V

O

| V

| V

OD1

| V

| Vt (RL = 54 Ω)

OD2

| V

|

OD3

Δ | VOD | || Vt | − | Vt ||

V

OC

Δ | VOC | | Vos − Vos |

I

OS

I

O

SN55LBC176

SN65LBC176Q

MIN TYP MAX MIN TYP†MAX

8 31 8 25 ns

12 12 ns

Voa, V

ob

o

Vt (test termination

measurement 2)

| Vos |

None

Iia, I

ib

SN65LBC176
SN75LBC176

UNIT

6 0 6 ns

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265



O

VID = 200 mV

IOH = 400 μA

O

VID = 200 mV

IOL = 8 mA

Other input = 0 V

CC

ICCSupply current

driver disabled

PARAMETER

TEST CONDITIONS

UNIT

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176

DIFFERENTIAL BUS TRANSCEIVERS



SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010

RECEIVER SECTION

electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN

Positive-going input threshold

V

IT +

voltage

Negative-going input threshold

V

IT −

voltage

Hysteresis voltage (V

V

hys

(see Figure 4)

V

Enable-input clamp voltage II = − 18 mA −1.5 V

IK

V

High-level output voltage

OH

V

Low-level output voltage

OL

High-impedance-state output

I

OZ

current

I

Line input current

I

I

High-level enable-input current VIH = 2.7 V −100 μA

IH

I

Low-level enable-input current VIL = 0.4 V −100 μA

IL

r

Input resistance 12 kΩ

I

IT +

− V

IT −

VO = 2.7 V, IO = − 0.4 mA 0.2 V

VO = 0.5 V, IO = 8 mA −0.2

)

VID = 200 mV, I

,

See Figure 6

VID = −200 mV, I

,

= − 400 μA,

H

= 8 mA,

L

,

,

2.7 V

See Figure 6

VO = 0.4 V to 2.4 V −20 20 μA

Other input = 0 V,
See Note 5

VI = 12 V 1

,

VI = − 7 V −0.8

Receiver enabled
and driver disabled

I

Supply current

VI = 0 or VCC,
No load

Receiver and
driver disabled

SN55LBC176,
SN65LBC176,
SN65LBC176Q

SN75LBC176 0.2

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet.

NOTE 5: This applies for both power on and power off. Refer to ANSI Standard RS-485 for exact conditions.

†

TYP

‡

50 mV

MAX UNIT

V

0.45 V

mA

3.9 mA

0.25
mA

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

†

= 15 pF

L

PARAMETER TEST CONDITIONS

Propagation delay time, low- to high-level

t

PLH

single-ended output

Propagation delay time, high- to low-level

t

PHL

single-ended output

t

Pulse skew (| t

sk(p)

t

Output enable time to high level

PZH

t

Output enable time to low level

PZL

t

Output disable time from high level

PHZ

t

Output disable time from low level

PLZ

PLH

− t

|) 10 3 6 ns

PHL

All typical values are at VCC = 5 V, TA = 25°C.

SN65LBC176Q

VID = − 1.5 V to 1.5 V,
See Figure 7

See Figure 8

See Figure 8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN55LBC176

SN65LBC176
SN75LBC176

MIN MAX MIN TYP†MAX

11 37 11 33 ns

11 37 11 33 ns

35 35 ns

35 30 ns

35 35 ns

35 30 ns

UNIT

7

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176
DIFFERENTIAL BUS TRANSCEIVERS


SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010

PARAMETER MEASUREMENT INFORMATION

R

L

V

OD2

2

R

L

V

OC

2

V

OD3

375 Ω

60 Ω

375 Ω



V

test

Figure 1. Driver VOD and V

Generator

(see Note A)

0 V or 3 V

Generator

(see Note A)

50 Ω

50 Ω

Figure 2. Driver V

Input

t

d(ODH)

Output

3 V

OC

RL = 54 Ω

C

= 50 pF

L

(see Note B)

Output

t

TEST CIRCUIT

Figure 3. Driver Test Circuit and Voltage Waveforms

Output

Input

Output

C

= 50 pF

L

(see Note B)

TEST CIRCUIT

S1

R

L

= 110 Ω

OD3

1.5 V

50%

90%

10%

t(OD)

VOLTAGE WAVEFORMS

1.5 V

1.5 V

t

PZH

2.3 V
t

PHZ

VOLTAGE WAVEFORMS

1.5 V

3 V

0 V

t

d(ODL)

≈ 2.5 V

50%

≈ − 2.5 V

t

t(OD)

3 V

0 V

0.5 V

V

OH

V

≈ 0 V

off

Figure 4. Driver Test Circuit and Voltage Waveforms

3 V or 0 V

Generator

(see Note A)

50 Ω

C

= 50 pF

L

(see Note B)

TEST CIRCUIT

S1

5 V

R

L

= 110 Ω

Output

Input

t

Output

PZL

1.5 V

1.5 V

2.3 V

VOLTAGE WAVEFORMS

t

PLZ

3 V

0 V

5 V

0.5 V

V

OL

Figure 5. Driver Test Circuit and Voltage Waveforms

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,

8

ZO=50Ω.

B. CL includes probe and jig capacitance.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265



SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176

DIFFERENTIAL BUS TRANSCEIVERS

SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010

PARAMETER MEASUREMENT INFORMATION

V

ID

V

OL

+I

OL

V

OH

−I

OH



Figure 6. Receiver VOH and V

Generator

(see Note A)

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,

ZO=50Ω.

B. CL includes probe and jig capacitance.

51 Ω

1.5 V

0 V

TEST CIRCUIT

Output

CL = 15 pF

(see Note B)

OL

Input

Output

1.5 V

t

PLH

1.3 V

VOLTAGE WAVEFORMS

1.5 V

t

PHL

1.3 V

3 V

0 V

V

V

OH

OL

Figure 7. Receiver Test Circuit and Voltage Waveforms

THERMAL CHARACTERISTICS − D PACKAGE

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Low-K board, no air flow 199.4

Junction−to−ambient thermal reisistance, θ

Junction−to−board thermal reisistance, θ

Junction−to−case thermal reisistance, θ

Average power dissipation, P

Thermal shutdown junction temperature, T

†

See TI application note literature number SZZA003, Package Thermal Characterization Methodologies, for an explanation of this parameter.

(AVG)

†

JA

High-K board, no air flow 119

SD

High-K board, no air flow 67

46.6

RL = 54 Ω, input to D is 10 Mbps 50% duty
cycle square wave, VCC = 5.25 V,
TJ = 130 °C.

165 °C

330 mW

JB

JC

°C/W

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176
DIFFERENTIAL BUS TRANSCEIVERS


SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010

PARAMETER MEASUREMENT INFORMATION



Input

Output

1.5 V

−1.5 V

Generator

(see Note A)

t

PZH

S1

50 Ω

1.5 V

1.5 V

3 V

S1 to 1.5 V
S2 Open

S3 Closed

0 V

V

OH

0 V

CL = 15 pF
(see Note B)

TEST CIRCUIT

Input

Output

5 kΩ

2 kΩ

1N916 or Equivalent

S3

t

PZL

S2

1.5 V

1.5 V

5 V

3 V

S1 to −1.5 V
S2 Closed
S3 Opened

0 V

≈ 4.5 V

V

OL

Input

Output

t

PHZ

0.5 V

1.5 V

3 V

S1 to 1.5 V
S2 Closed
S3 Closed S3 Closed

0 V

V

OH

≈ 1.3 V

VOLTAGE WAVEFORMS

Input

Output

t

1.5 V

PLZ

0.5 V

3 V

S1 to −1.5 V
S2 Closed

0 V

≈ 1.3 V

V

OL

Figure 8. Receiver Test Circuit and Voltage Waveforms

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,

ZO=50Ω.

B. CL includes probe and jig capacitance.

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265



SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176

DIFFERENTIAL BUS TRANSCEIVERS



SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010

THERMAL CHARACTERISTICS OF IC PACKAGES

ΘJA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient temperature

divided by the operating power

Θ

is NOT a constant and is a strong function of

JA

D the PCB design (50% variation)

D altitude (20% variation)

D device power (5% variation)

can be used to compare the thermal performance of packages if the specific test conditions are defined and used.

Θ

JA

Standardized testing includes specification of PCB construction, test chamber volume, sensor locations, and the thermal
characteristics of holding fixtures.
installations.

TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition thermal
performance and consists of a single trace layer 25 mm long and 2-oz thick copper. The high-k board gives best case in−use
condition and consists of two 1-oz buried power planes with a single trace layer 25 mm long with 2-oz thick copper. A 4%
to 50% difference in Θ

Θ

(Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by the

JC

can be measured between these two test cards

JA

operating power. It is measured by putting the mounted package up against a copper block cold plate to force heat to flow
from die, through the mold compound into the copper block.

is often misused when it is used to calculate junction temperatures for other

Θ

JA

Θ

is a useful thermal characteristic when a heatsink is applied to package. It is NOT a useful characteristic to predict

JC

junction temperature as it provides pessimistic numbers if the case temperature is measured in a non-standard system and
junction temperatures are backed out. It can be used with Θ

Θ

(Junction-to-Board Thermal Resistance) is defined to be the difference in the junction temperature and the PCB

JB

in 1-dimensional thermal simulation of a package system.

JB

temperature at the center of the package (closest to the die) when the PCB is clamped in a cold−plate structure. ΘJB is only
defined for the high-k test card.

Θ

provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal resistance

JB

(especially for BGA’s with thermal balls) and can be used for simple 1-dimensional network analysis of package system
(see Figure 1).

Ambient Node

qCA Calculated

Surface Node

qJC Calculated/Measured

Junction

qJB Calculated/Measured

PC Board

Figure 1. Thermal Resistance

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176


DIFFERENTIAL BUS TRANSCEIVERS


SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010

MECHANICAL INFORMATION

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0.050 (1,27)

14

1

0.069 (1,75) MAX

A

0.020 (0,51)

0.014 (0,35)

0.010 (0,25)

0.004 (0,10)

DIM

8

7

PINS **

0.010 (0,25)

0.157 (4,00)

0.150 (3,81)

M

0.244 (6,20)

0.228 (5,80)

Seating Plane

0.004 (0,10)

8

14

0.008 (0,20) NOM

0°− 8°

16

Gage Plane

0.010 (0,25)

0.044 (1,12)

0.016 (0,40)

A MAX

A MIN

NOTES: A. All linear dimensions are in inches (millimeters).

12

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.197

(5,00)

0.189

(4,80)

0.344

(8,75)

0.337

(8,55)

0.394

(10,00)

0.386

(9,80)

4040047/D 10/96



SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176

DIFFERENTIAL BUS TRANSCEIVERS



SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010

MECHANICAL INFORMATION

FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

28 TERMINALS SHOWN

A SQ

B SQ

19

20

22

23

24

25

21

12826 27

121314151618 17

0.020 (0,51)

0.010 (0,25)

MIN

0.342

(8,69)

0.442

0.640

0.740

0.938

1.141

A

0.358

(9,09)

0.458

(11,63)

0.660

(16,76)

0.761

(19,32)(18,78)

0.962

(24,43)

1.165

(29,59)

NO. OF

TERMINALS

**

11

10

9

8

7

6

5

432

20

28

44

52

68

84

0.020 (0,51)

0.010 (0,25)

(11,23)

(16,26)

(23,83)

(28,99)

MINMAX

0.307
(7,80)

0.406

(10,31)

0.495

(12,58)

0.495

(12,58)

0.850
(21,6)

1.047
(26,6)

0.080 (2,03)

0.064 (1,63)

B

MAX

0.358
(9,09)

0.458

(11,63)

0.560

(14,22)

0.560

(14,22)

0.858
(21,8)

1.063
(27,0)

0.055 (1,40)

0.045 (1,14)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold-plated.

E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

4040140/C 11/95

13

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176


DIFFERENTIAL BUS TRANSCEIVERS


SLLS067H − AUGUST 1990 − REVISED DECEMBER 2010

MECHANICAL INFORMATION

JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE PACKAGE

0.400 (10,20)

0.355 (9,00)

0.063 (1,60)

0.015 (0,38)

0.100 (2,54)

8

1

5

4

0.065 (1,65)

0.045 (1,14)

0.020 (0,51) MIN

0.280 (7,11)

0.245 (6,22)

0.200 (5,08) MAX

0.130 (3,30) MIN

0.023 (0,58)

0.015 (0,38)

0.310 (7,87)

0.290 (7,37)

Seating Plane

0°−15°

0.014 (0,36)

0.008 (0,20)

NOTES: A. All linear dimensions are in inches (millimeters).

14

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL-STD-1835 GDIP1-T8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4040107/C 08/96

MECHANICAL DATA

MPDI001A − JANUARY 1995 − REVISED JUNE 1999

MECHANICAL INFORMATION

P (R-PDIP-T8) PLASTIC DUAL-IN-LINE

0.400 (10,60)

0.355 (9,02)

8

5

0.260 (6,60)

0.240 (6,10)

1

0.021 (0,53)

0.015 (0,38)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001

4

0.070 (1,78) MAX

0.020 (0,51) MIN

0.200 (5,08) MAX

0.125 (3,18) MIN

0.100 (2,54)

0.010 (0,25)

Seating Plane

M

0.325 (8,26)

0.300 (7,62)

0.015 (0,38)

Gage Plane

0.010 (0,25) NOM

0.430 (10,92)
MAX

4040082/D 05/98

For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

15

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device

5962-9318301Q2A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
5962-9318301QPA ACTIVE CDIP JG 8 1 TBD Call TI Call TI

SN65LBC176D ACTIVE SOIC D 8 75 Green (RoHS

SN65LBC176DG4 ACTIVE SOIC D 8 75 Green (RoHS

SN65LBC176DR ACTIVE SOIC D 8 2500 Green (RoHS

SN65LBC176DRG4 ACTIVE SOIC D 8 2500 Green (RoHS

SN65LBC176P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

SN65LBC176PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

SN65LBC176QD ACTIVE SOIC D 8 75 Green (RoHS

SN65LBC176QDG4 ACTIVE SOIC D 8 75 Green (RoHS

SN65LBC176QDR ACTIVE SOIC D 8 2500 Green (RoHS

SN65LBC176QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS

SN75LBC176D ACTIVE SOIC D 8 75 Green (RoHS

SN75LBC176DG4 ACTIVE SOIC D 8 75 Green (RoHS

SN75LBC176DR ACTIVE SOIC D 8 2500 Green (RoHS

SN75LBC176DRG4 ACTIVE SOIC D 8 2500 Green (RoHS

SN75LBC176P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN75LBC176PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SNJ55LBC176FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ55LBC176JG ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type

Status

(1)

Package Type Package

Drawing

Pins Package Qty

Eco Plan

& no Sb/Br)

& no Sb/Br)

& no Sb/Br)

& no Sb/Br)

& no Sb/Br)

& no Sb/Br)

& no Sb/Br)

& no Sb/Br)

& no Sb/Br)

& no Sb/Br)

& no Sb/Br)

& no Sb/Br)

(2)

Lead/

Ball Finish

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

MSL Peak Temp

23-May-2012

(3)

Samples

(Requires Login)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

23-May-2012

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN55LBC176, SN65LBC176, SN75LBC176 :

Catalog: SN75LBC176

•

Automotive: SN65LBC176-Q1

•

Military: SN55LBC176

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

Military - QML certified for Military and Defense Applications

•

23-May-2012

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

SN65LBC176DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

SN65LBC176QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

SN75LBC176DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Type

Package
Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN65LBC176DR SOIC D 8 2500 340.5 338.1 20.6

SN65LBC176QDR SOIC D 8 2500 367.0 367.0 35.0

SN75LBC176DR SOIC D 8 2500 340.5 338.1 20.6

Pack Materials-Page 2

MECHANICAL DATA

MCER001A – JANUARY 1995 – REVISED JANUARY 1997

JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE

0.400 (10,16)

0.355 (9,00)

0.063 (1,60)

0.015 (0,38)

0.100 (2,54)

8

1

5

4

0.065 (1,65)

0.045 (1,14)

0.020 (0,51) MIN

0.023 (0,58)

0.015 (0,38)

0.280 (7,11)

0.245 (6,22)

0.310 (7,87)

0.290 (7,37)

0.200 (5,08) MAX
Seating Plane

0.130 (3,30) MIN

0°–15°

0.014 (0,36)

0.008 (0,20)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.

E. Falls within MIL STD 1835 GDIP1-T8

4040107/C 08/96

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products Applications

Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Copyright © 2012, Texas Instruments Incorporated