Datasheet SN75ALS164DW, SN75ALS164DWR, SN75ALS164N Datasheet (Texas Instruments)

Page 1
DW PACKAGE
(TOP VIEW)
GPIB
I/O Ports
Terminal I/O Ports
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
SC
TE
REN
IFC NDAC NRFD
DAV
EOI
ATN
SRQ
NC
GND
V
CC
ATN+ EOI REN IFC NDAC NRFD DAV EOI ATN SRQ NC DC
NOT RECOMMENDED FOR NEW DESIGNS
NC – No internal connection
SN75ALS164
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS022C – JUNE 1986 – REVISED MA Y 1998
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D
8-Channel Bidirectional Transceiver
D
Designed to Implement Control Bus Interface
D
Designed for Multiple-Controller Systems
D
High-Speed Advanced Low-Power Schottky Circuitry
D
Low-Power Dissipation...46 mW Max Per Channel
D
Fast Propagation Times . . . 20 ns Max
D
High-Impedance pnp Inputs
D
Receiver Hysteresis...650 mV Typ
D
Bus-Terminating Resistors Provided on Driver Outputs
D
No Loading of Bus When Device Is Powered Down (V
CC
= 0)
D
Power-Up/Power-Down Protection (Glitch Free)
description
The SN75ALS164 eight-channel general-purpose interface bus transceiver is a monolithic, high-speed, advanced low-power Schottky device designed to meet the requirements of IEEE Standard 488-1978. Each transceiver is designed to provide the bus-management and data-transfer signals between operating units of a multiple-controller instrumentation system. When combined with the SN75ALS160 octal bus transceiver, the SN75ALS164 provides the complete 16-wire interface for the IEEE 488 bus.
The SN75ALS164 features eight driver-receiver pairs connected in a front-to-back configuration to form input/output (I/O) ports at both the bus and terminal sides. All outputs are disabled (at the high-impedance state) during V
CC
power-up and power-down transitions for glitch-free operation. The direction of data flow through these driver-receiver pairs is determined by the DC, TE, and SC enable signals. The SN75ALS164 is identical to the SN75ALS162 with the addition of an OR gate to help simplify board layouts in several popular applications. The ATN and EOI signals are ORed to provide the ATN + EOI output, which is a standard totem-pole output.
The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high impedance to the bus when supply voltage V
CC
is 0. The drivers are designed to handle loads up to 48 mA of sink current. Each receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV minimum for increased noise immunity . All receivers have 3-state outputs that present a high impedance to the terminal when disabled.
The SN75ALS164 is characterized for operation from 0°C to 70°C.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Page 2
SN75ALS164 OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS022C – JUNE 1986 – REVISED MA Y 1998
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
CHANNEL IDENTIFICATION TABLE
NAME
IDENTITY CLASS
DC TE SC
Direction-Control Talk-Enable System Control
Control
ATN SRQ REN
IFC
EOI
Attention Service Request Remote Enable Interface Clear End or Identity
Bus Management
ATN+EOI ATN Logical or EOI Logic
DAV
NDAC NRFD
Data Valid No Data Accepted Not Ready for Data
Data Transfer
Function Tables
RECEIVE/TRANSMIT FUNCTION TABLE
CONTROLS
BUS-MANAGEMENT CHANNELS DATA-TRANSFER CHANNELS
SC DC TE ATN
ATN
SRQ REN IFC EOI DAV NDAC NRFD
(controlled by DC) (controlled by SC) (controlled by TE)
H H H
T
H H L
R
TRT
R
R
L L H
R
L L L
T
RTR
T
T
H L X R T R R T T
L H X T R T T R R H T T L R R
H = high level, L = low level, R = receive, T = transmit, X = irrelevant Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side. Data transfer is noninverting in both directions.
ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI when the DC and TE inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only.
ATN + EOI FUNCTION TABLE
INPUTS
OUTPUT
ATN EOI
ATN + EOI
H X H X HH LLL
Page 3
SN75ALS164
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS022C – JUNE 1986 – REVISED MA Y 1998
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic symbol
EN3
EN2/G5
3
2
2
3
DAV
NDAC
EOI
SRQ
REN
IFC
6
6
1
5
7
4
3
10
8
15
22
21
18
20
NDAC
DAV
IFC
REN
SRQ
ATN + EOI
23
17
EOI
1
1
1
1
1 1
11
ATN
9
EN6
4
5
ATN
16
SC
TE
1
2
2
3
1
1
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
EN1/G4DC
1
2
13
1
2
NRFD
6
19
NRFD
1
2
3
Designates 3-state outputs Designates passive-pullup outputs
logic diagram (positive logic)
13
DC
TE
2
ATN + EOI
23
9
16
ATN
ATN
EOI
EOI
17
8
SRQ
SRQ
15
10
3
22
REN
REN
4
21
IFC
IFC
DAV
DAV
18
7
5
20
NDAC
NDAC
SC
1
6
19
NRFD
NRFD
Page 4
SN75ALS164 OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS022C – JUNE 1986 – REVISED MA Y 1998
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
schematics of inputs and outputs
EQUIVALENT OF ALL
CONTROL INPUTS
TYPICAL OF SRQ, NDAC, AND NRFD
GPIB I/O PORT
Circuit inside dashed lines is on the driver outputs only.
TYPICAL OF ALL I/O PORTS
EXCEPT SRQ, NDAC, AND NRFD GPIB I/O PORTS
Receiver output Req = 110 NOM
Driver output Req = 30 NOM
GND
Input
V
CC
NOM
9 k
10 k NOM
1.7 k
NOM
NOM
4 k
Input/Output Port
10 k NOM
1.7 k NOM
NOM
4 k
R
eq
NOM
4 k
Input/Output Port
ATN + EOI OUTPUT
GND
Output
V
CC
8 k 200 k
4.6 k
2.5 k1.3 k
GND
V
CC
GND
V
CC
Circuit inside dashed lines is on the driver outputs only.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
CC
(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-level driver output current 100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2) 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51.
Page 5
SN75ALS164
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS022C – JUNE 1986 – REVISED MA Y 1998
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
CC
4.75 5 5.25 V
High-level input voltage, V
IH
2 V
Low-level input voltage, V
IL
0.8 V
Bus ports with 3-state outputs – 5.2 mA
High-level output current, I
OH
Terminal ports – 800 ATN + EOI – 400
µ
A
Bus ports 48
Low-level output current, I
OL
Terminal ports 16
mA
ATN + EOI 4
Operating free-air temperature, T
A
0 70 °C
electrical characteristics over recommended supply-voltage and operating free-air temperature ranges (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
Input clamp voltage II = –18 mA – 0.8 –1.5 V
V
hys
Hysteresis (VT+ – VT–) Bus 0.4 0.65 V
Terminal IOH = – 800 µA 2.7 3.5
V
OH
High-level output voltage
Bus
IOH = – 5.2 mA 2.5 3.3
V ATN+EOI IOH = – 400 µA 2.7 Terminal IOL = 16 mA 0.3 0.5
V
OL
Low-level output voltage
Bus
IOL = 48 mA 0.35 0.5
V ATN+EOI IOL = 4 mA 0.4
Input current at maximum input
Terminal
§
VI = 5.5 V 0.2 100
I
I
voltage
ATN, EOI
VI = 5.5 V 200
µA
I
IH
High-level input current
Terminal control
VI = 2.7 V 0.1 20
µA
IH
g
ATN, EOI VI = 2.7 V 40
µ
I
IL
Low-level input current
Terminal control
VI = 0.5 V –10 –100
µA
IL
ATN, EOI VI = 0.5 V – 500
µ
p
I
I(bus)
= 0 2.5 3.0 3.7
V
I/O(bus)
Voltage at bus port
Driver disabled
I
I(bus)
= –12 mA –1.5
V
V
I(bus)
= –1.5 V to 0.4 V –1.3
V
I(bus)
= 0.4 V to 2.5 V 0 –3.2
I
I/O(bus
)
Current into bus port
Power on
Driver disabled
V
I(bus)
= 2.5 V to 3.7 V
+ 2.5 – 3.2
mA
I/O(bus)
V
I(bus)
= 3.7 V to 5 V 0 2.5
V
I(bus)
= 5 V to 5.5 V 0.7 2.5
Power off VCC = 0, V
I(bus)
= 0 to 2.5 V –40 µA
Terminal –15 –35 –75
I
OS
Short-circuit output current
Bus
–25 –50 –125
mA
ATN + EOI –10 –100
I
CC
Supply current No load, TE, DC, and SC low 55 75 mA
C
I/O(bus)
Bus-port capacitance VCC = 0 to 5 V, V
I/O
= 0 to 2 V, f = 1 MHz 30 pF
All typical values are at VCC = 5 V, TA = 25°C.
VOH applies for 3-state outputs only.
§
Except ATN and EOI terminals.
Page 6
SN75ALS164 OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS022C – JUNE 1986 – REVISED MA Y 1998
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, VCC = 5 V
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
MIN TYP MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output
CL = 30 pF,
10 20
t
PHL
Propagation delay time, high-to-low-level output
Terminal
Bus
L
See Figure 1
12 20
ns
t
PLH
Propagation delay time, low-to-high-level output
C
= 30 pF,
5 10
t
PHL
Propagation delay time, high-to-low-level output
Bus
Terminal
L
,
See Figure 2
7 14
ns
t
PLH
Propagation delay time, low-to-high-level output
Terminal ATN
or
Terminal EOI
ATN+EOI
CL = 15 pF, See Figure 3
3.5 10 ns
t
PHL
Propagation delay time, high-to-low-level output
Terminal ATN
or
Terminal EOI
ATN+EOI
CL = 15 pF, See Figure 3
7 15 ns
t
PZH
Output enable time to high level 30
t
PHZ
Output disable time from high level
Bus (ATN, EOI,
C
= 15 pF,
20
t
PZL
Output enable time to low level
TE, DC, or SC
REN, IFC
, an
d
DAV
)
L
,
See Figure 4
45
ns
t
PLZ
Output disable time from low level
DAV)
20
t
PZH
Output enable time to high level 30
t
PHZ
Output disable time from high level
CL = 15 pF,
25
t
PZL
Output enable time to low level
TE, DC, or SC
Terminal
L
See Figure 5
30
ns
t
PLZ
Output disable time from low level 25
Page 7
SN75ALS164
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS022C – JUNE 1986 – REVISED MA Y 1998
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
LOAD CIRCUIT
VOLTAGE WAVEFORMS
V
OL
V
OH
0 V
3 V
1.0 V
1.5 V
(see Note B)
2.2 V
1.5 V
Bus
Output
Terminal
Input
Test Point
(see Note A)
CL = 30 pF
480
200
From (bus)
Output Under
Test
5 V
t
PLH
t
PHL
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, tr 6 ns, tf 6 ns,
ZO = 50 .
Figure 1. Terminal-to-Bus Load Circuit and Voltage Waveforms
LOAD CIRCUIT
VOLTAGE WAVEFORMS
V
OL
V
OH
0 V
3 V
1.5 V
1.5 V
(see Note B)
1.5 V
1.5 V
Terminal
Output
Bus
Input
Test Point
(see Note A)
CL = 30 pF
3k
240
From (terminal)
Output Under
Test
4.3 V
t
PLH
t
PHL
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, tr 6 ns,
tf 6 ns, ZO = 50 .
Figure 2. Bus-to-Terminal Load Circuit and Voltage Waveforms
Page 8
SN75ALS164 OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS022C – JUNE 1986 – REVISED MA Y 1998
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
LOAD CIRCUIT
(see Note A)
C
L
2k
From
ATN+EOI
V
CC
VOLTAGE WAVEFORMS
V
OL
V
OH
0 V
3 V
1.5 V
1.5 V
1.5 V
1.5 V
ATN + EOI
Terminal
ATN+EOI
t
PLH
t
PHL
Test
Point
(see Note B)
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N916 or 1N3064
Figure 3. ATN + EOI Load Circuit and Voltage Waveforms
Page 9
SN75ALS164
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS022C – JUNE 1986 – REVISED MA Y 1998
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
t
PZL
0.5 V
1 V
3.5 V
0 V
V
OH
0 V
3 V
90%
2 V
(see Note B)
Bus
Output
S1 Closed
Bus
Output
S1 Open
Control
Input
1.5 V1.5 V
5 V
Test Point
(see Note A)
CL = 15 pF
480
200
From (bus)
Output Under
Test
S1
LOAD CIRCUIT
VOLTAGE WAVEFORMS
V
OL
t
PZH
t
PLZ
t
PHZ
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, tr 6 ns, tf 6 ns,
ZO = 50 .
Figure 4. Bus Load Circuit and Voltage Waveforms
Page 10
SN75ALS164 OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS022C – JUNE 1986 – REVISED MA Y 1998
10
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
t
PZL
0.7 V
1 V
4 V
0 V
V
OH
0 V
3 V
90%
1.5 V
(see Note B)
Terminal
Output
S1 Closed
Terminal
Output
S1 Open
1.5 V1.5 V
4.3 V
Test Point
(see Note A)
CL = 15 pF
3 k
240
From (terminal)
Output Under
Test
S1
LOAD CIRCUIT
VOLTAGE WAVEFORMS
V
OL
t
PZH
t
PLZ
t
PHZ
Control
Input
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, tr 6 ns, tf 6 ns,
ZO = 50 .
Figure 5. Terminal Load Circuit and Voltage Waveforms
Page 11
SN75ALS164
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS022C – JUNE 1986 – REVISED MA Y 1998
11
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
2
1
0.5
0
0 – 5 – 10 – 15 – 20 – 25
– High-Level Output Voltage – V
3
3.5
TERMINAL HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
4
– 30 – 35 – 40
2.5
1.5
VCC = 5 V TA = 25°C
V
OH
IOH – High-Level Output Current – mA
Figure 6
0.3
0.2
0.1
0
01020
– Low-Level Output Voltage – V
0.4
0.5
TERMINAL LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.6
30 40 50
60
VCC = 5 V TA = 25°C
IOL – Low-Level Output Current – mA
V
OL
Figure 7
2
1.5
0.5
0
0 0.2 0.4 0.6 0.8 1 1.2
– Output Voltage – V
2.5
3.5
TERMINAL OUTPUT VOLTAGE
vs
BUS INPUT VOLTAGE
4
1.4 1.6 1.8 2
1
3
VCC = 5 V No Load TA = 25°C
V
O
VI – Input Voltage – V
V
T–
V
T+
Figure 8
Page 12
SN75ALS164 OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS022C – JUNE 1986 – REVISED MA Y 1998
12
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 9
2
1
0
0 – 10 – 20 – 30 – 40
– High-Level Output Voltage – V
3
BUS HIGH-LEVEL OUTPUT VOLTAGE
vs
BUS HIGH-LEVEL OUTPUT CURRENT
4
– 50 – 60
VCC = 5 V TA = 25°C
IOH – High-Level Output Current – mA
V
OH
Figure 10
0.3
0.2
0.1
0
0 102030405060
– Low-Level Output Voltage – V
0.4
0.5
BUS LOW-LEVEL OUTPUT VOLTAGE
vs
BUS LOW-LEVEL OUTPUT CURRENT
0.6
70 80 90 100
IOL – Low-Level Output Current – mA
V
OL
VCC = 5 V TA = 25°C
Figure 11
2
1
0
0.9 1 1.1 1.2 1.3 1.4
– Output Voltage – V
3
BUS OUTPUT VOLTAGE
vs
TERMINAL INPUT VOLTAGE
4
1.5 1.6 1.7
VI – Input Voltage – V
V
O
VCC = 5 V No Load TA = 25°C
–2
–4
–6
–7
–2 –1 0 1 2 3
II/O(bus) – Bus Current – mA
–1
1
BUS CURRENT
vs
BUS VOLTAGE
456
–5
0
–3
2
I/O(bus)
I
VCC = 5 V TA = 25°C
The Unshaded Area Conforms to Paragraph 3.5.3 of IEEE Standard 488-1978
V
I/O(bus)
– Bus Voltage – V
3
Figure 12
Page 13
IMPORTANT NOTICE
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOL VE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.
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Copyright 1998, Texas Instruments Incorporated
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