Page 1
SN75ALS163
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS021E – JUNE 1986 – REVISED MA Y 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
8-Channel Bidirectional Transceiver
D
High-Speed Advanced Low-Power Schottky
Circuitry
D
Low Power Dissipation...46 mW Max per
Channel
D
Fast Propagation Times . . . 20 ns Max
D
High-Impedance pnp Inputs
D
Receiver Hysteresis...650 mV Typ
D
Open-Collector Driver Output Option
D
No Loading of Bus When Device Is
Powered Down (V
CC
= 0)
D
Power-Up/Power-Down Protection
(Glitch Free)
description
The SN75ALS163 octal general-purpose interface bus transceiver is a monolithic, high-speed, advanced
low-power Schottky device. It is designed for two-way data communications over single-ended transmission
lines. The transceiver features driver outputs that can be operated in either the open-collector or 3-state mode.
If talk enable (TE) is high, these outputs have the characteristics of open-collector outputs when pullup enable
(PE) is low and of 3-state outputs when PE is high. T aking TE low places the outputs in the high-impedance state.
The driver outputs are designed to handle loads of up to 48 mA of sink current. Each receiver features pnp
transistor inputs for high input impedance and 400 mV minimum of hysteresis for increased noise immunity.
Output glitches during power up and power down are eliminated by an internal circuit that disables both the bus
and receiver outputs. The outputs do not load the bus when V
CC
= 0.
The SN75ALS163 is characterized for operation from 0°C to 70°C.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TE
B1
B2
B3
B4
B5
B6
B7
B8
GND
V
CC
D1
D2
D3
D4
D5
D6
D7
D8
PE
DW PACKAGE
(TOP VIEW)
GPIB
I/O
Ports
Terminal
I/O Ports
NOT RECOMMENDED FOR NEW DESIGNS
Page 2
SN75ALS163
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS021E – JUNE 1986 – REVISED MA Y 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
EACH DRIVER
INPUTS
OUTPUT
D TE PE
B
H H H H
L HX L
HXL Z
XLX Z
EACH RECEIVER
INPUTS
OUTPUT
B TE PE
D
L L X L
H LX H
XHX Z
H = high level, L = low level,
X = irrelevant, Z = high-impedance state
logic symbol
†
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Designates 3-state outputs
Designates open-collector outputs
1
EN4 [RCV]
EN3 [XMT]
M2 [0C]
M1 [3S]
B8
B7
B6
B5
B4
B3
B2
B1
9
8
7
6
5
4
3
2
D8
D7
D6
D5
D4
D3
D2
D1
TE
PE
12
13
14
15
16
17
18
19
1
11
/23 (1 )
4
logic diagram (positive logic)
GPIB
I/O
Ports
PE
11
1
TE
Terminal
I/O
Ports
B1
2
19
D1
B2
3
18
D2
B3
4
17
D3
B4
5
16
D4
B5
6
15
D5
B6
7
14
D6
D7
13
8
B7
9
12
D8
B8
Page 3
SN75ALS163
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS021E – JUNE 1986 – REVISED MA Y 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics of inputs and outputs
10 kΩ
NOM
EQUIVALENT OF ALL INPUT/OUTPUT PORTS
R
eq
NOM
4 kΩ
Input/Output Port
Receiver output Req = 110 Ω NOM
Driver output Req = 30 Ω NOM
GND
Input
V
CC
9 kΩ NOM
EQUIVALENT OF ALL CONTROL INPUTS
V
CC
GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, V
CC
(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-level driver output current 100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2) 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
CC
4.75 5 5.25 V
High-level input voltage, V
IH
2 V
Low-level input voltage, V
IL
0.8 V
p
Bus ports with pullups active – 5.2 mA
High-level output current, I
OH
Terminal ports – 800 µA
p
Bus ports 48
Low-level output current, I
OL
Terminal ports 16
mA
Operating free-air temperature, T
A
0 70 °C
Page 4
SN75ALS163
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS021E – JUNE 1986 – REVISED MA Y 1998
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended supply-voltage and operating free-air temperature
ranges (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
Input clamp voltage II = –18 mA – 0.8 –1.5 V
V
hys
Hysteresis (VT+ – VT–) Bus 0.4 0.65 V
p
Terminal IOH = – 800 µA, TE at 0.8 V 2.7 3.5
VOHHigh-level output voltage
Bus IOH = – 5.2 mA, PE and TE at 2 V 2.5 3.3
V
p
Terminal IOL = 16 mA, TE at 0.8 V 0.3 0.5
VOLLow-level output voltage
Bus IOL = 48 mA, TE at 2 V 0.35 0.5
V
I
OH
High-level output current
(open-collector mode)
Bus VO = 5.5 V,
PE at 0.8 V ,
D and TE at 2 V
100 µA
Off-state output current
PE at 2 V, VO = 2.7 V 20
I
OZ
(3-state mode)
Bus
TE at 0.8 V VO = 0.5 V –100
µ
A
I
I
Input current at
maximum input voltage
Terminal VI = 5.5 V 0.2 100 µA
I
IH
High-level input current
Terminal,
VI = 2.7 V 0.1 20 µA
I
IL
Low-level input current
,
PE, or TE
VI = 0.5 V –10 –100 µA
Short-circuit output
T erminal –15 –35 –75
I
OS
current
Bus
–25 –50 –125
mA
I
Supply current No load
Terminal outputs low
and enabled
42 65
mA
CC
y
Bus outputs low and enabled 52 80
C
I/O(bus)
Bus-port capacitance VCC = 0 to 5 V, V
I/O
= 0 to 2 V, f = 1 MHz 30 pF
†
All typical values are at VCC = 5 V, TA = 25°C.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), V
CC
= 5 V
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS MIN
TYP
†
MAX UNIT
t
PLH
Propagation delay time,
low-to-high-level output
CL = 30 pF,
7 20
t
PHL
Propagation delay time,
high-to-low-level output
T erminal
Bus
L
See Figure 1
8 20
ns
t
PLH
Propagation delay time,
low-to-high-level output
C
= 30 pF,
7 14
t
PHL
Propagation delay time,
high-to-low-level output
Bus
T erminal
L
,
See Figure 2
9 14
ns
t
PZH
Output enable time to high level 19 30
t
PHZ
Output disable time from high level
C
= 15 pF,
5 12
t
PZL
Output enable time to low level
TE
Bus
L
,
See Figure 3
16 35
ns
t
PLZ
Output disable time from low level 9 20
t
PZH
Output enable time to high level 13 30
t
PHZ
Output disable time from high level
C
= 15 pF,
12 20
t
PZL
Output enable time to low level
TE
Terminal
L
,
See Figure 4
12 20
ns
t
PLZ
Output disable time from low level 11 20
t
en
Output pull-up enable time
CL = 15 pF,
11 22
t
dis
Output pull-up disable time
PE
Bus
L
See Figure 5
6 12
ns
†
All typical values are at VCC = 5 V, TA = 25°C.
Page 5
SN75ALS163
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS021E – JUNE 1986 – REVISED MA Y 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
V
OH
V
OL
t
PHL
1.5 V
2.2 V
t
PLH
1.5 V
B Output
D Input
(see Note B)
CL = 30 pF
Output
5 V
200 Ω
480 Ω
B
3 V
PE
D
50 Ω
3 V
TE
(see Note A)
Generator
TEST CIRCUIT VOLTAGE WAVEFORMS
1 V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 1. Terminal-to-Bus Test Circuit and Voltage Waveforms
3 V
0 V
V
OH
V
OL
1.5 V
1.5 V
t
PHL
1.5 V
t
PLH
1.5 V
D Output
B Input
D
TE
B
(see Note B)
CL = 30 pF
Output
4.3 V
240 Ω
50 Ω
(see Note A)
Generator
TEST CIRCUIT VOLTAGE WAVEFORMS
3 Ω
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 2. Bus-to-Terminal Test Circuit and Voltage Waveforms
Page 6
SN75ALS163
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS021E – JUNE 1986 – REVISED MA Y 1998
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
TEST CIRCUIT VOLTAGE WAVEFORMS
0.5 V
1 V
90%
0 V
0.8 V
3.5 V
V
OL
V
OH
t
PLZ
3 V
2 V
1.5 V1.5 V
t
PHZ
S2 Closed
S1 to GND
B Output
PZL
t
S2 Open
S1 to 3 V
B Output
t
PZH
TE Input
200 Ω
S2
480 Ω
5 V
Output
(see Note B)
CL = 15 pF
S1
3 V
PE
B
D
50 Ω
TE
(see Note A)
Generator
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 3. TE-to-Bus Test Circuit and Voltage Waveforms
TEST CIRCUIT VOLTAGE WAVEFORMS
t
PLZ
t
PHZ
D Output
t
PZL
t
PZH
S2 Closed
S1 to GND
S2 Open
S1 to 3 V
D Output
TE Input
1.5 V
1 V
0.7 V
90%
V
OL
V
OH
4 V
≈ 0
V
0 V
3 V
1.5 V1.5 V
4.3 V
3 kΩ
240 Ω
S2
50 Ω
S1
3 V
Output
(see Note B)
CL = 15 pF
TE
B
D
(see Note A)
Generator
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 4. TE-to-Terminal Test Circuit and Voltage Waveforms
Page 7
SN75ALS163
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS021E – JUNE 1986 – REVISED MA Y 1998
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
TEST CIRCUIT VOLTAGE WAVEFORMS
90%
0 V
V
OH
3 V
2 V
t
dis
t
en
1.5 V1.5 V
B Output
PE Input
Output
RL = 480 Ω
(see Note B)
CL = 15 pF
3 V
50 Ω
TE
PE
B
D
(see Note A)
Generator
VOL≈ 0.8 V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 5. PE-to-Bus Test Circuit and Voltage Waveforms
Page 8
SN75ALS163
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS021E – JUNE 1986 – REVISED MA Y 1998
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 6
2
1
0.5
0
0 – 5 – 10 – 15 – 20 – 25
– High-Level Output Voltage – V
3
3.5
TERMINAL HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
4
– 30 – 35 – 40
2.5
1.5
VCC = 5 V
TA = 25°C
V
OH
IOH – High-Level Output Current – mA
Figure 7
0.3
0.2
0.1
0
01020
– Low-Level Output Voltage – V
0.4
0.5
TERMINAL LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.6
30 40 50
60
VCC = 5 V
TA = 25°C
IOL – Low-Level Output Current – mA
V
OL
2
1.5
0.5
0
0 0.2 0.4 0.6 0.8 1 1.2
– Output Voltage – V
2.5
3.5
TERMINAL OUTPUT VOLTAGE
vs
BUS INPUT VOLTAGE
4
1.4 1.6 1.8 2
1
3
VCC = 5 V
No Load
TA = 25°C
V
O
VI – Input Voltage – V
V
T–
V
T+
Figure 8
Page 9
SN75ALS163
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS021E – JUNE 1986 – REVISED MA Y 1998
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 9
2
1
0
0 – 10 – 20 – 30 – 40
– High-Level Output Voltage – V
3
BUS HIGH-LEVEL OUTPUT VOLTAGE
vs
BUS HIGH-LEVEL OUTPUT CURRENT
4
–50 –60
VCC = 5 V
TA = 25°C
IOH – High-Level Output Current – mA
V
OH
Figure 10
0.3
0.2
0.1
0
0 102030405060
– Low-Level Output Voltage – V
0.4
0.5
BUS LOW-LEVEL OUTPUT VOLTAGE
vs
BUS LOW-LEVEL OUTPUT CURRENT
0.6
70 80 90 100
IOL – Low-Level Output Current – mA
V
OL
VCC = 5 V
TA = 25°C
2
1
0
0.9 1 1.1 1.2 1.3 1.4
– Output Voltage – V
3
BUS OUTPUT VOLTAGE
vs
TERMINAL INPUT VOLTAGE
4
1.5 1.6 1.7
VI – Input Voltage – V
V
O
VCC = 5 V
No Load
TA = 25°C
Figure 11
Page 10
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Copyright 1998, Texas Instruments Incorporated
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