Low Power Dissipation:
SN55ALS160...56 mW Max Per Channel
SN75ALS160...46 mW Max Per Channel
D
Fast Propagation Times . . . 20 ns Max
D
High-Impedance pnp Inputs
D
Receiver Hysteresis:
SN55ALS160...550 mV T yp
SN75ALS160...650 mV T yp
D
Open-Collector Driver Output Option
D
No Loading of Bus When Device Is
Powered Down (V
D
Power-Up/Power-Down Protection
(Glitch Free)
CC
= 0)
description
The SN55ALS160 and SN75ALS160 eightchannel general-purpose interface bus
transceivers are monolithic, high-speed,
advanced low-power Schottky (ALS) devices
designed for two-way data communications over
single-ended transmission lines. They are
GPIB
I/O Ports
SN55ALS160 ...J OR W PACKAGE
SN75ALS160 . . . DW OR N PACKAGE
TE
B1
B2
B3
B4
B5
B6
B7
B8
GND
SN55ALS160 ...FK PACKAGE
B3
4
B4
5
B5
6
B6
7
B7
8
†
(TOP VIEW)
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
(TOP VIEW)
CC
B2B1TE
3212019
910111213
V
D1
18
17
16
15
14
V
D1
D2
D3
D4
D5
D6
D7
D8
PE
CC
Terminal
I/O Ports
D2
D3
D4
D5
D6
designed to meet the requirements of IEEE
Standard 488-1978. The transceivers feature
driver outputs that can be operated in either the
B8
GND
PE
D8
D7
passive-pullup or 3-state mode. If talk enable (TE) is high, these ports have the characteristics of passive-pullup
outputs when pullup enable (PE) is low and of 3-state outputs when PE is high. T aking TE low places these ports
in the high-impedance state. The driver outputs are designed to handle loads up to 48 mA of sink current.
An active turn-off feature has been incorporated into the bus-terminating resistors so that the device exhibits
a high impedance to the bus when V
= 0. When combined with the SN55ALS161, SN75ALS161, or
CC
SN75ALS162 bus management transceiver , the pair provides the complete 16-wire interface for the IEEE-488
bus.
The SN55ALS160 is characterized for operation from –55°C to 125°C. The SN75ALS160 is characterized for
operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
The transceivers are suitable for IEEE Standard 896 applications to the extent of the operating conditions and characteristics specified in this
data sheet. Certain limits contained in the IEEE specification are not met or cannot be tested over the entire military temperature range.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1995, Texas Instruments Incorporated
1
Page 2
SN55ALS160, SN75ALS160
OUTPUT
OUTPUT
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS018D – JUNE 1986 – REVISED MA Y 1995
Function Tables
EACH DRIVER
INPUTS
DTEPE
HHHH
LHX L
HXL Z
XLX Z
EACH RECEIVER
INPUTS
BTEPE
LLXL
HLX H
XHX Z
H = high level, L = low level, X = irrelevant,
Z = high-impedance state
†
This is the high-impedance state of a
normal 3-state output modified by the
internal resistors to VCC and GND.
OUTPUT
B
‡
‡
OUTPUT
D
logic symbol
11
PE
1
TE
19
D1
18
D2
17
D3
16
D4
15
D5
14
D6
13
D7
12
D8
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Designates 3-state outputs
Designates open-collectoroutputs with passive pullup
‡
M1 [3S]
M2 [0C]
EN3 [XMT]
EN4 [RCV]
4
/23 (1)
1
logic diagram (positive logic)
11
PE
1
TE
19
D1
2
B1
3
B2
4
B3
5
B4
6
B5
7
B6
B7
B8
Terminal
I/O
Ports
8
9
D2
D3
D4
D5
D6
D7
D8
18
17
16
15
14
13
12
2
B1
3
B2
4
B3
5
B4
GPIB
I/O
6
7
8
9
Ports
B5
B6
B7
B8
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 3
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
schematics of inputs and outputs
SN55ALS160, SN75ALS160
SLLS018D – JUNE 1986 – REVISED MA Y 1995
EQUIVALENT OF ALL CONTROL INPUTS
V
CC
Input
GND
9 kΩ
NOM
Driver output R
Receiver output R
R
= equivalent resistor
(eq)
Circuit inside dashed lines is on the driver outputs only.
EQUIVALENT OF ALL INPUT/OUTPUT PORTS
1.7 kΩ
NOM
4 kΩ
NOM
4 kΩ
NOM
= 30 Ω NOM
(eq)
(eq)
R
(eq)
Input/Output Port
= 110 Ω NOM
10 kΩ
NOM
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Low-level driver output current, I
Operating free-air temperature range, T
Storage temperature range, T
Case temperature for 60 seconds, T
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: DW or N package 260°C. . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from the case for 60 seconds: J or W package 300°C. . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.
Supply voltage, V
High-level input voltage, V
Low-level input voltage, V
Operating free-air temperature, T
CC
TE and PE at TA = –55°C to 125°C2
IH
IL
p
p
CC
p
p
OH
OL
IH
IL
OH
OL
Bus and terminal at TA = 25°C to 125°C2
Bus and terminal at TA = –55°C2.1
TE and PE at TA = –55°C to 125°C0.8
Bus and terminal at TA = 25°C to –55°C0.8
Bus and terminal at TA = 125°C0.7
Bus ports with pullups active (VCC = 5 V)– 5.2mA
Terminal ports– 800µA
Bus ports48
Terminal ports16
A
Bus ports with pullups active– 5.2mA
Terminal ports– 800µA
Bus ports48
Terminal ports16
A
MINNOMMAXUNIT
4.7555.25V
V
V
–55125°C
MINNOMMAXUNIT
4.7555.25V
2V
0.8V
070°C
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER
TEST CONDITIONS
†
UNIT
y
(V
IT
V
IT
)
Bus
V
§
High-level output voltage
V
VOLLow-level output voltage
V
,
V
Voltage at bus port
,
V
I/O(bus)
IOSShort-circuit output current
mA
ICCSupply current
,
mA
•5
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless
otherwise noted)
SN55ALS160SN75ALS160
MIN TYP‡MAXMIN TYP‡MAX
V
IK
V
hys
OH
I
I
I
IH
I
IL
I/O(bus)
I
C
I/O(bus)
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
Terminal outputs low and enabled42564265
Bus outputs low and enabled52855280
= 0 to 2 V,f = 1 MHz3030pF
I/O
2.5
– 3.2
2.5
– 3.2
mA
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS018D – JUNE 1986 – REVISED MAY 1995
SN55ALS160, SN75ALS160
Page 6
t
gy,g
Terminal
Bus
See Figure 1
ns
t
gy,g
t
gy,g
Bus
Terminal
See Figure 2
ns
t
gy,g
t
Output enable time to high level
t
Output disable time from high level
TE
Bus
See Figure 3
ns
t
Output enable time to low level
t
Output disable time from low level
t
Output enable time to high level
t
Output disable time from high level
TE
Terminal
See Figure 4
t
Output enable time to low level
t
Output disable time from low level
tenOutput pullup enable time
PE
Bus
See Figure 5
t
Output pullup disable time
SN55ALS160, SN75ALS160
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS018D – JUNE 1986 – REVISED MA Y 1995
switching characteristics at VCC = 4.75 V, 5 V, and 5.25 V, CL = 50 pF (unless otherwise noted)
PARAMETER
Propagation delay time, low- to high-level
PLH
output
Propagation delay time, high- to low-level
PHL
output
Propagation delay time, low- to high-level
PLH
output
Propagation delay time, high- to low-level
PHL
output
PZH
PHZ
PZL
PLZ
PZH
PHZ
PZL
PLZ
dis
†
Full range is –55°C to 125°C.
‡
All typical values are at VCC = 5 V.
p
p
p
p
p
p
p
p
p
p
p
p
p
p
FROM
(INPUT)TO(OUTPUT)
TEST
CONDITIONS
†
T
A
25°C1017
Full range20
25°C1014
Full range16
25°C815
Full range18
25°C815
Full range18
25°C2430
Full range41
25°C914
Full range16
25°C1628
Full range34
25°C1219
Full range24
25°C2436
Full range50
25°C1018
Full range23
25°C1526
Full range30
25°C1524
Full range31
25°C1624
Full range25
25°C916
Full range20
MIN TYP‡MAXUNIT
ns
ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
Page 7
SN55ALS160, SN75ALS160
Terminal
Bus
L
,
ns
Bus
Terminal
L
,
ns
TE
Bus
L
,
ns
TE
Terminal
L
,
ns
PE
Bus
L
ns
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS018D – JUNE 1986 – REVISED MA Y 1995
switching characteristics over recommended range of operating free-air temperature, VCC = 5 V
PARAMETER
t
Propagation delay time, low- to high-level output
PLH
t
Propagation delay time, high- to low-level output
PHL
t
Propagation delay time, low- to high-level output
PLH
t
Propagation delay time, high- to low-level output
PHL
t
Output enable time to high level1930
PZH
t
Output disable time from high level
PHZ
t
Output enable time to low level
PZL
t
Output disable time from low level920
PLZ
t
Output enable time to high level1330
PZH
t
Output disable time from high level
PHZ
t
Output enable time to low level
PZL
t
Output disable time from low level1120
PLZ
t
Output pullup enable time
en
t
Output pullup disable time
dis
†
Typical values are at TA = 25°C.
FROM
(INPUT)TO(OUTPUT)
TEST
CONDITIONS
C
= 30 pF,
See Figure 1
C
= 30 pF,
See Figure 2
C
= 15 pF,
See Figure 3
C
= 15 pF,
See Figure 4
CL = 15 pF,
See Figure 5
MIN TYP†MAXUNIT
720
820
714
914
512
1635
1220
1220
1122
612
PARAMETER MEASUREMENT INFORMATION
5 V
PE
3 V
Generator
(see Note A)
[ ] denotes the SN55ALS160 military test conditions.
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
D
50 Ω
TE
3 V
TEST CIRCUITVOLTAGE WA VEFORMS
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Output
B
CL = 30 pF
[ = 50 pF]
(see Note B)
Figure 1. Terminal-to-Bus Test Circuit and Voltage Waveforms
[7 V]
200 Ω
[500 Ω]
480 Ω
[500 Ω]
D Input
t
PLH
B Output
1.5 V
2.2 V
t
PHL
1.5 V
1 V
3 V
0
V
V
OH
OH
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 8
SN55ALS160, SN75ALS160
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS018D – JUNE 1986 – REVISED MA Y 1995
PARAMETER MEASUREMENT INFORMATION
TE
Output
Generator
(see Note A)
[ ] denotes the SN55ALS160 military test conditions.
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
B
50 Ω
TEST CIRCUITVOLTAGE WAVEFORMS
D
CL = 30 pF
[ = 50 pF]
(see Note B)
4.3 V
[7 V]
240 Ω
[500 Ω]
3 kΩ
[500 Ω]
B Input
t
PLH
D Output
1.5 V
t
PHL
1.5 V1.5 V
1.5 V
3 V
0
V
V
OH
OL
Figure 2. Bus-to-Terminal Test Circuit and Voltage Waveforms
5 V
3 V
Generator
(see Note A)
S1
PE
D
50 Ω
[7 V]
200 Ω
Output
B
CL = 15 pF
[ = 50 pF]
(see Note B)
TE
TEST CIRCUITVOLTAGE WAVEFORMS
[500 Ω]
S2
480 Ω
[500 Ω]
TE Input
t
PZH
B Output
S1 to 3 V
S2 Open
t
PZL
B Output
S1 to GND
S2 Closed
2 V
1 V
t
PHZ
t
PLZ
1.5 V1.5 V
90%
0.5 V
3 V
0
V
OH
0.8 V
3.5 V
V
OL
[ ] denotes the SN55ALS160 military test conditions.
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 3. TE-to-Bus Test Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
Page 9
SN55ALS160, SN75ALS160
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS018D – JUNE 1986 – REVISED MA Y 1995
PARAMETER MEASUREMENT INFORMATION
4.3 V
[7 V]
TE Input
Generator
(see Note A)
3 V
[ ] denotes the SN55ALS160 military test conditions.
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
B. CL includes probe and jig capacitance.
TE
50 Ω
S1
ZO = 50 Ω.
S2
Output
240 Ω
D
B
TEST CIRCUITVOLTAGE WAVEFORMS
[500 Ω]
CL = 15 pF
[ = 50 pF]
(see Note B)
3 kΩ
[500 Ω]
t
PZH
D Output
S1 to 3 V
S2 Open
t
PZL
D Output
S1 to GND
S2 Closed
1.5 V
1.5 V
1 V
t
PHZ
t
PLZ
1.5 V
90%
0.7 V
3 V
0
V
0
4 V
V
OH
OL
Figure 4. TE-to-T erminal Test Circuit and Voltage Waveforms
Generator
(see Note A)
50 Ω
3 V
PE
TE
BD
CL = 15 pF
[ = 50 pF]
(see Note B)
Output
RL = 480 Ω
[ = 500 Ω ]
PE Input
t
en
B Output
1.5 V
2 V
t
dis
1.5 V
90%
3 V
0
V
OH
VOL ≈ 0.8
TEST CIRCUIT
[ ] denotes the SN55ALS160 military test conditions.
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
VOLTAGE WAVEFORMS
Figure 5. PE-to-Bus Test Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 10
SN55ALS160, SN75ALS160
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS018D – JUNE 1986 – REVISED MA Y 1995
TYPICAL CHARACTERISTICS
TERMINAL HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT CURRENT
4
3.5
3
2.5
2
1.5
– High-Level Output Voltage – V
1
OH
V
0.5
0
0– 5 – 10 – 15 – 20 – 25
IOH – High-Level Output Current – mA
vs
vs
LOW-LEVEL OUTPUT CURRENT
TERMINAL LOW-LEVEL OUTPUT VOLTAGE
0.6
VCC = 5 V
TA = 25°C
–30 –35 –40
– Low-Level Output Voltage – V
OL
V
VCC = 5 V
TA = 25°C
0.5
0.4
0.3
0.2
0.1
0
01020
IOL – Low-Level Output Current – mA
304050
Figure 6Figure 7
TERMINAL OUTPUT VOLTAGE
vs
BUS INPUT VOLTAGE
4
VCC = 5 V
No Load
3.5
TA = 25°C
3
60
2.5
2
1.5
– Output Voltage – V
O
V
1
0.5
0
00.2 0.4 0.6 0.811.2
VI – Input Voltage – V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V
IT –
Figure 8
V
IT +
1.4 1.6 1.82
11
Page 11
SN55ALS160, SN75ALS160
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS018D – JUNE 1986 – REVISED MA Y 1995
TYPICAL CHARACTERISTICS
BUS HIGH-LEVEL OUTPUT VOLTAGE
BUS HIGH-LEVEL OUTPUT CURRENT
4
3
2
1
– High-Level Output Voltage – V
OH
V
0
0– 10– 20– 30– 40
IOH – High-Level Output Current – mA
Figure 9
vs
VCC = 5 V
TA = 25°C
–50–60
BUS LOW-LEVEL OUTPUT VOLTAGE
BUS LOW-LEVEL OUTPUT CURRENT
0.6
VCC = 5 V
TA = 25°C
0.5
0.4
0.3
0.2
– Low-Level Output Voltage – V
OL
0.1
V
0
0 102030405060
IOL – Low-Level Output Current – mA
vs
70 80 90 100
Figure 10
BUS OUTPUT VOLTAGE
TERMINAL INPUT VOLTAGE
4
VCC = 5 V
No Load
TA = 25°C
3
2
– Output Voltage – V
O
V
1
0
0.911.11.21.31.4
VI – Input Voltage – V
Figure 11
vs
1.51.61.7
BUS CURRENT
BUS VOLTAGE
VCC = 5 V
2
TA = 25°C
1
0
–1
–2
–3
–4
I/O(bus)
I
II/O(bus) – Bus Current – mA
–5
–6
–7
–2–10123
The Unshaded Area
Conforms to Paragraph 3.5.3
of IEEE Standard 488-1978
V
– Bus Voltage – V
I/O(bus)
Figure 12
vs
456
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 12
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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