Datasheet SN74SSTL16837ADGGR Datasheet (Texas Instruments)

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Page 1

SN74SSTL16837A

20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER

WITH 3-STATE OUTPUTS

SCBS675G – SEPTEMBER 1996 – REVISED SEPTEMBER 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Member of the Texas Instruments

Widebus

 Family

Supports SSTL_3 Signal Inputs and Outputs

Flow-Through Architecture Optimizes PCB Layout

Meets SSTL_3 Class I and Class II Specifications

Latch-Up Performance Exceeds 250 mA Per JESD 17

Packaged in Plastic Thin Shrink Small-Outline Package

description

This 20-bit universal bus driver is designed for 3-V to 3.6-V V

operation and SSTL_3 or L VTTL I/O

levels. Data flow from A to Y is controlled by the

output-enable (OE

) input. The device operates in the transparent mode when latch enable (LE) is high. The A data is latched if LE is low and clock (CLK) is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE

is high,

the outputs are in the high-impedance state. T o ensure the high-impedance state during power

up or power down, OE

should be tied to V

through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74SSTL16837A is characterized for operation from 0°C to 70°C.

Widebus is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DGG PACKAGE

(TOP VIEW)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

Y1 Y2

GND

Y3 Y4

DDQ

Y5 Y6

GND

Y7 Y8

DDQ

Y10

GND

REF

GND

Y1 1 Y12

DDQ

Y13 Y14

GND

Y15 Y16

DDQ

Y17 Y18

GND

Y19 Y20

A1 A2 GND A3 A4 V

A5 A6 GND A7 A8 V

A9 A10 GND CLK LE GND A1 1 A12 V

A13 A14 GND A15 A16 V

A17 A18 GND A19 A20

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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SN74SSTL16837A 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

SCBS675G – SEPTEMBER 1996 – REVISED SEPTEMBER 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

INPUTS

OUTPUT

OE LE CLK A

L H X H H L HXL L LL↑HH LL↑LL LLHX Y

†

LLLX Y

‡

HXXX Z

†

Output level before the indicated steady-state input conditions were established, provided that CLK was high before LE went low

‡

Output level before the indicated steady-state input conditions were established

logic diagram (positive logic)

CLK

To 19 Other Channels

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

or V

DDQ

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

(see Notes 1 and 2) –0.5 V to V

DDQ

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

(VO = 0 to V

DDQ

) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through each V

, V

DDQ

, or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

(see Note 3) 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and VO > V

DDQ

3. The package thermal impedance is calculated in accordance with JESD 51.

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SN74SSTL16837A

20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER

WITH 3-STATE OUTPUTS

SCBS675G – SEPTEMBER 1996 – REVISED SEPTEMBER 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 4)

MIN NOM MAX UNIT

Supply voltage V

DDQ

3.6 V

DDQ

Output supply voltage 3 3.6 V

REF

Reference voltage (V

REF

= 0.45 × V

DDQ

) 1.3 1.5 1.7 V

Termination voltage (V

REF

= VTT = 0.45 × V

DDQ

) V

REF

–50mV V

REFVREF

+50mV V

Input voltage 0 V

AC high-level input voltage All inputs V

REF

+400mV V

AC low-level input voltage All inputs V

REF

–400mV V

DC high-level input voltage All inputs V

REF

+200mV V

DC low-level input voltage All inputs V

REF

–200mV V

High-level output current –20

Low-level output current 20

Operating free-air temperature 0 70

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS V

MIN TYP†MAX UNIT

II = –18 mA 3 V –1.2 V IOH = –100 µA 3 V to 3.6 V VCC–0.2

IOH = –16 mA

2.2

IOH = –20 mA

3 V

2.1

IOL = 100 µA 3 V to 3.6 V 0.2

IOL = 16 mA

0.5

IOL = 20 mA

3 V

0.55

VI = 2.1 V or 0.9 V

±40 µA

VI = 3.6 V or 0

REF

= 1.3 V or 1.7

3.6 V

±1.2 mA

VI = 2.1 V or 0.9 V

±5

ata inputs,

VI = 3.6 V or 0

REF

= 1.3 V or 1.7

3.6 V

±5

µA

VI = 2.1 V or 0.9 V

±150

CLK

VI = 3.6 V or 0

REF

1.3 V or 1.7 V

3.6 V

±4 mA

REF

= 1.3 V or 1.7 V 3.6 V ±150 µA

VO = 0.9 V or 2.1 V

±10

VO = 0 or 3.6 V

3.6 V

±10

VI = 2.1 V or 0.9 V

VI = 3.6 V or 0

3.6 V

Control inputs

2.5 p

A port

= 2.1 V or 0.9

3.3 V

Y port VO = 2.1 V or 0.9 V 3.3 V 3 pF

†

All typical values are at VCC = 3.3 V, TA = 25°C.

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SN74SSTL16837A 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

SCBS675G – SEPTEMBER 1996 – REVISED SEPTEMBER 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)

VCC = 3.3 V

± 0.3 V

UNIT

MIN MAX

clock

Clock frequency 200 MHz

LE high 2.5

twPulse duration

CLK high or low 2.5

A before CLK↑ LE low 1.5

Setup time

CLK high 1.5

A before LE↓

CLK low 2

A after CLK↑ LE low 1

thHold time

A after LE↓ 1

switching characteristics over recommended operating free-air temperature range, Class I, V

REF

= VTT = V

DDQ

X 0.45 and CL = 10 pF (unless otherwise noted) (see Figure 1)

PARAMETER

FROM

VCC = 3.3 V

± 0.3 V

UNIT

(INPUT)

(OUTPUT)

MIN MAX

max

200 MHz

A 1.1 4

1.5 4.1

CLK 1 3

Y 1.8 5.5 ns

dis

Y 1.8 6 ns

switching characteristics over recommended operating free-air temperature range, Class II, V

REF

= VTT = V

DDQ

X 0.45 and CL = 30 pF (unless otherwise noted) (see Figure 1)

PARAMETER

FROM

VCC = 3.3 V

± 0.3 V

UNIT

(INPUT)

(OUTPUT)

MIN MAX

max

200 MHz

A 1.1 4.2

1.5 4.3

CLK 1 3.2

Y 1.8 5.5 ns

dis

Y 1.8 6 ns

Page 5

SN74SSTL16837A

20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER

WITH 3-STATE OUTPUTS

SCBS675G – SEPTEMBER 1996 – REVISED SEPTEMBER 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

LOAD CIRCUIT

Data Input

Timing Input

1.9 V

1.1 V

1.9 V

1.1 V

1.9 V

1.1 V

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

Output

Waveform 1

(see Note B)

Output

Waveform 2

(see Note B)

PZL

PZH

PLZ

PHZ

1.1 V

1.9 V

Output

Control

PLH

PHL

1.9 V

1.1 V

Input

Output

25 Ω = SSTL_3 Class II 50 Ω = SSTL_3 Class I

CL = 10 pF or 30 pF

(see Note A)

Test Point

25 Ω

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 1 ns, tf≤ 1 ns. D. The outputs are measured one at a time with one transition per measurement. E. VTT = V

REF

= VCC × 0.45

F. t

PLZ

and t

PHZ

are the same as t

dis

G. t

PZL

and t

PZH

are the same as ten.

H. t

PHL

and t

PLH

are the same as tpd.

1.5 V

1.5 V 1.5 V

1.1 V

1.9 V 1.9 V

Figure 1. Load Circuit and Voltage Waveforms

Page 6

IMPORTANT NOTICE

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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

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