Datasheet SN74LVCH32245AGKER Datasheet (Texas Instruments)

Page 1
SN74LVCH32245A
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS616A – OCTOBER 1998 – REVISED JUNE 1999
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D
Widebus
Family
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
T ypical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, TA = 25°C
D
T ypical V
OHV
(Output VOH Undershoot)
> 2 V at V
CC
= 3.3 V, TA = 25°C
D
I
off
Supports Partial-Power-Down-Mode
Operation
D
Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With
3.3-V V
CC
)
D
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
D
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
D
Packaged in Plastic Fine-Pitch Ball Grid Array Package
description
This 32-bit (dual-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V VCC operation. The SN74LVCH32245A is designed for asynchronous communication between data buses. The
control-function implementation minimizes external timing requirements. This device can be used as four 8-bit transceivers, two 16-bit transceivers, or one 32-bit transceiver. It allows
data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE
) input can be used to disable the device so that the
buses are effectively isolated. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment. This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down. T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74LVCH32245A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OE DIR
OPERATION
L L B data to A bus L H A data to B bus H X Isolation
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Page 2
SN74LVCH32245A 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS616A – OCTOBER 1998 – REVISED JUNE 1999
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
GKE PACKAGE
(TOP VIEW)
JHGFEDCBA
2 1
3
4
6 5
PNMLK TR
terminal assignments
6 1A2 1A4 1A6 1A8 2A2 2A4 2A6 2A7 3A2 3A4 3A6 3A8 4A2 4A4 4A6 4A7 5 1A1 1A3 1A5 1A7 2A1 2A3 2A5 2A8 3A1 3A3 3A5 3A7 4A1 4A3 4A5 4A8 4 1OE GND V
CC
GND GND V
CC
GND 2OE 3OE GND V
CC
GND GND V
CC
GND 4OE
3 1DIR GND V
CC
GND GND V
CC
GND 2DIR 3DIR GND V
CC
GND GND V
CC
GND 4DIR
2 1B1 1B3 1B5 1B7 2B1 2B3 2B5 2B8 3B1 3B3 3B5 3B7 4B1 4B3 4B5 4B8 1 1B2 1B4 1B6 1B8 2B2 2B4 2B6 2B7 3B2 3B4 3B6 3B8 4B2 4B4 4B6 4B7
A B C D E F G H J K L M N P R T
Page 3
SN74LVCH32245A
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS616A – OCTOBER 1998 – REVISED JUNE 1999
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic diagram (positive logic)
To Seven Other Channels
1DIR
1A1
1B1
1OE
To Seven Other Channels
2DIR
2A1
2B1
2OE
A3
A5
H3
E5
A4
A2
H4
E2
To Seven Other Channels
3DIR
3A1
3B1
3OE
To Seven Other Channels
4DIR
4A1
4B1
4OE
J3
J5
T3
N5
J4
J2
T4
N2
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
–0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
:(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each V
CC
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 3) 40°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
Page 4
SN74LVCH32245A 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS616A – OCTOBER 1998 – REVISED JUNE 1999
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN MAX UNIT
pp
Operating 1.65 3.6
VCCSuppl
y v
oltage
Data retention only 1.5
V
VCC = 1.65 V to 1.95 V 0.65 × V
CC
V
IH
High-level input voltage
VCC = 2.3 V to 2.7 V
1.7
V VCC = 2.7 V to 3.6 V 2 VCC = 1.65 V to 1.95 V 0.35 × V
CC
V
IL
Low-level input voltage
VCC = 2.3 V to 2.7 V
0.7
V VCC = 2.7 V to 3.6 V 0.8
V
I
Input voltage 0 5.5 V
p
High or low state 0 V
CC
VOOutput voltage
3 state 0 5.5
V
VCC = 1.65 V –4
p
VCC = 2.3 V –8
IOHHigh-level output current
VCC = 2.7 V –12
mA
VCC = 3 V –24 VCC = 1.65 V 4
p
VCC = 2.3 V 8
IOLLow-level output current
VCC = 2.7 V 12
mA
VCC = 3 V 24
t/v Input transition rise or fall rate 5 ns/V T
A
Operating free-air temperature –40 85 °C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
Page 5
SN74LVCH32245A
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS616A – OCTOBER 1998 – REVISED JUNE 1999
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS
V
CC
MIN TYP†MAX UNIT
IOH = –100 µA 1.65 V to 3.6 V VCC–0.2 IOH = –4 mA 1.65 V 1.2 IOH = –8 mA 2.3 V 1.7
V
OH
2.7 V 2.2
V
I
OH
= –12
mA
3 V 2.4 IOH = –24 mA 3 V 2.2 IOL = 100 µA 1.65 V to 3.6 V 0.2 IOL = 4 mA 1.65 V 0.45
V
OL
IOL = 8 mA 2.3 V 0.7
V IOL = 12 mA 2.7 V 0.4 IOL = 24 mA 3 V 0.55
I
I
Control inputs VI = 0 to 5.5 V 3.6 V ±5 µA
VI = 0.58 V
25
VI = 1.07 V
1.65 V
–25
VI = 0.7 V
45
I
I(hold)
VI = 1.7 V
2.3 V
–45
µA
()
VI = 0.8 V
75
VI = 2 V
3 V
–75
VI = 0 to 3.6 V
3.6 V ±500
I
off
VI or VO = 5.5 V 0 ±10 µA
I
OZ
§
VO = 0 to 5.5 V 3.6 V ±10 µA VI = VCC or GND
20
I
CC
3.6 V VI 5.5 V
I
O
=
0
3.6 V
20
µ
A
I
CC
One input at VCC – 0.6 V, Other inputs at VCC or GND 2.7 V to 3.6 V 500 µA
C
i
Control inputs VI = VCC or GND 3.3 V 5 pF
C
io
A or B ports VO = VCC or GND 3.3 V 7.5 pF
All typical values are at VCC = 3.3 V, TA = 25°C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§
For I/O ports, the parameter IOZ includes the input leakage current, but not I
I(hold)
.
This applies in the disabled state only.
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3)
PARAMETER
FROM
TO
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
(INPUT)
(OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
t
pd
A or B B or A
# # # #
4.7 1 4 ns
t
en
OE
A or B
# # # #
6.7 1.5 5.5 ns
t
dis
OE
A or B
# # # #
7.1 1.5 6.6 ns
t
sk(o)
||
1.5 ns
#
This information was not available at the time of publication.
||
Skew between any two outputs of the same package switching in the same direction
Page 6
SN74LVCH32245A 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS616A – OCTOBER 1998 – REVISED JUNE 1999
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
operating characteristics, T
A
= 25°C
TEST
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
PARAMETER
CONDITIONS
TYP TYP TYP
UNIT
Power dissipation capacitance
Outputs enabled
40
p
C
pd
per transceiver
Outputs disabled
f
= 10 MHz
4
pF
This information was not available at the time of publication.
PARAMETER MEASUREMENT INFORMATION
V
CC
= 1.8 V ± 0.15 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
1 k
1 k
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
V
CC
0 V
0 V
t
w
V
CC
V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
0 V
V
CC
VCC/2
t
PHL
VCC/2 VCC/2
V
CC
0 V
V
OH
V
OL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
t
PLH
2 × V
CC
V
CC
Figure 1. Load Circuit and Voltage Waveforms
Page 7
SN74LVCH32245A
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS616A – OCTOBER 1998 – REVISED JUNE 1999
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.5 V ± 0.2 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
V
CC
0 V
0 V
t
w
V
CC
V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
0 V
V
CC
VCC/2
t
PHL
VCC/2 VCC/2
V
CC
0 V
V
OH
V
OL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
t
PLH
2 × V
CC
V
CC
Figure 2. Load Circuit and Voltage Waveforms
Page 8
SN74LVCH32245A 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS616A – OCTOBER 1998 – REVISED JUNE 1999
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.7 V AND 3.3 V ± 0.3 V
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
6 V
Open
GND
500
500
t
PLH
t
PHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V1.5 V
1.5 V 1.5 V
2.7 V
0 V
1.5 V 1.5 V
V
OH
V
OL
0 V
1.5 V VOL + 0.3 V
1.5 V
VOH – 0.3 V
0 V
1.5 V
2.7 V
0 V
1.5 V 1.5 V 0 V
2.7 V
0 V
1.5 V 1.5 V
t
w
Input
2.7 V
2.7 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Output
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
Page 9
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