Datasheet SN74LVC2G74 Datasheet (TEXAS INSTRUMENTS)

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DCT OR DCU PACKAGE

(TOP VIEW)

1
2
3
4

8
7
6
5

CLK

D

Q

GND

V

CC

PRE
CLR
Q

4
3
2
1

5
6
7
8

GND

Q
D

CLK

Q
CLR
PRE
V

CC

YEA, YEP, YZA, OR YZP PACKAGE

(BOTTOM VIEW)

查询SN74LVC2G74DCTR供应商

FEATURES

• Available in the Texas Instruments

NanoStar™ and NanoFree™ Packages

• Supports 5-V V

• Inputs Accept Voltages to 5.5 V

• Max tpdof 5.9 ns at 3.3 V

• Low Power Consumption, 10- µ A Max I

• ± 24-mA Output Drive at 3.3 V

• Typical V

<0.8 V at V

• Typical V

>2 V at V

• I

off

OLP

CC

OHV

CC

Supports Partial-Power-Down Mode

Operation

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)

CC

(Output Ground Bounce)

= 3.3 V, T

(Output V

= 3.3 V, T

Operation

= 25 ° C

A

Undershoot)

OH

= 25 ° C

A

SN74LVC2G74

SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH CLEAR AND PRESET

SCES203K – APRIL 1999 – REVISED JUNE 2005

CC

DESCRIPTION/ORDERING INFORMATION

This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V V
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the

die as the package.

T

A

–40°C to 85°C

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.

DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).

operation.

CC

ORDERING INFORMATION

PACKAGE

NanoStar™
WCSP (DSBGA) – YEA

NanoFree™
WCSP (DSBGA) – YZA (Pb-free)

NanoStar™ – WCSP (DSBGA)

0.23-mm Large Bump – YEP
NanoFree™ – WCSP (DSBGA)

0.23-mm Large Bump – YZP (Pb-free)
SSOP – DCT Reel of 3000 SN74LVC2G74DCTR C74_ _ _

VSSOP – DCU C74_

(1)

Reel of 3000 _ _ _CP_

Reel of 3000 SN74LVC2G74DCUR
Reel of 250 SN74LVC2G74DCUT

ORDERABLE PART NUMBER TOP-SIDE MARKING

SN74LVC2G74YEAR

SN74LVC2G74YZAR

SN74LVC2G74YEPR

SN74LVC2G74YZPR

(2)

NanoStar, NanoFree are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 1999–2005, Texas Instruments Incorporated

www.ti.com

TG

C

C

TG

C

C

TG

C

C

C

TG

C

C

PRE

CLK

D

CLR

Q

Q

C

7

2

6

5

3

1

SN74LVC2G74
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET

SCES203K – APRIL 1999 – REVISED JUNE 2005

DESCRIPTION/ORDERING INFORMATION (CONTINUED)

A low level at the preset ( PRE) or clear ( CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.

This device is fully specified for partial-power-down applications using I
preventing damaging current backflow through the device when it is powered down.

FUNCTION TABLE

INPUTS OUTPUTS

PRE CLR CLK D Q Q

L H X X H L
H L X X L H
L L X X H
H H ↑ H H L
H H ↑ L L H
H H L X Q

. The I

off

circuitry disables the outputs,

off

(1)

0

(1)

H

Q

0

(1) This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive

(high) level.

LOGIC DIAGRAM (POSITIVE LOGIC)

2

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SN74LVC2G74

SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH CLEAR AND PRESET

SCES203K – APRIL 1999 – REVISED JUNE 2005

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

V

Supply voltage range –0.5 6.5 V

CC

V

Input voltage range

I

V

Voltage range applied to any output in the high-impedance or power-off state

O

V

Voltage range applied to any output in the high or low state

O

I

Input clamp current VI< 0 –50 mA

IK

I

Output clamp current VO< 0 –50 mA

OK

I

Continuous output current ±50 mA

O

Continuous current through V

θ

Package thermal impedance

JA

T

Storage temperature range –65 150 °C

stg

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The value of V
(4) The package thermal impedance is calculated in accordance with JESD 51-7.

(2)

is provided in the recommended operating conditions table.

CC

(1)

MIN MAX UNIT

–0.5 6.5 V

(2)

(2) (3)

or GND ±100 mA

CC

–0.5 6.5 V
–0.5 V

DCT package 220

(4)

DCU package 227
YEA/YZA package 140
YEP/YZP package 102

CC

+ 0.5 V

°C/W

3

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SN74LVC2G74
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET

SCES203K – APRIL 1999 – REVISED JUNE 2005

Recommended Operating Conditions

V

V

V

V
V

I

OH

I

OL

∆ t/ ∆ v Input transition rise or fall rate V

T

(1) All unused inputs of the device must be held at V

Supply voltage V

CC

High-level input voltage V

IH

Low-level input voltage V

IL

Input voltage 0 5.5 V

I

Output voltage 0 V

O

High-level output current –16 mA

Low-level output current 16 mA

Operating free-air temperature –40 85 °C

A

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

(1)

or GND to ensure proper device operation. Refer to the TI application report,

CC

MIN MAX UNIT

Operating 1.65 5.5
Data retention only 1.5
V

= 1.65 V to 1.95 V 0.65 × V

CC

V

= 2.3 V to 2.7 V 1.7

CC

V

= 3 V to 3.6 V 2

CC

V

= 4.5 V to 5.5 V 0.7 × V

CC

V

= 1.65 V to 1.95 V 0.35 × V

CC

V

= 2.3 V to 2.7 V 0.7

CC

V

= 3 V to 3.6 V 0.8

CC

V

= 4.5 V to 5.5 V 0.3 × V

CC

V

= 1.65 V –4

CC

V

= 2.3 V –8

CC

V

= 3 V

CC

V

= 4.5 V –32

CC

V

= 1.65 V 4

CC

V

= 2.3 V 8

CC

V

= 3 V

CC

V

= 4.5 V 32

CC

V

= 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20

CC

= 3.3 V ± 0.3 V 10 ns/V

CC

V

= 5 V ± 0.5 V 5

CC

CC

CC

CC

CC

V

CC

–24

24

4

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SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS V

IOH= –100 µ A 1.65 V to 5.5 V V
IOH= –4 mA 1.65 V 1.2

V

OH

V

OL

Data or

I

I

control inputs

I

off

I

CC

∆ I

CC

C

i

(1) All typical values are at V

IOH= –8 mA 2.3 V 1.9
IOH= –16 mA 2.4
IOH= –24 mA 2.3
IOH= –32 mA 4.5 V 3.8
IOL= 100 µ A 1.65 V to 5.5 V 0.1
IOL= 4 mA 1.65 V 0.45
IOL= 8 mA 2.3 V 0.3
IOL= 16 mA 0.4
IOL= 24 mA 0.55
IOL= 32 mA 4.5 V 0.55

VI= 5.5 V or GND 0 to 5.5 V ±5 µ A
VIor VO= 5.5 V 0 ±10 µ A

VI= 5.5 V or GND, IO= 0 1.65 V to 5.5 V 10 µ A
One input at V
VI= V

CC

= 3.3 V, TA= 25°C.

CC

– 0.6 V, Other inputs at V

CC

or GND 3 V to 5.5 V 500 µ A

CC

or GND 3.3 V 5 pF

WITH CLEAR AND PRESET

SCES203K – APRIL 1999 – REVISED JUNE 2005

CC

3 V

3 V

MIN TYP

– 0.1

CC

SN74LVC2G74

(1)

MAX UNIT

V

V

Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )

V

= 1.8 V V

CC

± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V

MIN MAX MIN MAX MIN MAX MIN MAX

f

clock

t

Pulse duration ns

w

t

Setup time, before CLK ↑ ns

su

t

Hold time, data after CLK ↑ 0 0.3 1.2 0.5 ns

h

CLK 6.2 2.7 2.7 2
PRE or CLR low 6.2 2.7 2.7 2
Data 2.9 1.7 1.3 1.1
PRE or CLR inactive 1.9 1.4 1.2 1

80 175 175 200 MHz

= 2.5 V V

CC

= 3.3 V V

CC

CC

Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )

V

= 1.8 V V

PARAMETER UNIT

f

max

t

pd

FROM TO

(INPUT) (OUTPUT)

CLK

Q 4.8 13.4 2.2 7.1 2.2 5.9 1.4 4.1
Q 6 14.4 3 7.7 2.6 6.2 1.6 4.4 ns

CC

± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V

MIN MAX MIN MAX MIN MAX MIN MAX

80 175 175 200 MHz

PRE or CLR Q or Q 4.4 12.9 2.3 7 1.7 5.9 1.6 4.1

= 2.5 V V

CC

= 3.3 V V

CC

CC

= 5 V

UNIT

= 5 V

5

www.ti.com

SN74LVC2G74
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET

SCES203K – APRIL 1999 – REVISED JUNE 2005

Operating Characteristics

TA= 25°C

PARAMETER TEST CONDITIONS UNIT

C

Power dissipation capacitance f = 10 MHz 35 35 37 40 pF

pd

V

= 1.8 V V

CC

TYP TYP TYP TYP

= 2.5 V V

CC

= 3.3 V V

CC

= 5 V

CC

6

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V

M

t

h

t

su

From Output

Under Test

C

L

(see Note A)

LOAD CIRCUIT

S1

V

LOAD

Open

GND

R

L

R

L

Data Input

Timing Input

V

I

0 V

V

I

0 V

0 V

t

w

Input

VOLTAGE W AVEFORMS

SETUP AND HOLD TIMES

VOLTAGE W AVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE W AVEFORMS

PULSE DURATION

t

PLH

t

PHL

t

PHL

t

PLH

V

OH

V

OH

V

OL

V

OL

V

I

0 V

Input

Output
Waveform 1
S1 at V

LOAD

(see Note B)

Output
Waveform 2

S1 at GND

(see Note B)

V

OL

V

OH

t

PZL

t

PZH

t

PLZ

t

PHZ

V

LOAD

/2

0 V

VOL + V

∆

VOH − V

∆

≈0 V

V

I

VOLTAGE W AVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

V

LOAD

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. t

PLZ

and t

PHZ

are the same as t

dis

.

F. t

PZL

and t

PZH

are the same as ten.

G. t

PLH

and t

PHL

are the same as tpd.

H. All parameters and waveforms are not applicable to all devices.

Output

Control

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

I

V

M

V

M

1.8 V ± 0.15 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V
5 V ± 0.5 V

1 kΩ
500 Ω
500 Ω
500 Ω

V

CC

R

L

2 × V

CC

2 × V

CC

6 V

2 × V

CC

V

LOAD

C

L

30 pF
30 pF
50 pF
50 pF

0.15 V

0.15 V

0.3 V

0.3 V

V

∆

V

CC

V

CC

3 V

V

CC

V

I

VCC/2
VCC/2

1.5 V

VCC/2

V

M

tr/t

f

≤2 ns

≤2 ns
≤2.5 ns
≤2.5 ns

INPUTS

SN74LVC2G74

SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH CLEAR AND PRESET

SCES203K – APRIL 1999 – REVISED JUNE 2005

PARAMETER MEASUREMENT INFORMATION

Figure 1. Load Circuit and Voltage Waveforms

7

PACKAGE OPTION ADDENDUM

www.ti.com

30-Aug-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

SN74LVC2G74DCTR ACTIVE SM8 DCT 8 3000 Pb-Free

SN74LVC2G74DCTRE4 ACTIVE SM8 DCT 8 3000 Pb-Free

SN74LVC2G74DCUR ACTIVE US8 DCU 8 3000 Pb-Free

SN74LVC2G74DCURE4 ACTIVE US8 DCU 8 3000 Pb-Free

SN74LVC2G74DCURG4 ACTIVE US8 DCU 8 3000 Green (RoHS &

no Sb/Br)

SN74LVC2G74DCUT ACTIVE US8 DCU 8 250 Pb-Free

SN74LVC2G74DCUTE4 ACTIVE US8 DCU 8 250 Pb-Free

SN74LVC2G74YEAR ACTIVE WCSP YEA 8 3000 TBD SNPB Level-1-260C-UNLIM
SN74LVC2G74YEPR ACTIVE WCSP YEP 8 3000 TBD SNPB Level-1-260C-UNLIM
SN74LVC2G74YZAR ACTIVE WCSP YZA 8 3000 Pb-Free

SN74LVC2G74YZPR ACTIVE WCSP YZP 8 3000 Pb-Free

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

SNAGCU Level-1-260C-UNLIM

SNAGCU Level-1-260C-UNLIM

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MPDS049B – MA Y 1999 – REVISED OCT OBER 2002

DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE P ACKAGE

0,65

PIN 1
INDEX AREA

0,30

0,15

8

1

3,15

2,75

5

2,90
2,70

4

1,30 MAX

M

0,13

4,25
3,75

Seating Plane

0,15 NOM

0° – 8°

Gage Plane

0,25

0,60
0,20

0,10
0,00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion
D. Falls within JEDEC MO-187 variation DA.

0,10

4188781/C 09/02

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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